JPH03154577A - Weighted mean processing circuit - Google Patents

Abstract

PURPOSE:To make the movement of all patterns to be synthesized smooth and to improve the coding efficiency by reading preceding pattern information corresponding to pattern information inputted to a weighted mean processing section and controlling the read and write state of plural frame memories to write the relevant pattern information from the weighted mean processing section. CONSTITUTION:A frame memory control section 53 reads preceding pattern information corresponding to pattern information inputted to a weighted means processing section 52 and writes the relevant pattern information from the weighted mean processing section 52. That is, when pattern information is inputted, the relevant preceding is read from a frame memory 51-i (i=1-n), the weighted mean processing section 52 uses the pattern information to apply the weighted mean processing and then the result is written in the frame memory 51-i extracted now as the preceding pattern information to revise the content of the frame memory 51-i. Thus, the movement of all patterns to be synthesized is made smooth and the coding efficiency is improved.

Description

[Detailed description of the invention] [Industrial application field] The present invention is useful when combining different screen information.

The present invention relates to a weighted average processing circuit for performing weighted average processing on such screen information.

In recent years, in conjunction with the diversification of image transmission devices, video conferencing systems have frequently adopted a method of compositing, for example, a full view of the meeting and a partially enlarged close view. When compositing these images, it is necessary to perform weighted average processing on these images. here,
Weighted average processing means that the previous screen information is divided into X)1. If the current screen information is X 1 r and the weighting coefficient is K, then KXl+ (K-
1) Processing that performs the calculation Xi-1.

For example, when transmitting moving images at a low bit rate, frames are subsampled, which results in coarse motion. Therefore, before performing subsampling, the data of the invalid frame is added to the data of the valid frame and weighted average processing is performed to smooth the motion. Further, in this case, data that is similar to the data of the previous frame is output, so that it is easy to predict the data to be encoded in the encoder.

[Prior Art] FIG. 4 is a block diagram of the screen transmitting side of a video conference system.

IB is a television camera, 2A and 2B are analog/digital converters (A/D converters), and 3 is a selector.

4 is a time division multiplexing circuit, 5 is a weighted average processing circuit, and 6 is an encoding circuit, thus, the television camera IA.

Different analog screen information taken in 1B (Screen ■, ■
) is digitally converted by the A/D converters 2A and 2B, one of the screen information is selected by the selector 3, and then subjected to time division multiplexing by the time division multiplexing circuit 4.
The weighted average processing circuit 5 performs weighted average processing, and the encoded signal is encoded by the encoding circuit 6.

By the way, as shown in FIG. 5, the weighted average processing circuit 5 has a frame memory 51. It has a weighted average processing section 52.

Here, the frame memory 51 stores only information about, for example, a screen in units of frames.

The weighted average processing unit 52 outputs screen information obtained by performing weighted average processing on the previous screen information X1-1 from the frame memory 51 and the subsequent screen information (input) xl. Coefficient setters 521 and 522 that multiply the coefficient by 1-K and output the result, and each coefficient setter 521 and 5
22, and an adder 523 for adding the outputs from 22.

With such a configuration, for example, television cameras IA, IB
When combining two screens from each TV camera IA,
The signals from IB (screen ■, ■) are input alternately,
Since there is only one frame memory 51, for example, the screen
When the information on the previous screen is received, the previous screen information from the frame memory 51 is taken out, weighted average processing is performed using this information, and this information is written into the frame memory 51 again. However, when the information from screen ■ comes in, the data is different, so even if weighted average processing is performed, only meaningless data will be obtained. Therefore, it is not necessary to read or write the previous screen information in the frame memory 51. Neither.

That is, weighted average processing is not performed.

The states of the input data of the weighted average processing section 52, the data of the frame memory 51, and the output data of the weighted average processing section 52 at this time are shown in FIGS. 6(a) to 6(c).

[Problems to be Solved by the Invention] As described above, since the conventional weighted average processing circuit has only one frame memory, it is only possible to perform weighted average processing on one screen. In the case of two-screen synthesis, the other screen is output to the encoding unit without performing weighted average processing. Therefore, it is difficult to make the movement of the other screen smooth, and there is a risk that the encoding efficiency will deteriorate.

The present invention was made in view of these problems, and
It has a frame memory equal to the number of frames to be synthesized, but uses a common weighted average processing unit to smooth the movement of all the frames to be synthesized and increase encoding efficiency. The purpose is to provide an average processing circuit.

[Means to solve the problem] FIG. 1 is a block diagram of the principle of the present invention.

In this FIG. 1, 51-1. ..., 51-n are frame memories, and each frame memory 51-i (i=
1. . . t n) can separately store each of the different screen information to be combined with each other.

52 is a weighted average processing unit, and this weighted average processing unit 52 is
It outputs screen information obtained by subjecting the previous screen information and subsequent screen information from the frame memory 51-1 to weighted average processing.

Reference numeral 53 denotes a frame memory control unit, and this frame memory control unit 53 reads the previous screen information corresponding to the screen information input to the weighted average processing unit 52, and reads the corresponding screen information from the weighted average processing unit 52. To write,
It controls the read and write states of the plurality of frame memories 51-1, respectively.

[Function] In the above-described weighted average processing circuit of the present invention, the frame memory control unit 53 reads the previous screen information corresponding to the screen information input to the weighted average processing unit 52, and also reads the previous screen information from the weighted average processing unit 52. The corresponding screen information is written.

As a result, when certain screen information is input, the previous screen information corresponding to this is read out from the frame memory 51-1, and the weighted average processing section 52 uses this screen information to perform weighted average processing. administered. Thereafter, the screen information after this weighted average processing is written as the previous screen information into the frame memory 51-1 just taken out, and the contents of this frame memory 51-1 are updated.

Note that even when other screen information is input, the previous screen information corresponding to this is stored in the frame memory 5l-j (j≠i; 1.
. . tn), and the weighted average processing unit 52 performs weighted average processing using these screen information. Thereafter, the screen information after this weighted average processing is written as the previous screen information into the frame memory 51-j just taken out, and the contents of this frame memory 51-j are updated.

[Example] The present invention will be described in detail below with reference to two drawings.

Now, in the case of this embodiment as well, as described above with reference to FIG. 2A
, 2B performs digital conversion, the selector 3 selects one of the screen information, and the time division multiplexing circuit 4 converts it into digital data.
An example will be described in which, after time division multiplexing is performed, weighted average processing is performed in the weighted average processing circuit 5, and then encoding is performed in the encoding circuit 6.

In addition, TV cameras LA, IB, A/D converters 2A, 2
B. Selector 32 time division multiplex circuit 4. The encoding circuit 6 is
Since it is the same as the conventional one, its explanation will be omitted.

By the way, a weighted average processing circuit according to the present invention is used as the weighted average processing circuit 5, and as shown in FIG. 51-1.51-2. Weighted average processing unit 52. It has a frame memory control section 53.

Here, the frame memory 51-1 is capable of storing information on the screen (2), and the frame memory 51-2 is capable of storing information on the screen (2) to be combined with the screen (2).

The weighted average processing unit 52 includes frame memories 51-1;
Previous screen information from -2 X 11-1; X 2 L-
+ and subsequent screen information (input) XIi:X21 to output screen information subjected to weighted average processing, and for this purpose, a coefficient setter 521 multiplies the input information by 2 and outputs the coefficient Kl; , a coefficient setter 522 that multiplies input information by a coefficient 1-Kl ; 1- by 2, and an adder 523 that adds the outputs from each coefficient setter 521 and 522. Note that each coefficient setter 521,
522 has a ROM that stores different coefficient values, and the coefficients can be switched using a control signal from a frame memory control unit 53, which will be described later.

The frame memory control unit 53 receives the switching signal from the time division multiplexing circuit 4 and reads out the previous screen information corresponding to the screen information input to the weighted average processing unit 52.
In order to write the corresponding screen information from the weighted average processing section 52, the reading and writing states of the frame memory 51-1 and 52-2 are respectively controlled. Note that this frame memory control unit 53 uses, for example, the above-mentioned frame memory write and read control signals,
Coefficient switching of coefficient setters 521 and 522 is also controlled.

With the above configuration, when combining screens ■ and ■, for example, when the information of screen ■ is first input, the previous screen information of this screen ■ is read from the frame memory 51-1, and the weighted average processing section At 52, a weighted average process is performed using this screen information. Thereafter, the screen information after this weighted average processing is sent to the encoding circuit 6 side, and is written as the previous screen information into the frame memory 51-1 just taken out.
-Update the contents of 1.

In addition, when information on another screen (■) is input, the previous screen information corresponding to this is read out from the frame memory 51-2, and the weighted average processing section 52 uses this screen information and performs switching. Weighted average processing is performed using the coefficients.

After that, the screen information after this weighted average processing is sent to the encoding circuit 6 side, and is written as the previous screen information into the frame memory 51-2 just taken out. Update the contents of.

Here, writing and reading control of each of the frame memories 51-1 and 51-2 is performed by the frame memory control unit 53.
The writing and reading timing by this frame memory control unit 53 is shown in FIG. 3 (a).
) to (f). Note that WEI is a write control signal for the frame memory 51-1, REI is a read control signal for the frame memory 51-1, WF2 is a write control signal for the frame memory 51-2, and RE2 is a read control signal for the frame memory 51-2. be.

As described above, according to this embodiment, there are as many frame memories 51-1 and 51-2 as there are frames to be synthesized, that is, two frame memories 51-1 and 51-2.
Since the weighted average processing section 52 uses a common one,
Without significantly increasing the circuit scale, it is possible to smooth the movements of all the screens (2) and (3) to be synthesized, and increase encoding efficiency.

Note that the number of screens to be combined may be three or more, and in this case, frame memories are prepared for the number of screens to be combined.

Further, the coefficients in the weighted average processing section 52 may be the same for each screen, and in this case, coefficient switching is not necessary.

[Effects of the Invention] As detailed above, the weighted average processing circuit of the present invention has frame memories equal to the number of screens to be synthesized, but since a common weighted average processing unit is used, the circuit This has the advantage that the motion of all screens to be synthesized can be smoothed and encoding efficiency can be increased without causing a significant increase in scale.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a diagram of writing by a frame memory control unit. FIG. 4 is a block diagram of the screen transmission side of the video conference system; FIG. 5 is a block diagram of a conventional example; and FIG. 6 is a diagram illustrating the operation of the conventional example. In the figure, IA and IB are television cameras, 2A and 2B are A/D converters, 3 is a selector, 4 is a time division multiplexing circuit, 5 is a weighted average processing circuit, 6 is an encoding circuit, and 51-1 is a frame memory. , 52 is a weighted average processing unit. 53 is a frame memory control unit, and 521 and 522 are coefficient setters. 523 is an adder.

Claims (1)

[Claims] A plurality of frame memories (51-i) capable of separately storing different screen information to be combined with each other; a weighted average processing unit (52) that outputs screen information subjected to weighted average processing from the screen information;
2) in order to read the previous screen information corresponding to the screen information input to the frame memory 2) and write the corresponding screen information from the weighted average processing section (52). 1. A weighted average processing circuit comprising a frame memory control section (53) that controls respective write states.