JPH03154547A - Carrier recovery circuit - Google Patents

Abstract

PURPOSE:To facilitate analysis and design by detecting a phase of an input multi-value amplitude phase modulation signal and using digital signal processing to recover the carrier thereby making the phase comparison characteristic linear. CONSTITUTION:A multi-value amplitude phase modulation signal (multivalue APSK modulation signal) inputted to an input terminal 1 is inputted to a demodulation means 2 and an input phase detection means 4 and the means 2 uses a recovered carrier from a controlled oscillation means 9 to demodulate the input multi-value APSK signal into a multi-value digital signal. The multi-value digital signal is inputted to an error voltage selection means 7 and outputted to output terminals 3a, 3b. The input phase signal outputted from the input phase detection means 4 is inputted to subtractor 5 and the subtractor 5 calculates a difference between the phase of the input phase signal and the phase of the recovered carrier being an output of the control oscillation means 9, outputs the result to an error voltage generating means 6 and the input output characteristic of the means 6 is brought into a characteristic such as a repetitive function of a pi/2 period and the phase comparison characteristic is made linear. Thus, the characteristic analysis of the phase locked loop is easily implemented and the design in matching with the request characteristic is facilitated.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a carrier regeneration circuit that regenerates a reference carrier wave used for demodulation from a multilevel amplitude phase modulation signal.

BACKGROUND OF THE INVENTION Conventional circuits for regenerating a reference carrier wave used for demodulation from a multilevel amplitude phase modulation signal include a method of directly regenerating a carrier wave from a reproduced signal by a Costas method, an inverse modulation method, or the like. In particular, when using a modulation method such as 16-level quadrature amplitude modulation (16QAM) in which the minimum phase difference between signal points is less than π/2, the reference carrier regeneration circuit only needs to adjust the phase at every integer multiple of π/2. Since it is required to have a reference point, π/
It is necessary to avoid the influence of signal points that do not have a phase that is an integral multiple of 2. Therefore, using the Costas method, the four-phase phase change jJ
A selection-based '4I+1 type carrier regeneration circuit was used, which selected only the signal points with the same phase as the W (4PSK) signal points, and used previously stored control information for other signal points (for example, Izumi Horiyoshi et al.: Carrier recovery circuit for carrier selection control type 16QAM'', Transactions of the Institute of Electronics and Communication Engineers '80/7
Vol. J63-B No. 7, Institute of Electronics, Information and Communication Engineers, July 1982).

Another method is to use a phase-locked loop (PLL) that detects the phase of an input signal and creates a sinusoidal phase signal synchronized with the detected phase information through digital signal processing. There is a digital signal processing type carrier wave regeneration circuit that introduces a function to support multilevel APSK modulated signals (for example, Masafumi Hagiwara et al.: “'
Digital signal processing TAN format 2nd order DPLL and N-phase PS
"Application to synchronous demodulation circuit for K and 16QAM", Transactions of Institute of Electronics and Communication Engineers '86/12 Vol, J69-t3
Nα12, Institute of Electronics, Information and Communication Engineers, 1986.12). When the carrier wave of a multilevel APSK signal is regenerated by this method, there is a drawback that a so-called pseudo-pulling phenomenon occurs in which signal points that are not in the same phase as the 4PSK signal points are pulled into positions in the same phase. On the other hand, is the phase comparison characteristic function different? Which PL using jf number of PLLs?
A method has been proposed that determines whether the output of L is correct and uses the correctly synchronized PLL output (for example, Omori et al.: ``A carrier wave regeneration circuit for digital signal processing format 16QAM without pseudo pull-in phenomenon, 1986 Institute of Electronics, Information and Communication Engineers Spring All-I Conference Lecture Proceedings Volume B-2, 2-2
04 page, Institute of Electronics, Information and Communication Engineers, 1986.3).

Problems to be Solved by the Invention In such a conventional carrier wave regeneration circuit, when a carrier wave is regenerated using a selection control type carrier wave regeneration circuit, if the carrier wave regeneration circuit is configured with a digital circuit, the phase comparison characteristic becomes rectangular, and the analog phase comparison characteristic becomes rectangular. Even when configured as a circuit, the phase comparison characteristics are nonlinear, making analysis and design difficult.

In addition, when a carrier wave is regenerated using a digital signal processing type carrier wave regeneration circuit, a pseudo pull-in phenomenon becomes a problem.

On the other hand, when a plurality of PLLs having different phase comparison characteristic functions are used, the circuit configuration becomes complicated. Especially the multi-value number is 32
When the number of values increases to 64, there is a drawback that the circuit scale becomes extremely large.

The present invention has been made in view of these points, and since the phase comparison characteristic is linear, it is easy to analyze and design, the circuit scale can be relatively small even when the number of multi-values increases, and there is no pseudo-entrainment phenomenon. The purpose is to provide a carrier wave regeneration circuit.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides demodulation means that receives a multilevel amplitude phase modulation signal as input and demodulates it using a regenerated carrier wave, and detects the phase of the input multilevel amplitude phase modulation signal. an input phase detection means for comparing the phase of an input phase signal outputted from the input phase detection means with a reproduced carrier wave and outputting a phase difference; an error voltage generation means for outputting an error voltage synchronized with the demodulation means;
Only the error voltage generated from the signal point with the same phase as the signal point of phase phase modulation was selected and stored instead of the error voltage generated from the signal point with a different phase from the signal point of 4-phase phase modulation. an error voltage selection means using an error voltage from a signal point one clock before; a filter means for filter-linking the output of the error voltage selection means to determine the characteristics of the carrier wave regeneration circuit; and controlled oscillation means for generating a reproduced carrier wave.

Operation The present invention has the above-described configuration, detects the phase of the input multilevel amplitude phase modulation signal, and uses digital signal processing to regenerate the carrier wave, so that the carrier wave regeneration circuit has a linear phase comparison characteristic and is easy to analyze and design. can be provided. In addition, using the demodulated signal, only the error voltage generated from the signal point having the same phase as the signal point of the four-phase phase modulation was selected and stored in place of the error voltage generated from the other signal points. Since the error voltage from the signal point before the clock is used, there is no pseudo pull-in phenomenon, and even if the number of multi-values increases, it is possible to provide a synchronized wave regeneration circuit whose circuit scale is relatively small.

Embodiment Hereinafter, a carrier wave regeneration circuit according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the main part configuration of a carrier wave recovery circuit in one embodiment of the present invention. A multilevel amplitude phase modulation signal (multilevel APSK modulation signal) applied to the input terminal 1 is input to the demodulation means 2 and the input phase detection means 4. The demodulation means 2 demodulates the input multi-value APSK signal into a multi-value digital signal using the reproduced carrier wave from the controlled oscillation means 9. The multilevel digital signal is input to the error voltage selection means 7, and is also input to the output terminal 3a.
and 3b.

The input multi-level APSK signal inputted to the input phase detection means 4 is phase-shifted by 90° by the 90° phase shifter 401, and the input multi-level APSK signal is input to the input phase detection means 4.
The tan'' calculation means 402 is input together with the ° signal to the jan"' calculation means 402. The tan" calculation means 402 is composed of a ROM (read-only memory), etc., and calculates the j a n"' function from the 0° signal and the 90' signal. The phase of the input multi-level APSK signal is detected and output.

The input phase signal output from the jan-' calculation means 402 is input to the subtracter 5. The subtracter 5 serves as a phase comparison means, and calculates the difference between the input phase signal and the phase of the reproduced carrier wave output from the controlled oscillation means 9, and outputs it to the error voltage generation means 6. The error voltage generating means 6 is RO
It is a function circuit composed of M, etc., and its input/output characteristics are set to, for example, the characteristics shown in FIG. 2 (a repetitive function of π/2 period). With the above configuration, the phase comparison characteristics are linear, so it is easy to analyze the characteristics of the phase-locked loop, and it is also easy to design the phase-locked loop according to the required characteristics.

The error voltage, which is the output of the error voltage generation means 6, is selected by the error voltage selection means 7 and controls the control oscillation means 9 via the loop filter 8. As described above, the subtracter 5, error voltage generation means 6, error voltage selection means 7, loop filter 8, and controlled oscillation means 9 operate in a phase-locked loop (
PLL).

FIG. 3 shows an example of the configuration of the error voltage selection means 7.

Here, a 32QAM signal having the signal point arrangement shown by black dots in FIG. 4 is assumed as the input multilevel APSK signal.

Two systems of multivalued digital signals output from the demodulation means 2 are inputted from terminals 601 and 602, respectively, and are full-wave rectified by full-wave rectifiers 603 and 604, respectively. The output of the full wave rectifier 603 is subjected to amplitude discrimination by comparators 605 and 606.

Further, the output of the full-wave rectifier 604 is subjected to amplitude discrimination by comparators 607 and 608. Comparator 60
From the identification results of 5.606.607 and 608, EX-
OR circuit 609.610 and AND circuit 611.61
2, a signal point selection signal is generated. In addition, the terminal 61
3 is supplied with a reproduced clock.

On the other hand, the error voltage generated by the error voltage generation means 6 is inputted to the sample hold means 615 via the terminal 614. In response to the signal point selection signal, the sample hold means 615 outputs and stores only the error voltage generated from the signal point having the same phase as the signal point of the four-phase phase modulation, and stores the error voltage generated from the other signal points. Instead of the voltage, the stored error voltage from the signal point l clocks ago is output.

The discrimination levels of the comparators 605, 606, 607 and 608 are set such that the signal point selection signal indicates only error voltages generated by signal points within the shaded range in FIG. Ru.

By configuring the error voltage selection means 7 as described above, only the error voltages generated from the signal points located in the shaded area in FIG. 4 are used, and the error voltages generated from areas other than the shaded area are not used. The error voltage generated by the stored signal point one clock ago is used. Therefore, the phase-locked loop (PLL) consisting of the subtracter 5, the error voltage generation means 6, the error voltage selection means 7, the loop filter 8, and the controlled oscillation means 9 can generate the reference carrier without causing the condensation pull-in phenomenon. can be played.

As described above, according to this embodiment, the phase of the input multilevel amplitude phase modulation signal is detected and the carrier wave is regenerated using digital signal processing, so the phase comparison characteristic is linear, making analysis and design easy. . In addition, using the demodulated signal, only the error voltage generated from the signal point having the same phase as the signal point of the four-phase phase modulation was selected and stored in place of the error voltage generated from the other signal points. Since the error voltage from the signal point before the clock is used, the pseudo pull-in phenomenon can be avoided.

In the embodiment of the present invention, 32QAM is assumed as the input signal modulation method, but by changing the configuration of the error voltage selection means 7 from the configuration shown in FIG.
It can also support other multi-level APSK modulation signals. Further, as an example of the configuration of the loop filter 8 and the controlled oscillation means 9, the first
Although the figure shows an example configured with a digital circuit, this part can also be configured with an analog circuit.

Effects of the Invention As described above, according to the present invention, the phase of the input multilevel amplitude phase modulation signal is detected and the carrier wave is regenerated using digital signal processing. Design becomes easier.

In addition, using the demodulated signal, only the error voltage generated from the signal point having the same phase as the signal point of the four-phase phase modulation was selected and stored in place of the error voltage generated from the other signal points. Since the error voltage from the signal point before the clock is used, it is possible to provide a carrier wave regeneration circuit which does not suffer from the pseudo pull-in phenomenon and whose circuit size can be kept relatively small even when the number of multi-values increases, which is extremely useful.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the main part configuration of a carrier wave regeneration circuit according to an embodiment of the present invention, FIG. 2 is an explanatory diagram showing an example of characteristics of the error voltage generating means according to an embodiment of the present invention, and FIG. 4 is a block diagram showing a configuration example of the error voltage selection means, and FIG. 4 is an explanatory diagram showing the signal point arrangement of 32QAM and the signal point selection area of the error voltage selection means on the signal space. l...Input terminal, 2...Demodulation means, 3
a, 3b...Output terminal, 4...Input phase detection means, 5...Subtractor, 6...Error voltage generation means, 7... ...Error voltage selection means, 8
......Loop filter, 9...Controlled oscillation means, 201a, 201b--Multiplier, 2
02a. 202 b...LPF, 203...C
O3 waveform generation means, 204...SIN waveform generation means,
401...90' phase shifting means, 402---t
a n -' calculation means, 601.602.613゜6
14...Input terminal, 603.604...Full wave rectifier, 605°606, 607.608...
Comparator, 609.610...EX-OR gate, 611. 612...AND gate, 615
...Sample hold means, 801.802.
...Coefficient unit, 803, 904.906...
・Delay element, 804.805.903°905...
...adder, 901...mod (0,2π)
Calculation means, 902...2πfckT calculation means.

Claims (1)

[Claims] demodulating means for inputting a multi-level amplitude phase modulated signal and demodulating it using a regenerated carrier wave; input phase detecting means for detecting the phase of the input multi-level amplitude phase modulating signal; and an input that is the output of the input phase detecting means. a phase comparing means for comparing the phase of the phase signal and the reproduced carrier wave and outputting a phase difference; an error voltage generating means for receiving the phase difference as input and outputting an error voltage for synchronizing the reproduced carrier wave with a predetermined phase; and the demodulating means. With the output signal and the error voltage as input, only the error voltage generated from the signal point having the same phase as the signal point of the 4-phase phase modulation is output as is, and the error voltage generated from the signal point having a phase different from the signal point of the 4-phase phase modulation is output as is. error voltage selection means for outputting a stored error voltage from a signal point one clock before, instead of the error voltage determined by the error voltage; filter means for filter-linking the output of the error voltage selection means; A carrier wave regeneration circuit comprising a controlled oscillation means for generating a regenerated carrier wave according to the output.