JPH03154381A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enable a MIS FET of SOI structure wherein the fluctuation of threshold voltage V and the breakdown strength drop between a source and a drain are suppressed by connecting a channel region to a substrate, so that it may not contact with an element isolating insulating film, in the region where a gate electrode and the element isolating insulating film overlap each other. CONSTITUTION:A p-type channel region 31 and n-type source and drain regions 32 and 33 are made in a single crystal Si film 3 positioned on a p-Si substrate 1 through a buried insulating film 2. A gate electrode 6 is made through a gate insulating film 5 on the channel region 31, and an element insulating insulating film 4 is made around the element region. Hereupon, in the region 2A, the buried insulating film 2 does not exist, and the channel region 31 and the substrate 1 are connected. Even if it is done this way, the buried insulating layer 2 exists in the channel region 31, so the strong point of SOI(Silicon On Insulator) structure is not lost, and the positive holes generated in the channel region flow the the substrate. Hereby, the fluctuation of threshold voltage V and the breakdown strength between the source and the drain can bo suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] This invention relates to a semiconductor device having an MIS field effect transistor ([SFET]).

The purpose of this study is to obtain an SFET with a sor structure that suppresses fluctuations in threshold voltage V and decreases in breakdown voltage between the source and drain.

A source/drain region (32) is formed by introducing impurities of the opposite conductivity type from the surface of a semiconductor substrate (1) of one conductivity type with a channel region (31) in between.

(33) and a data 1-insulating film (5) on the channel region.
a gate electrode (6) formed through the substrate, an element isolation insulating film (4) formed around the channel region and the source/drain region on the substrate, and at least a portion thereof inside the substrate. has a buried insulating layer (2) formed in a region overlapping with the channel region, and the buried insulating layer (2) comprises:
A region (2) where the gate electrode and the element bone MM insulating film overlap
A) is configured so that it is not in contact with the element isolation insulating film (4), and the channel region is configured to be electrically connected to the substrate.

[Industrial application field]

The present invention relates to a semiconductor device having an MIS field effect transistor.

The high performance of semiconductor devices in recent years is largely due to the improvement in the performance of individual transistors due to higher device integration1, that is, the miniaturization of the transistors that make up the device.This is due to thinner gate insulating films and shorter channel lengths. This is because the channel conductance increases, and further improvement in performance is desired.

The present invention can be applied to semiconductor devices that are compatible with high performance.

[Prior Art] Conventionally, the performance of MIS FETs has been improved by making the gate insulating film thinner and reducing the channel length as described above.

However, since the power supply voltage is constant, the increase in the vertical electric field due to thinning of the gate insulating film and the saturation of carrier velocity due to shortening of the channel reduce the actual carrier mobility within the channel, that is, the field effect mobility μ. 1. will decrease. This is a phenomenon particular to old S devices and is unavoidable.

For this reason, a transistor with a gate length of 1 μm or less cannot be expected to improve performance as much as miniaturization.

A thin film transistor having a first-order SOI structure shown in FIG. 4 has recently attracted attention as a method for alleviating the decrease in mobility caused by the vertical electric field.

FIGS. 4(1) to 4(3) are a plan view and a sectional view of a conventional MIS FET.

The figure shows 5OI (Silicon On In5ulato)
r) structure, FIG. 4(1) is a plan view, FIG. 4(2) is a sectional view taken along line A-A, and FIG. 4(3) is shown along line B-
8 is a sectional view.

In the figure, a p-type channel region 31 and n-type source/drain regions 32 and 33 are formed in a single crystal St film 3 on a p-type silicon (p-St) substrate 1 via a buried insulating film 2. ing.

A gate electrode 6 is formed on the channel region 31 via a gate insulating film 5, and an element isolation insulating film 4 is formed around the element region.

Thin single crystal S on thick buried insulating film (Sol insulating film) 2
It has been reported at academic conferences that by forming a transistor in the i-film 3, the decrease in mobility can be significantly suppressed.

This means that the gate voltage is
This is because the vertical electric field divided by the capacitance formed by the buried insulating film/substrate and applied to the gate insulating film is relaxed.

In addition, the present inventor also first developed MrS Ff! with a Sol structure. An example of T has been filed in Japanese Patent Application No. 1-233180.

[Problem to be solved by the invention]

However, problems have also arisen in the MIS FET having the above-mentioned Sol structure. In FIG. 4, the element isolation insulating film 4 is in contact with the buried insulating layer 2, and the active region is completely isolated, so that the channel region 31 is in an electrically floating state.

In an n-channel transistor, electrons flowing through the channel from the source to the drain are accelerated near the drain and generate electron-hole pairs through impact ionization. The generated electrons e are attracted to a positive potential and flow into the drain, while holes become a substrate current in a normal structure, but accumulate in the floating channel region 31 in an SOI structure.

As a result, the p-wall region of the channel region 31 is positively biased, the substrate potential shifts to the positive side, the threshold voltage V changes, and a kink phenomenon appears in the static characteristics of drain current-drain voltage. Or.

The effect of the parasitic bipolar transistor composed of the channel region 31 and source/drain regions 32 and 33 causes a reduction in breakdown voltage.

An object of the present invention is to obtain a Sol structure MisFET in which fluctuations in threshold voltage Vth and reduction in breakdown voltage between the source and drain are suppressed.

[Means to solve the problem]

The solution to the above problem is to - source/drain regions (32) formed by introducing impurities of the opposite conductivity type from the surface of a conductivity type semiconductor substrate (1) with a channel region (31) in between; (33), a gate electrode (6) formed on the channel region via a gate insulating film (5),
an element isolation insulating film (4) formed on the substrate around the channel region and the source/drain region; and a buried layer formed inside the substrate in a region at least partially overlapping with the channel region. an insulating layer (2), such that the buried insulating layer (2) is not in contact with the element isolation insulating film (4) in a region (2A) where the gate electrode and the element isolation insulating film overlap. This is achieved by a semiconductor device configured to have a channel region electrically connected to the substrate.

(effect) FIGS. 1 (1) to (3) are diagrams explaining the principle of the present invention.

The figure shows a MIS FET with a Sol structure.
Figure 1 (2) is a plan view, Figure 1 (2) is a sectional view taken along line A-A, Figure 1 (3) is a plan view.
is a sectional view taken along B-8.

In the figure, a p-type channel region 31 and n-type source/drain regions 32 and 33 are formed in a single crystal Si film 3 on a p-Si substrate 1 via a buried insulating film 2. A gate electrode 6 is connected through a gate insulating film 5.
is formed, and an element isolation insulating film 4 is formed around the five element regions.

The above is the same as the conventional example shown in FIG. 4, but one difference between the present invention and the conventional example is that in FIG. and the board 1 are connected to each other.

Even in this case, the channel region 31 is filled with the buried insulating layer 2.
The advantages of the SOT structure are not lost because of the presence of
Fluctuations in tb and reduction in breakdown voltage between the source and drain can be suppressed.

〔Example〕

FIGS. 2(1) to 00) are cross-sectional views illustrating an embodiment of the present invention.

In the figure, (1), (3), (5), (7), (
9) shows the A-A cross section in Figure 1, (2), (4)
, (6), (8), GO) show the BB cross section in FIG.

Here, the manufacturing process will be outlined and its structure will be explained in order of process.

(2) In FIGS. 2(1) and (2), a thermally oxidized SiO□ film with a thickness of 0.5 to 1 μm is formed on the p-Si substrate 1 as the buried insulating film 2.

Thereafter, the buried insulating film 2 in the region 2A of FIG. 1(1) is removed.

(2) In FIGS. 2(3) and (4), a single crystal Si film 3 is formed by shrimp growth. At this time, the film thickness on the buried insulating film 2 is set to 500 to 2000 layers.

Alternatively, instead of shrimp growth, amorphous St or the like may be deposited and then heat treated to recrystallize it.

(2) In FIGS. 2(5) and 2(6), the single crystal Si film 3 on the element isolation region including the region 2A in FIG. 1(1) is removed by etching to form a groove. At this time, the buried insulating film 2 is prevented from being exposed.

After that, by vapor phase growth (CVD) method, the groove part has a thickness of 0.
．． An element isolation insulating film 4 is formed by embedding a 5 to 1 μm thick Sin film.

The element isolation insulating film 4 may be formed using the LOCO5 method, which performs thermal oxidation using a Si nitride film as an oxidation-resistant mask.

■ In Figure 2 (7) and (8), 1 gate insulating film 5
As a result, a thermally oxidized SiO2 film with a thickness of 100 to 200 mm is formed.

Thereon, poly-Si is deposited to a thickness of 1,000 to 3,000 layers by CVD, and a gate electrode 6 is formed by dry etching.

■ In Figure 2 (9), GO), using the gate electrode 6 as an implantation mask, arsenic ions (As'') are implanted into single-crystal Si.
It is implanted into the film 3 to form source/drain regions 32 and 33.

The conditions for implanting As" are an energy of 60 KeV and a dose of 10" cm.

FIGS. 3(1) and 3(2) are sectional views illustrating another embodiment of the present invention.

FIG. 3(1) is a sectional view taken along line AA in FIG. 1, and FIG. 3(2) is a sectional view taken along line CC in FIG.

In this example, the buried insulating layer 2 and source/drain regions 32.
33 so that they do not come into contact with each other. Therefore, the channel region 31 is in contact with the substrate 1 even in areas other than the region 2A in FIG.

An outline of the manufacturing process will be explained in conjunction with FIG. 2.

(2) The buried insulating film 2 is left only in the portion corresponding to the channel region.

■ The thickness of the single crystal Si film of the buried insulating film 2 is 1500~3.
000 people.

■,■ Same as Figure 2■ The thickness of the source/drain regions 32 and 33 is 1000mm
~2000 people.

The structure in which the buried insulating layer is separated from the source and drain shown in FIG. 3 has the following features compared to the structure in which the buried insulating layer is in contact with the source and drain in FIG. 2.

Although it is the same in that it prevents floating of the channel region, there is more margin in the process in terms of pattern layout.

In other words, when the source/drain region and the buried layer are in contact with each other, there is only a current path between the channel region and the lower substrate on both sides of the channel region, so the element isolation insulating film and the buried layer in this area are in contact with each other. This is because it is necessary to have some margin to avoid this.

Traditional SO! In a transistor, in a static characteristic diagram of drain current vs. drain voltage, a bump called a kink appears due to fluctuations in the threshold voltage Vtk.

Kink was not recognized in the past.

〔Effect of the invention〕

As explained above, according to the present invention, the threshold voltage VL
S that suppresses the fluctuation of h and the drop in breakdown voltage between the source and drain.
A MIS FET with an OL structure was obtained, and a semiconductor device equipped with a high-performance short channel transistor became possible.

[Brief explanation of the drawing]

FIGS. 1 (1) to (3) are diagrams explaining the principle of the present invention. FIGS. 2(1) to 00) are cross-sectional views illustrating an embodiment of the present invention. FIGS. 3(1) and 3(2) are sectional views illustrating another embodiment of the present invention. FIG. 4 (1) to (3) are MIS Fll! according to the conventional example.
It is a top view and sectional view of T. In fig. 1 is a semiconductor substrate, which is a p-3t substrate. 2 is a buried insulating film, which is a SiOx film. 3 is a single crystal Si film. 31 is a channel region. 32 and 33 are source/drain regions. 4 is an element isolation insulating film, which is a SiO2 film. 5 is a gate insulating film, which is a 5i02 film. 6 is the gate electrode; poly-Si film (1) top view (2) A-AFr plane (3) B-Bvr plane of the present invention. , 5 ri map? ; 1 Figure (1) A-A cross section (') 2) (1) Cross section (2) C-C fold i Other example fold diagram Figure 3

Claims (1)

[Claims] Source/drain regions (32), (33) are formed by introducing impurities of the opposite conductivity type from the surface of a semiconductor substrate (1) of one conductivity type with a channel region (31) in between.
), a gate electrode (6) formed on the channel region via a gate insulating film (5), and an element isolation insulating film formed on the substrate around the channel region and the source/drain region. (4), and a buried insulating layer (2) formed inside the substrate in a region at least partially overlapping with the channel region, and the buried insulating layer (2) is connected to the gate electrode. and the device isolation insulating film (2A) are configured so that they are not in contact with the device isolation insulating film (4) in an overlapping region (2A), and the channel region is electrically connected to the substrate. semiconductor device.