JPH03154354A - Mounting structure of lsi - Google Patents
Mounting structure of lsiInfo
- Publication number
- JPH03154354A JPH03154354A JP1294166A JP29416689A JPH03154354A JP H03154354 A JPH03154354 A JP H03154354A JP 1294166 A JP1294166 A JP 1294166A JP 29416689 A JP29416689 A JP 29416689A JP H03154354 A JPH03154354 A JP H03154354A
- Authority
- JP
- Japan
- Prior art keywords
- lsi
- wiring
- substrate
- insulating layer
- end side
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 239000004642 Polyimide Substances 0.000 abstract description 2
- 239000011521 glass Substances 0.000 abstract description 2
- 229920001721 polyimide Polymers 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/494—Connecting portions
- H01L2224/4943—Connecting portions the connecting portions being staggered
- H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、ＬＳＩの実装構造に係り、例えば光書込みユ
ニット用のＬＳＩの実装構造に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an LSI mounting structure, for example, an LSI mounting structure for an optical writing unit.
（従来の技術）
ＬＳＩのコストは、ユニットコストの約１／３を占め、
ＬＳＩチップ面積と比例関係にあり、ＬＳＩチップ面積
は（ワイヤー）ボンディングの電極ピンチによって決ま
る。現在、例えばえＡ１ウェッジ方式のボンディングに
おいては、電極ピッチは１２０μｍピッチ前後の値がひ
とつの目安となっている。また、ＬＳＩを実装する基板
の配線のラインビ・ノチが小さ（なると、配線歩留りが
大幅に低下する。例えばあるユニットにおいては、配線
のライン幅の限界は２２μｍになっている。(Prior art) The cost of LSI accounts for about 1/3 of the unit cost,
There is a proportional relationship with the LSI chip area, and the LSI chip area is determined by the electrode pinch of (wire) bonding. Currently, for example, in A1 wedge type bonding, one guideline for the electrode pitch is a value of around 120 μm pitch. Further, the line width and notch of the wiring on the board on which the LSI is mounted is small (as a result, the wiring yield is significantly reduced. For example, in a certain unit, the limit of the line width of the wiring is 22 μm.
一方、例えば自己走査型のユニットにおいては、ＬＳＩ
上の電極パッド（出力ビン）のレイアウト方法がポイン
トになっている。すなわち、機能素子が長手方向に多数
、例えばＡ４ ３００ＤＰＩ（−１２本／ｍｍ）の場合
には２５６０ドツト並び、各ドツトに１個のドライバー
が必要になるので、各ドツトに接続されるＬＳＩ上の電
極パッドのレイアウト方法がポイントになる。電極パッ
ドのレイアウト方法は、機能素子の列に出力ビンを直角
に並べる方法あるいは平行に並べる方法、またＬＳＩチ
ップの片側に並べる方法あるいは両側に並べる方法から
選択することができる。例えば、電極パッドを機能素子
に対して直角に並べた場合、接続される基板側の接続端
子ピッチが小さくなったり、ポールボンダー以外の使用
が不可になったり、電極材料が制限されたり、ファイン
ピッチボンディングが不可になったり、あるいはＡｆウ
ェッジボンダーを用いるとヘッド回転のボンダー以外の
使用が不可になり、ボンディング時間が長くなったりす
るといった不具合がある。このため、通常、電極パッド
を機能素子に平行に並べる方法がよく用いられている。On the other hand, for example, in a self-scanning unit, LSI
The key point is the layout of the upper electrode pads (output bins). In other words, there are many functional elements in the longitudinal direction, for example, in the case of A4 300DPI (-12 lines/mm), 2560 dots are arranged, and each dot requires one driver, so the number of functional elements on the LSI connected to each dot is The key point is how to lay out the electrode pads. The electrode pad layout method can be selected from the following methods: arranging the output bins perpendicular to or parallel to the rows of functional elements, or arranging them on one side or both sides of the LSI chip. For example, when electrode pads are arranged perpendicular to a functional element, the pitch of the connection terminals on the board to which they are connected becomes smaller, it becomes impossible to use anything other than a pole bonder, the electrode materials are limited, and fine pitch There are problems in that bonding becomes impossible, or if an Af wedge bonder is used, it becomes impossible to use anything other than a head-rotating bonder, resulting in a longer bonding time. For this reason, a method of arranging electrode pads parallel to functional elements is often used.
（発明が解決しようとする課題）
しかしながら、このような従来のＬＳＩの実装構造にあ
っては、下達のような理由により、ＬＳｒの高密度実装
が困難であったり、コストが上昇したりするといった問
題点があった。(Problems to be Solved by the Invention) However, in such a conventional LSI mounting structure, high-density mounting of LSr is difficult and costs increase due to reasons such as inferiority. There was a problem.
すなわち、基板上の配線パターンのない領域にＬＳＩを
実装していたため、ＬＳＩ実装の高密度化が困難であっ
た。That is, since the LSI was mounted in an area on the board where there is no wiring pattern, it was difficult to increase the density of LSI mounting.
また、ＬＳＩの電極パッドを機能素子に対して平行に並
べた場合、機能素子のピッチが小さくなると、電極パッ
ドは第７図に示すように千鳥に配列される。第７〜１０
図において、例えば配線ピッチをＰ、配線の接続端子２
１の幅を０ 、０９ｍｍとすると、配線の最小ライン幅
Ｉは、
■＝ （２Ｐ−０，０９） ／３ ・・・・・・■
となり、ＬＳＩ２２の切断代＋αを０．２３９ Ｘ２
＝０゜４７８１とすると、ＬＳＩ２２の長さＷは、例え
ば、Ｗ ＝ １２８ Ｐ 十０．４７８ ・・
・・・・■となる。ＬＳＩ２２の幅を１．４ｍｍとする
と、ＬＳＩ２２のチップ面積Ｓは、
Ｓ＝１．４Ｗ ・・・・・・■
となる。ここで、Ｐが０．０７６ ｍｍ以下のファイン
ピッチになると、電極パッド２３をボンディングする際
、先にボンディングした電極パッド２４のワイヤー２５
とウェッジツール２６が干渉するので、ウェッジツール
２６のクリアランスエリアＣが隣接する電極パッド２４
と重なり合わないように第７図の寸法Ａを０．４ｍｍ以
上にする必要がある。ただし第８図はＰ ＞０．０７６
のときの電極パッド２３．２４の位置関係、第９図はＰ
≦０．０７６のときの電極パッド２３．２４の位置関係
を示している。このため・、Ｐ≦０．０７６の範囲のＳ
は、
Ｓ ＝ （１，４＋０．４ ） Ｗ ・・・・
・・■となる。したがって、ＬＳＩ２２のチップサイズ
が太き（なり、コストが上昇していた。なお、基板配線
の最小のライン幅およびコストとチップ面積との関係は
第５図の点線グラフにより示される。Further, when the electrode pads of an LSI are arranged parallel to the functional elements, when the pitch of the functional elements becomes small, the electrode pads are arranged in a staggered manner as shown in FIG. 7th to 10th
In the figure, for example, the wiring pitch is P, the wiring connection terminal 2
If the width of 1 is 0.09mm, the minimum line width I of wiring is: ■= (2P-0,09)/3 ・・・・・・■
Therefore, the cutting allowance +α of LSI22 is 0.239 X2
= 0°4781, the length W of the LSI 22 is, for example, W = 128 P +0.478...
...■. Assuming that the width of the LSI 22 is 1.4 mm, the chip area S of the LSI 22 is S=1.4W. Here, when P becomes a fine pitch of 0.076 mm or less, when bonding the electrode pad 23, the wire 25 of the electrode pad 24 bonded earlier
Since the wedge tool 26 interferes with the adjacent electrode pad 24, the clearance area C of the wedge tool 26 interferes with the adjacent electrode pad 24.
It is necessary to make dimension A in FIG. 7 0.4 mm or more so as not to overlap with the above. However, in Figure 8, P > 0.076
Figure 9 shows the positional relationship of the electrode pads 23 and 24 when P
The positional relationship of the electrode pads 23 and 24 when ≦0.076 is shown. Therefore, S in the range of P≦0.076
is, S = (1,4+0.4) W...
... becomes ■. Therefore, the chip size of the LSI 22 has become thicker and the cost has increased.The relationship between the minimum line width of the substrate wiring and the cost and the chip area is shown by the dotted line graph in FIG.
（発明の目的）
そこで第１の発明は、ＬＳＩを絶縁層を介して基板の配
線上に実装することにより、ＬＳＩの実装の高密度化を
図ることを目的としている。(Objective of the Invention) Therefore, a first object of the invention is to increase the density of LSI mounting by mounting the LSI on the wiring of the substrate via an insulating layer.
また、第２の発明は、ＬＳＩの他端側電極パッドに接続
された配線をＬＳＩの下を通して千鳥配列の各一端側接
続端子間を通すことにより、ＬＳＩのチップ面積を小さ
くして、コストを低減することを目的としている。In addition, the second invention reduces the chip area of the LSI and reduces costs by passing the wiring connected to the electrode pad on the other end of the LSI under the LSI and between the connecting terminals on the one end in a staggered arrangement. The aim is to reduce
（発明の構成）
第１の発明によるＬＳＩの実装構造は、上記目的達成の
ため、基板上に基板の配線の一部を覆う絶縁層を形成し
、該絶縁層上にＬＳＩを実装したことを特徴とするもの
である。(Structure of the Invention) In order to achieve the above object, an LSI mounting structure according to the first invention includes forming an insulating layer on a substrate to cover a part of the wiring of the substrate, and mounting an LSI on the insulating layer. This is a characteristic feature.
第２の発明によるＬＳＩの実装構造は、上記目的達成の
ため、ＬＳＩの一端部側および他端部側にそれぞれ配設
された複数の一端側電極パッドおよび他端側電極パッド
と、ＬＳＩを絶縁層を介して載置する基板と、基板に、
ＬＳＩの一端部に沿って配設され、対応する一端側電極
パッドにそれぞれ接続される複数の一端側接続端子と、
基板に、ＬＳＩの他端部に沿って配設され、対応する他
端側電極パッドにそれぞれ接続される複数の他端側接続
端子と、を備えたＬＳＩの実装構造において、前記一端
側接続端子が千鳥に配列され、他端側接続端子が１列ま
たは千鳥に配列され、かつ、他端側接続端子に接続され
る配線がＬＳＩ下の絶縁層および基板間を通り抜けて、
各一端側接続端子間を通るように延在したことを特徴と
するものである。In order to achieve the above object, the LSI mounting structure according to the second invention insulates the LSI from a plurality of one-end electrode pads and a plurality of other-end electrode pads arranged on one end side and the other end side of the LSI, respectively. The substrate to be placed through the layers, and the substrate,
a plurality of one-end side connection terminals arranged along one end of the LSI and respectively connected to corresponding one-end side electrode pads;
In an LSI mounting structure, the LSI mounting structure includes a plurality of other end side connection terminals arranged along the other end of the LSI and connected to corresponding other end side electrode pads, respectively. are arranged in a staggered manner, the connection terminals on the other end are arranged in a row or in a staggered manner, and the wiring connected to the connection terminal on the other end passes between the insulating layer and the substrate under the LSI,
It is characterized in that it extends so as to pass between each one end side connection terminal.
以下、本発明の実施例に基づいて説明する。Hereinafter, the present invention will be explained based on examples.
第１〜５図は第１および第２の発明に係るＬＳＩの実装
構造の一実施例を示す図である。1 to 5 are diagrams showing an example of an LSI mounting structure according to the first and second inventions.
まず、構成を説明する。First, the configuration will be explained.
第１〜４図において、１は基板であり、基板１は所定パ
ターンの配線２を有している。基板１の配線２の一部は
５〜３０μｍ厚さのガラスまたはポリイミドからなる絶
縁層３により覆われており、ＬＳＩ４は絶８ｉ層３上に
絶縁性のダイボンディングペースト５を介して実装され
ている。すなわち、基板１は絶縁層３およびグイボンデ
ィングペースト５を介してＬＳＩ４を載置している。Ｌ
ＳＩ４は一端部４ａおよび他端部４ｂを有し、一端部４
ａ側および他ツ１１部４ｂ側に複数の電極パッド６が振
り分けて配設されており、一端部４ａ側のものを電極パ
ッド６ａ、他端部４ｂ側のものを電極パッド６ｂとする
。基板１にはＬＳＩ４の一端部４ａに沿って複数の接続
端子７が配設され、他端部４ｂに沿って複数の接続端子
８が配設されている。In FIGS. 1 to 4, reference numeral 1 denotes a substrate, and the substrate 1 has wiring 2 in a predetermined pattern. A part of the wiring 2 of the substrate 1 is covered with an insulating layer 3 made of glass or polyimide with a thickness of 5 to 30 μm, and the LSI 4 is mounted on the insulating layer 3 via an insulating die bonding paste 5. There is. That is, the LSI 4 is mounted on the substrate 1 via the insulating layer 3 and the bonding paste 5. L
SI4 has one end 4a and the other end 4b, and the one end 4
A plurality of electrode pads 6 are distributed and arranged on the a side and the other 11 part 4b side, and the one on the one end 4a side is called the electrode pad 6a, and the one on the other end 4b side is called the electrode pad 6b. On the board 1, a plurality of connection terminals 7 are arranged along one end 4a of the LSI 4, and a plurality of connection terminals 8 are arranged along the other end 4b.
接続端子７は配線２のうちの配線２ａの端子であり、接
続端子８は配線２のうちの配線２ｂの端子である。接続
端子７．８のそれぞれは対応するＬＳＩ４の電極パッド
６．７のそれぞれにワイヤーボンディングによりワイヤ
ー９を介して接続されている。接続端子７はＬＳＩ４の
一端部４ａに沿って千鳥に配列され、接続端子８はＩ＝
Ｓ ＋ ４の他端部４ｂに沿って１列または千鳥（本
実施例では１列）に配列されている。また、接続端子８
に接続される配線２ｂはＬＳＩ４下の絶縁層３および基
板１間を通り抜けて、各接続端子７の間を通るように延
在している。すなわち、配線２ｂはＬＳＩ４の他端部４
ｂ側からＬＳＩ４の下を通り抜けて、ＬＳＩの一端部４
ａ側に延在し、そして、接続端子７および配線２ａの形
成する配線パターン間を通るように延在している。The connection terminal 7 is a terminal of the wiring 2a of the wiring 2, and the connection terminal 8 is a terminal of the wiring 2b of the wiring 2. Each of the connection terminals 7.8 is connected to each of the electrode pads 6.7 of the corresponding LSI 4 via a wire 9 by wire bonding. The connection terminals 7 are arranged in a staggered manner along one end 4a of the LSI 4, and the connection terminals 8 are arranged at I=
They are arranged in one row or in a staggered pattern (one row in this embodiment) along the other end 4b of S+4. In addition, connection terminal 8
The wiring 2b connected to the LSI 4 extends between the insulating layer 3 under the LSI 4 and the substrate 1, and between the connection terminals 7. That is, the wiring 2b is connected to the other end 4 of the LSI 4.
Pass under the LSI 4 from the b side and connect to one end 4 of the LSI.
It extends toward the a side, and extends between the wiring patterns formed by the connection terminal 7 and the wiring 2a.
上記のような構成によれば、ＬＳＩ４を絶縁層３を介し
て基板１の配線２上に実装しているので、基板１の配線
がない領域上にＬＳＩを実装していた従来のものに比較
すると、ＬＳＩ４を高密度実装することができる。According to the above configuration, the LSI 4 is mounted on the wiring 2 of the substrate 1 via the insulating layer 3, so compared to the conventional structure in which the LSI is mounted on an area of the substrate 1 where there is no wiring. Then, the LSI 4 can be mounted with high density.
また、本実施例の場合の配線２の最小ライン幅■。は、
第４図に示すように配線２ａのピッチをＰｏ、接続端子
７の幅を０．０９ｍｍとすると、１ 、 ＝ （２Ｐ、
−０，０９） ／７ ・・・、・・・■となり、
前述した第７図に示す従来のものと同様に考えると、Ｌ
ＳＩ４の長さＷｏは、
Ｗ０＝６４ＰＯ＋０．４７８ ・・・・・・■とな
り、ＬＳＩ４のチップ面積Ｓ０は、５ｏ−１，４Ｗｏ
・・・・・・■となる。チップ面積Ｓ０およびコス
トと最小ライン幅■。との関係は第５図の実線グラフに
示され、咳図から明らかに本実施例ではチップ面積を点
線グラフに示される従来のものより小さくすることがで
き、特に、Ｐ≦０．０７６以下に相当する範囲において
はその差が非常に大きくなる。したがって、コストを大
幅に低減することができる。Also, the minimum line width (■) of the wiring 2 in this embodiment. teeth,
As shown in FIG. 4, if the pitch of the wiring 2a is Po and the width of the connecting terminal 7 is 0.09 mm, then 1, = (2P,
-0,09) /7 ..., ...■,
Considering the same way as the conventional one shown in FIG. 7 mentioned above, L
The length Wo of SI4 is W0=64PO+0.478...■, and the chip area S0 of LSI4 is 5o-1,4Wo
・・・・・・■. Chip area S0, cost and minimum line width ■. The relationship between P and D is shown in the solid line graph in FIG. In the corresponding range, the difference becomes very large. Therefore, costs can be significantly reduced.
さらに、基板１の接続端子７を千鳥に配列し、各接続端
子７間にＬＳＩ４の下を通り抜けた配線２ｂを通してい
るので、配線２のパターン全体の幅をＬＳＩ４の長さよ
り小さくすることができる。Furthermore, since the connection terminals 7 of the board 1 are arranged in a staggered manner and the wiring 2b passing under the LSI 4 is passed between each connection terminal 7, the width of the entire pattern of the wiring 2 can be made smaller than the length of the LSI 4.
またさらに、仮に配線２ｂをＬＳＩ４の下を通さずに第
６図に示すようにＬＳＩ４間を通した場合、第６図のＭ
？ｉＪｆ域のスペースが小さくなり、配線２ｂのライ
ン幅およびピッチが非常に小さくなるが、本実施例にお
いては、ライン幅およびピッチを大きくすることができ
るので、基板１の歩留りを向上することができる。Furthermore, if the wiring 2b is not passed under the LSI 4 but is passed between the LSIs 4 as shown in FIG.
? Although the space in the iJf region becomes smaller and the line width and pitch of the wiring 2b become very small, in this example, the line width and pitch can be increased, so the yield of the substrate 1 can be improved. .
なお、接続端子７の千鳥配列の段数は本実施例のものに
限定されるものではなく、接ＥＦＥＯＩＭ子８を千鳥配
列にした場合も同様である９また、本発明Ｑ：よるＬｓ
Ｉの実装構造はサーマルヘッドやＬＥＤアレイ等の各種
デバイスのＬＳＩの実装構造にも適用することができる
。Note that the number of stages in the staggered arrangement of the connection terminals 7 is not limited to that of this embodiment, and the same applies when the contact EFEOIM elements 8 are arranged in a staggered arrangement.
The mounting structure of I can also be applied to LSI mounting structures of various devices such as thermal heads and LED arrays.
（効果）
第１の発明によれば、ＬＳＩを絶縁層を介して基板の配
線上に実装しているので、ＬＳＩの実装を高密度化する
ことができる。(Effects) According to the first invention, since the LSI is mounted on the wiring of the substrate via the insulating layer, the LSI can be mounted at high density.
第２の発明によれば、ＬＳＩの他端側電極パッドに接続
された配線をＬＳＩの下を通して千鳥配列の各一端側接
続端子間を通しているので、第１の発明の効果に加え、
ＬＳＩのチップ面積を小さくすることができ、コストを
低減することができる。また、配線のパターン幅をＬＳ
Ｉの長さより小さくすることができるので、基板を小さ
くすることができ、さらＬこ、配線のライン幅およびピ
ッチを大きくすることができるので、基板の歩留りを向
上することもできる。According to the second invention, since the wiring connected to the electrode pad on the other end of the LSI passes under the LSI and between each of the connection terminals on the one end of the staggered arrangement, in addition to the effects of the first invention,
The chip area of the LSI can be reduced, and costs can be reduced. Also, set the wiring pattern width to LS
Since the length of I can be made smaller than the length of I, the substrate can be made smaller, and since the line width and pitch of the wiring can be increased, the yield of the substrate can also be improved.
第１〜５図は本発明に係るＬＳＩの実装構造の一実施例
を示す図であり、第１図はその斜視図、第２図はその断
面図、第３図はその概略平面図、第４図はその要部概略
平面図、第５図は配線の最小ライン幅とチップ面積およ
びコストとの関係を示すグラフ、第６図は従来のＬＳＩ
の実装構造を示すその概略平面図、第７〜１０図は従来
の他のＬＳＩの実装構造を示す図であり、第７図はその
要部概略平面図、第８．９図はその作用を説明するため
の平面図、第１０図はその作用を説明するための側面図
である。
１・・・・・・基板、
２・・・・・・配線、
２ｂ・・・・・・配線（他端側接続端子に接続される配
線）３・・・・・・絶縁層、
４・・・・・・ＬＳＩ、
４ａ・・・・・・一端部、
４ｂ・・・・・・他端部、
６ａ・・・・・・電極パッド（一端側電極パッド）、６
ｂ・・・・・・電極パッド（他端側電極パッド）、７・
・・・・・接続端子（一端側接続端子）、８・・・・・
・接続端子（他端側接続端子）。1 to 5 are diagrams showing one embodiment of an LSI mounting structure according to the present invention, in which FIG. 1 is a perspective view thereof, FIG. 2 is a sectional view thereof, and FIG. 3 is a schematic plan view thereof, and FIG. Figure 4 is a schematic plan view of the main part, Figure 5 is a graph showing the relationship between the minimum line width of wiring, chip area and cost, and Figure 6 is a diagram of the conventional LSI.
7 to 10 are diagrams showing the mounting structure of other conventional LSIs, FIG. 7 is a schematic plan view of the main part thereof, and FIG. 8.9 shows its operation. FIG. 10 is a plan view for explaining, and a side view for explaining its operation. 1... Board, 2... Wiring, 2b... Wiring (wiring connected to the other end side connection terminal) 3... Insulating layer, 4. ...LSI, 4a...One end, 4b...Other end, 6a...Electrode pad (electrode pad on one end side), 6
b... Electrode pad (electrode pad on the other end side), 7.
...Connection terminal (one end side connection terminal), 8...
- Connection terminal (connection terminal on the other end).
Claims (2)
、該絶縁層上にＬＳＩを実装したことを特徴とするＬＳ
Ｉの実装構造。(1) An LS characterized in that an insulating layer is formed on a substrate to cover part of the wiring of the substrate, and an LSI is mounted on the insulating layer.
Implementation structure of I.
された複数の一端側電極パッドおよび他端側電極パッド
と、ＬＳＩを絶縁層を介して載置する基板と、基板に、
ＬＳＩの一端部に沿って配設され、対応する一端側電極
パッドにそれぞれ接続される複数の一端側接続端子と、
基板に、ＬＳＩの他端部に沿って配設され、対応する他
端側電極パッドにそれぞれ接続される複数の他端側接続
端子と、を備えたＬＳＩの実装構造において、前記一端
側接続端子が千鳥に配列され、他端側接続端子が１列ま
たは千鳥に配列され、かつ、他端側接続端子に接続され
る配線がＬＳＩ下の絶縁層および基板間を通り抜けて、
各一端側接続端子間を通るように延在したことを特徴と
するＬＳＩの実装構造。(2) A plurality of one end side electrode pads and other end side electrode pads respectively arranged on one end side and the other end side of the LSI, a substrate on which the LSI is mounted via an insulating layer, and a substrate;
a plurality of one-end side connection terminals arranged along one end of the LSI and respectively connected to corresponding one-end side electrode pads;
In an LSI mounting structure, the LSI mounting structure includes a plurality of other end side connection terminals arranged along the other end of the LSI and connected to corresponding other end side electrode pads, respectively. are arranged in a staggered manner, the connection terminals on the other end are arranged in a row or in a staggered manner, and the wiring connected to the connection terminal on the other end passes between the insulating layer and the substrate under the LSI,
An LSI mounting structure characterized by extending between connection terminals on one end side.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1294166A JPH03154354A (en) | 1989-11-13 | 1989-11-13 | Mounting structure of lsi |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1294166A JPH03154354A (en) | 1989-11-13 | 1989-11-13 | Mounting structure of lsi |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03154354A true JPH03154354A (en) | 1991-07-02 |
Family
ID=17804169
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1294166A Pending JPH03154354A (en) | 1989-11-13 | 1989-11-13 | Mounting structure of lsi |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03154354A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007103423A (en) * | 2005-09-30 | 2007-04-19 | Renesas Technology Corp | Semiconductor device and its manufacturing method |
-
1989
- 1989-11-13 JP JP1294166A patent/JPH03154354A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007103423A (en) * | 2005-09-30 | 2007-04-19 | Renesas Technology Corp | Semiconductor device and its manufacturing method |
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