JPH03152689A - Card processor - Google Patents

Abstract

PURPOSE:To attain low power consumption by permitting service when effective valuable mark information read out from each data track coincides with each other when the service is started. CONSTITUTION:When the service is completed, an available value is subtracted from the effective valuable mark information, and it is erased with a reading/ erasing part 22 in common for all data tracks. When the service is started, it can be permitted when the effective valuable mark information read out from each data track coincides with each other. Thereby, it is possible to suppress the consumption of mechanical and electrical energy without performing erasure and confirmation at every frequency of use.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a card processing device for processing a card equipped with a data track and a timing track.

[Prior Art] Conventional card processing devices use so-called card readers/writers that have both the function of reading the remaining power recorded on the card and the function of rewriting the remaining power. In particular, magnetic card readers that handle magnetic cards are used.・Writers (hereinafter referred to as card readers) are often used. However, since this card reader has a writing function, it is possible to illicitly modify the card, and an erasing type card reader that only has the function of erasing the remaining power that has been written on the card in advance is considered. ing. This erasing type card reader prevents unauthorized use of the card by checking whether or not the erased portion has been erased each time the number of degrees recorded on the card is erased.

[Problems to be Solved by the Invention] The conventional card processing device described above performs erasure confirmation every time the frequency recorded on the card is erased.

In order to erase and confirm erasure every time, the erasing point must be moved back and forth frequently to the position of the erasing head and the reading head, which consumes a lot of mechanical and electrical energy. The problem was that it was not possible to reduce power consumption.

[Means for Solving the Problems] In order to solve the above problems, the first invention of the card processing device of the present invention is to subtract the usage value at the end of the service and transfer the corresponding valid value mark information to the card according to the address. All data tracks in the data track are erased in common, and the service is permitted when the valid value mark information read from each data track at the start of the service matches.

In addition, the second invention provides mark information obtained by subtracting "1" from the effective value mark information at one timing 1 at the start of the service.
The configuration is such that only the hard disk is erased and the service is permitted when this erasure is confirmed by a reading sensor.

Further, in a third invention, the address determining means for determining the address of the valid value mark information recorded on each data track is configured to count timing pulses read out from the timing track.

Further, in a fourth aspect of the present invention, the above-mentioned address is determined by address data read from a plurality of address tracks recorded on the card.

Further, in the fifth invention, the above address is obtained by combining address data read from a plurality of address tracks recorded on the card, a counting means for counting repetitions of the address pattern, an output of this counting means, and the address data. The configuration is such that it is determined by calculating .

Moreover, the sixth invention is configured to check the valid value mark information erased at the end of the service on all data tracks.

Further, the seventh invention is provided with means for allocating an address number in a complementary relationship to the number indicating the valid value mark information and calculating the other number from the obtained one number.

[Effect 1: When the service ends, the usage value is subtracted from the effective value mark information and erased in common to all data tracks, and when the service starts, the service is permitted when the effective value mark information read from each data track matches. Ru.

Also, when starting the service, "1" will be displayed from the effective value mark information.
The reduced mark information is erased from one timing track and service is granted when this erasure is confirmed.

Further, the address of the valid value mark information recorded on each data track is determined by the timing pulse read from the timing track.

Further, the address of the validity mark information is determined by address data read from a plurality of address tracks recorded on the card.

Further, the address of the valid value mark information is determined by calculating the address data and a value obtained by counting the number of repetitions of the address pattern.

Furthermore, the valid value mark information that is deleted at the end of the service is checked on all data tracks.

Further, an address number is assigned in a complementary relationship to the number indicating the valid value mark information, and the other number is calculated from the obtained one number.

[Implementation! 4] Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment in which the card processing device of the present invention is applied to a card-type public telephone. In the figure, 21 is a CPU that controls this card processing device;
22 is a reading/erasing unit that reads and erases the power recorded on the card; 23 is a thermal head driver that drives the reading/erasing unit 22 to erase the power recorded on the card; and 24 is a card transporter. Card transport mechanism, a
is a billing signal coming from a line (not shown). The reading/erasing section 22 is configured as follows. That is, SAI, SA2, SBI, 5E12, S
CI, SC2 and SD are sensors for reading cards, and Hl and H2 are heads for erasing the card's power.

Next, FIG. 2 is a block diagram showing the structure of a card used in this card processing device. In the figure, 25 is a card, TI, '1' 2 is a data track where data, that is, frequency is recorded, T3 and T4 are address tracks, and T5 is a timing track. The card 25 is then conveyed in the direction of the arrow and returned in the opposite direction.

Among the heads and sensors described above, sensors SAI and SA2 are arranged linearly in a direction perpendicular to the card conveyance direction, and heads H1 and H2 and sensors SC
I, SC2, and SD are similarly arranged linearly in a direction perpendicular to the card conveyance direction (hereinafter referred to as the head axis), and sensors SBI and SB2 are also arranged linearly in a direction perpendicular to the card conveyance direction. Among these heads and sensors, sensor SAI, head H1, and sensor SBI are arranged linearly in the card conveyance direction, that is, in the horizontal direction,
Also, sensor SA2. Head I]2. Sensor SB2 is also arranged linearly in the horizontal direction.

In this embodiment, the distance between the sensors SAl, SA2 and the head axis corresponds to 3P of timing pulses recorded on the timing track T5, that is, 3 pulses, and the distance between the head axis and the sensor SBI , S.B.
2 corresponds to two timing pulses, but the distance between them may be any number of pulses.

Next, FIG. 3 is a timing chart showing the timing of the patterns recorded on each track of the unused card 25. Figures (a) and (b) show the pulse waveforms of the frequency part recorded on the data tracks TI and T2, respectively, and each shows 10 pulses, that is, the frequency part ■~[stock] (effective value mark Information> is recorded on the data tracks TI and T2.The frequency parts ■~[stock] recorded on the data tracks TI and T2 are the heads)It,
H2 erases only the part corresponding to the power used in the direction from the power part ■ to the power part [phase] shown in the figure, and this erased part is erased by the sensor SA provided correspondingly.
I, SA2 or sensors SBI, SB2.

3C and 3D show the waveforms of the address pulses recorded on the address tracks T3 and T4, respectively, and 1 to 17 in the drawings indicate address values. 1 is the start address value and 17 is the end address value, both of which are address track T3.
, the value of the address pulse on T4 is "1".

If the number of address tracks is n, then an address pattern of 2'' is recorded.In the case of this embodiment, the number of address tracks is 2, so the address pattern is 22-4.

That is, on the address track Tl, 1001
..., 1010 and 1010 are connected in series on the lower 2 address tracks.
The address pulse pattern of ... is recorded, and if this is read out in parallel by sensors SCI and SC2,
Four patterns of 11, 00, 01, and 10 can be read out as one cycle. In addition, in the case of this example,
The number of address patterns is 4, but the frequency part is 1.
Since the number of degrees is 0 and the number of degrees is greater, the cycle of the address pattern is counted and the address value is determined from the counted result and the value of the address pattern at this time.

Note that when the number of address tracks is large, and therefore the number of address patterns is large, values read out in parallel by sensors provided correspondingly may be used as address values.

Alternatively, a count value obtained by detecting and counting timing pulses on the lower timing track 5, which will be described later, may be used as the address value. And this address track T
3. The value of the address pulse recorded on T4 is detected by corresponding sensors SCI and SC2. In addition, this address value 1 to 17 and the frequency part ■
~ The positional relationship of [phase] is complementary. For example, the sum of the address of a certain power part and the address value located in the vertical direction is the number 14, and the position of a certain power part is known in advance. If so, you can also calculate the address value.

In addition, (e) shows the waveform of the timing pulse recorded on the timing track T5, and as shown in the figure, timing pulses based on the ``rl'' and ``OJ times signals at constant time intervals are recorded. S
Detected by D.

Next, FIGS. 4 to 6 are timing charts showing an overview of the operation of this card processing device. In addition, each of (a) to (e) in FIGS. 4 to 6 is a data track T.
1 is a timing chart corresponding to l-timing track T5. An outline of the operation of this device will be explained based on FIGS. 4 to 6.

When the card 25 is inserted into the insertion slot for making a call, the CPU 21 causes the card 25 to be conveyed to the card conveying mechanism 24, and scans and controls the sensor SD to detect timing pulses on the lower timing track 5 of the card 25. is scanned, and when the "1" portion of this timing pulse is detected, the sensors SCI and SC2 are scan-controlled to detect the respective address pulses on the address tracks TI and T2. Then, the address pulses are both rl,
When this address is reached, this address is recognized as the start address 1.

Next, data track T is detected by sensors SBI and SB2.
In order to detect the frequency part ■ to [phase] on T1 and T2, the card is further controlled to transport, and as shown in FIG. The position where the power part ■ ~ [phase] are both “0”,
In the example shown in this figure, it is conveyed to the degree section ■. This frequency part ■ is the maximum erase value of the card 25. Note that the position of the head axis at this time, that is, the address value, is calculated by the following equation.

Address value = 2AT'3 +AT4 +4N-2 Here, Ar1 and Ar1 are respectively sensor SCI and
This is the value of the address pattern read by SC2, and N is the number of pattern cycles counted until this address value is reached.

However, it is counted as one time at the start address ATS. And at this time, Ar1. , Ar1 are both "1",
Also, since N is 1, the address value=2X1+1+4X1-25.

Further, FIG. 5(a) shows an example in which the frequency part 3 on the data track TI is not erased for some reason. In such a case, the CPU 21 performs error processing.

Then, as shown in FIG. 4, the card 25 is conveyed to the position of the frequency section ■, and the data track TI is moved.

When it is detected that both of the frequency parts ■ on T2 have been erased and become "0", and furthermore, when the charging signal a indicating the start of a call is received, as shown in (a> CPU
2L causes the thermal head driver 23 to drive the head H1 to erase the power part (■) indicated by the dotted line. That is, an address is calculated by subtracting one degree from the maximum erase value of the card 25, the card 25 is transported to this position, the head H1 is made to face the degree part ■ on the data track TI, and only this degree part ■ is written. Make it disappear.

Note that the address value of the head H1 relative to the power part ■ at this time is 8, since the address of the power part ■ is 8.
1l-8=6. In addition, as a countermeasure in case the used call frequency is not deleted for some reason, the frequency section (■) on the bottom 2 of the data track is not deleted.

After that, the card 25 is conveyed again and the sensor SAI
This frequency part (2) is made to be relative to the other, but in this case, if the maximum address value is 17, the address of the frequency part (2) is 8, so the address value is 17-8=9.

Then, the card 25 is conveyed so that the address value 9 reaches the position of the head axis, and the sensor SAI is caused to detect whether or not the frequency part (3) has been erased.

Thereafter, when the call ends, the CPU 21 transports the card 25 to the position corresponding to the call frequency, and the head H1,
H2 erases a predetermined frequency portion on the data tracks T1 and T2.

If 2 frequencies are used in this call, the maximum frequency to be erased is 7, so the frequency to be erased is 7mo2=9, and the frequency part ■ is erased. After the part corresponding to the number of calls is erased in this way, the CPU
21 transports the card 25 to return it, and at this time, the erased frequency part (3) is checked by sensors SBI and SB2.

Note that the positions of sensors SBI and SB2 are 2 points from the head axis.
The position of the vertical power part of the point where this sensor is located and the position of the head axis are complementary, and the sum of these positions, that is, the address, is always 12. It remains constant. Therefore, when the sensors SBI and SB2 face this erased frequency part ■, the address value is 1.2-9 = 3, and the card 25 is conveyed so that the position of this address value 3 reaches the head axis. Then, the sensors SBI and SB2 check the erasure of the frequency part (2).9 Next, the detailed operation of the card processing apparatus of the present invention will be explained based on the flowchart of FIG.

When the card 25 is inserted, the CPU 21 controls the conveyance of this card, and thereafter, in step 50, the output of the sensor SD facing the timing track T5 becomes "0".
It is determined whether the value has changed from "1" to "1". Then, “N
”, wait until it changes to rl, and when “Y”, all the sensors are scanned in step 51, and in step 52, in order to detect the starting position of the card 25, the sensor SCI is selected in particular from among these sensors. , SC2 are both "1".

If this is "N", the process returns to step 50 and "
“Y” means that the start position has been detected.
In step 53, it is determined whether the output of the sensor SD has changed from "0" to "1". And when "N", "
Wait until it changes to ``1'', and if it is ``Y'', go to step 54.
In step 55, all the sensors are scanned, and in particular, sensor SBI or sensor SC2 is scanned.
It is determined whether the output of is r□. If "N", the process returns to step 53, and if "Y", then in step 56, it is determined whether or not both sensors SBI and SB2 become "0".

If the result in step 56 is "N", as will be described later, this means that the card 25 has not been erased even though it has been used, and error processing is executed in step 57. If the result in step 56 is [Y], it means that the card 25 is normal, and in step 60 the card 25 is normal.
In step 61, the position of the head H1 for erasing the power portion obtained by subtracting one power from the remaining power of the card 25 is calculated, and in step 62, the card 25 is stopped.

After that, when the calling party makes a dial call, it is determined in step 63 whether or not the charging signal a has arrived in response to the called party's response. Y", that is, if the card 25 can be received, the card 25 is re-transferred in step 64. Then, in step 65, the output of the sensor SD becomes "0".
” to determine whether “l” has changed. and,"
If the answer is "N", wait until it changes to rl; if the answer is "Y", all the sensors are scanned in step 66, and in step 67 the check is made to see if the part of the card 25 to be erased once has come to the position of the head H1. to judge. If "N", the process returns to step 65.

When the result in step 67 is "Y", it means that the card has been conveyed to the predetermined position, and in step 70, the head H1
The predetermined number of degrees of the data track T1 in the card 25 is erased. Then, in step 71, the position of the sensor SAl for detecting the erased location is calculated, and in step 72, it is determined whether the output of the sensor SD has changed from "0" to "1". And when "N", "1"
”, and if it is “Y”, all sensors are scanned in step 73, and in step 711 it is determined whether the erased portion of the card 25 has come to the position of sensor SAl. If "N", the process returns to step 72.

When “Y” in step 74, that is, card 2
When the erased portion of No. 5 reaches the position of sensor SAI, it is determined in step 75 whether the output of sensor SAI is "0". When this is "N", head H
1, the data track T1 portion of the card 25 could not be erased, so error processing is performed in step 57.

If the answer is step ``Y'', the card 25 is stopped in step 76, and the end of the call is determined in step 77. If it is "N", the call waits until the end of the call, but during this time, the charging signal a arrives every predetermined call time, and the call frequency corresponding to this charging signal a is determined by the CPU.
8IX is stored in the built-in memory of 21.

Then, when the answer is "ry" in step 77, that is, when the call ends, the remaining number of credits is calculated based on the number of credits used in step 80, and the return transportation for returning the card 25 is performed in step 81. Then, in step 82, it is determined whether the output of the sensor SD has changed from r□ to "1".

If it is "N", wait until it changes to "1", and then "
If "Y", all sensors are scanned in step 83, and it is determined in step 84 whether or not the card 25 has come to the position where it is to be erased. If this is rN, the process returns to step 82.

When "Y" is determined in step 84, that is, if the card 25 is transported to the position where it is to be erased, the head H is
3. H2 erases a predetermined degree portion of the data tracks T1 and T2, and in order to check whether this erased portion has been erased, the output of the sensor SD is
It is determined whether or not the value has changed from "0" to "1". and,
If "N", wait until it changes to "1", if "Y", all sensors are scanned in step 87, and in step 88, the erased part of the card 25 is detected by sensor SBI,
It is determined whether or not the object has been transported to the position of SB2. When this is r N J, the process returns to step 86.

When "Y" is determined in step 88, that is, when the card 25 is conveyed to the position of the sensor SBI and SB2, the sensor SBI is transferred in step 89.

It is determined whether the outputs of SB2 are both r□. If this is "N", it means that the heads H1 and H2 could not erase, and error processing is performed in step 57. In addition, if "YJ" in step 89, that is, if the data can be erased normally, it is determined in step 90 whether the output of the sensor SD does not change, that is, whether the card 25 has been returned, and if "N", the card 25 has not been returned. Wait until it is returned, and if it is "Y", that is, it is returned, the process ends.

In this embodiment, a thermal head was used as the erasing head and a magnetic sensor was used as the reading head, but a puncher for making a hole in the card was used as the erasing head, and the reading head was composed of a light emitting element and a light receiving element. Alternatively, an optical sensor may be used.

In addition, the erase head includes an element that changes the reflectance of the card.
For example, a thermal head using a thermal card or an ink stamp element may be used, and an optical sensor such as a light receiving element may be used as the reading head.

Further, in this embodiment, an example in which the card processing device is applied to a card-type public telephone has been described, but the present invention is not limited to a card-type public telephone, and may be applied to other card systems.

[Effects of the Invention] As explained above, the card processing device of the present invention subtracts the usage value from the effective value mark information and deletes it in common from all data tracks when the service ends, and erases it from each data track when the service starts. Since the configuration is such that the service is permitted when the read valid value mark information matches, there is no need to erase and confirm erasure every time, thus reducing mechanical and electrical energy consumption. This has the effect of making it possible to configure a device with low power consumption.

Also, when starting the service, "1" will be displayed from the effective value mark information.
Since the reduced mark information is erased from one timing track and the service is permitted when this erasure is confirmed, there is an effect that the quality of the card can be judged at the start of the service.

In addition, since the address of the valid value mark information recorded on each data track is determined by the timing pulse read from the timing track, an advantage is obtained in that addresses can be detected without providing an address track. be.

Further, since the address of the valid value mark information is determined by address data read from a plurality of address tracks recorded on the card, there is an effect that reliable address detection can be performed.

Furthermore, since the address of the effective value mark information is determined by calculating the address data and the value obtained by counting the repetition of the address pattern, the effect is that a large amount of effective value mark information can be held in a small number of address tracks. be.

Furthermore, since the valid value mark information erased at the end of the service is checked on all data tracks L, there is an effect that card erasure can be detected reliably.

In addition, the address number is assigned in a complementary relationship to the number indicating the valid value mark information, and the other number is calculated from one number, making it easy to calculate the address. effective.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing one embodiment of the card processing device of the present invention, Fig. 2 is a block diagram of a card used in this card processing device, and Figs. 3 to 6 show information recorded on the card. FIG. 7 is a flowchart explaining the operation of this card processing device. 21...-CPU, 22...Reading/erasing section, 23
...Thermal head driver, 24...Card transport mechanism, 25...Card, Hl, H2...
・Head, SAI, 5A2SBI, SB2, SC
I, SC2, SD---sensor, a---charging signal.

Claims (7)

[Claims] (1) In a card processing device that processes a card having at least a plurality of data tracks in which valid value mark information that can be erased according to an address is recorded and a timing track for reading out the information recorded in the data tracks. , When the service ends, the usage value is subtracted and the corresponding valid value mark information is deleted from all data tracks according to the address, and the service is started when the valid value mark information read from each data track matches when the service starts. Authorized card processing device. (2) In the card processing device according to claim (1), the mark information obtained by subtracting "1" from the effective value mark information at the start of the service is erased by one timing track, and when this erasure is confirmed by the reading sensor, the card processing apparatus is serviced. Card processing equipment that allows (3) A card processing apparatus according to claim (1), wherein the address determining means is means for counting timing pulses read from a timing track. (4) The card processing device according to claim (1), wherein the address is determined by address data read from a plurality of address tracks recorded on the card. (5) In the card processing device according to claim (1), the address is obtained by combining address data read from a plurality of address tracks recorded on the card, a counting means for counting repetitions of the address pattern, and a counter for counting the repetition of the address pattern. A card processing device characterized in that the determination is made by calculating output and address data. (6) A card processing device according to claim (1), characterized in that valid value mark information erased at the end of service is checked on all data tracks. (7) The card processing device according to claim (1), further comprising means for allocating an address number in a complementary relationship to a number indicating valid value mark information and calculating the other number from one of the obtained numbers. card processing equipment.