JPH031524A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To decrease the maximum quantity of the slippage, from the former pattern, of a pattern by exposure in and after the third process so that it may cope enough with high integration such as LSI, etc., by estimating the position of a wafer by the average value of the results of measurement of each position of a wafer using plural alignment marks formed in a preceding process. CONSTITUTION:In the first process, an alignment mark 11 is formed at the same time with formation of a pattern 1. And by detecting this alignment mark 11, and calculating the slippage between the sought coordinates of point P and the preset reference coordinates, and performing the same action at several points on the wafer, the total slippage of the wafer is estimated, and while performing compensation based on it, the exposure of a pattern II is done. In this second process, together with the pattern II an alignment mark 12 is formed. Next, both of the alignment marks 11 and 12 are detected, and the coordinates of point P and point Q are sought and those average is sought, and that is done at several points on the wafer so as to estimate the total slippage of the wafer. Accordingly, the maximum value of the slippage to the pattern in the second process is leveled and decreases.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a method for manufacturing a semiconductor, and more specifically, to a method for manufacturing a semiconductor.
The present invention relates to a manufacturing method suitable for obtaining highly integrated semiconductor devices such as I.

<Prior Art> Overlay exposure is known as a method of exposing semiconductor wafers. In overlapping exposure, a desired overall pattern is obtained by exposing the same wafer surface multiple times with different patterns.

In such overlapping exposure, in order to eliminate pattern deviation between each exposure process, a certain index (hereinafter referred to as an alignment mark) formed on the wafer surface is detected in each exposure process. Then, the position of the wafer with respect to a table or the like is measured, and the deviation between the determined coordinates and the preset coordinates is calculated. By performing this operation at a few points on the wafer, the overall deviation is predicted, and based on the prediction, the table position is corrected during actual exposure.

Figure 2 is an explanatory diagram of the procedure of the conventional overlapping exposure method.
The ideal exposure pattern shown in Figure 3 is shown in Figure 2 (a).
) to (C).

In this example, the alignment mark 11 formed in the first exposure process is used to measure the position of the wafer in the second and third exposure processes, in other words, based on the point P on the wafer. ing.

<Problems to be Solved by the Invention> By the way, even if the above-mentioned operations are performed, it is not possible to completely eliminate pattern deviations in each exposure process due to other factors on the apparatus, and therefore, the overlay process As the number increases, the amount of deviation also increases.

In other words, even if the deviations due to other factors on the apparatus are equal in each direction in each exposure process, and the amount follows a certain distribution, if we consider the procedure in Figure 2 as an example, the second process will be Assuming that the alignment mark 11 (first step) is shifted upward to the right and the third step is also shifted downward to the left, the patterns ■ and ■ of the second and third steps are the patterns of the first step, respectively. The pattern (2) of the third process has a deviation of one time from I, but the pattern (2) of the third process has a deviation of twice the deviation of one time from the pattern H of the second process.

The increase in the maximum amount of pattern deviation due to the increase in the number of overlapping steps has become impossible to ignore as semiconductor devices such as LSIs become highly integrated.

Means for Solving the Problems> The present invention has been made to solve the above problems, and is characterized by the fact that during the exposure after the third step, the at least 2
The position of the wafer is measured based on the above indicators, the differences between the two or more obtained position measurement results and the preset reference coordinates are averaged, and the positional deviation of the wafer is predicted based on the average value. The purpose is to perform exposure using

<Function> For example, the alignment mark formed during exposure in the second step is different from the alignment mark formed during exposure in the first step in both direction and amount.
This is equivalent to the actual deviation from the process pattern. Therefore, in the third step, if the wafer position measurement results from these two alignment marks are averaged, and the wafer position shift is predicted and corrected based on the average value, the other factors mentioned above in the third step can be corrected. Regardless of which direction the deviation occurs, the maximum amount of deviation of the pattern in the third step with respect to the pattern in the first or second step is equalized and reduced.

<Example> Figure 1 is an explanatory diagram of the manufacturing procedure of Example of the present invention.
Similar to the conventional example shown in the figure, an example is shown in which a pattern as shown in FIG. 3 is subjected to overlapping exposure through the first to third steps.

In the first step (a), the alignment mark 11 is formed simultaneously with the formation of the pattern I, as in the conventional method.

In the second step (b), this alignment mark 1
1, calculate the deviation between the obtained coordinates of point P and the preset reference coordinates, and perform the same operation at several points on the wafer to calculate the overall deviation of the wafer. The pattern (2) is exposed while making a prediction and making corrections based on the prediction.

In this second step, alignment marks 12 are formed together with pattern (2).

Next, in the third step (C), both alignment marks 11 and 12 are detected, the coordinates of point P and point Q are determined, the deviation from the reference coordinates is calculated, and the average value of these is determined. . Such operations are similarly performed at several points on the wafer to predict the overall wafer misalignment. That is, in this third step, the positional shift of the wafer is determined based on the coordinates of point R, which is the midpoint between point P and point Q.

The alignment mark 12 created in the second process has a deviation from the alignment mark 11 that is equal to the deviation between the patterns The wafer position will be predicted based on this.

This is based on the same conditions as explained above in FIG.
Similarly, if the process is shifted to the lower left, the second
There is a deviation of 1.5 times the amount of deviation of one time between the pattern ■ and ■ of the process and the third process, but there is a deviation of one time between the pattern I and ■ of the third process and the first process. A deviation of only 0.5 times the amount occurs. Therefore, according to this embodiment, the maximum deviation amount compared to the conventional method is 1.5/2, that is, 3/4
It will be reduced to

It goes without saying that the present invention is also effective for overlapping exposure of four or more steps. An average value may be used, or an average value of position measurement results using two or more appropriate alignment marks may be used.

<Effects of the Invention> As explained above, according to the present invention, the wafer position is predicted based on the average value of each position measurement result of the wafer using the plurality of alignment marks formed in the previous process. The maximum amount of deviation of the pattern from the previous pattern due to exposure in the third and subsequent steps has been reduced, and it has become possible to sufficiently cope with high integration of LSI and the like.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of the manufacturing procedure according to the embodiment of the present invention, Fig. 2 is an explanatory diagram of the conventional manufacturing procedure, and Fig. 3 is an illustration of the ideal pattern to be manufactured by the procedure of Figs. 1 and 2. It is an explanatory diagram. 11... Alignment mark 12... Alignment mark

Claims (1)

[Claims] In a method of forming a pattern on the wafer by exposing the wafer surface in at least three steps or more, the exposure patterns of each step are superimposed on the wafer. The position of the wafer is measured based on at least two or more indicators formed respectively, the differences between the two or more obtained position measurement results and preset reference coordinates are averaged, and the wafer is positioned based on the average value. 1. A method of manufacturing a semiconductor device, characterized in that exposure is performed by predicting a positional shift of a semiconductor device.