JPH03150798A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To relieve the defective cells with higher efficiency by performing the switching connection between the normal and redundant cell trains for each of divided cell array blocks. CONSTITUTION:A semiconductor memory device has a multi-bit input/output constitution, i.e., a memory cell array divided into blocks 11 - 1m. Each of these blocks consists of normal cell trains 21 - 2n. The memory device is provided with the redundant cell trains 31 - 3m and the switching circuits 51 - 5m containing the information storage circuits 41 - 4m respectively. Then the trains 21 - 2n can be replaced with the trains 31 - 3m for each of blocks 11 - 1m. Therefore the defective bits produced dispersedly among those blocks can all relieved. Then the yield is improved for the semiconductor memory device.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a technique for providing redundancy in semiconductor memory devices, particularly in memories with a multi-bit input/output configuration, and aims to more efficiently repair defective cells and improve yields. A memory cell array divided into a plurality of blocks, each block consisting of a plurality of regular cell columns, a plurality of redundant cell columns provided corresponding to each of the plurality of blocks, and a plurality of redundant cell columns provided corresponding to each of the plurality of blocks. a plurality of switching circuits each provided with an information storage circuit provided corresponding to each block and in which address information of a word line or column line to which a defective bit belongs is written in advance;
The switching circuit is configured to switch and connect the regular cell string and the redundant cell string for each corresponding block based on the contents of each information storage circuit in the plurality of switching circuits.

[Industrial Field of Application] The present invention relates to a semiconductor memory device, and particularly to a technique for providing redundancy in a memory having a multi-bit output configuration.

Memories with redundant cells are advantageous in that manufacturing yields can be improved, especially in large-capacity memories. However, since it is not possible to predict in which of the (regular) cells scheduled to be used a defective bit will occur, problems arise in how to set up redundant cells and how to switch between redundant cells and defective cells. Therefore, there is a need for a technology that effectively utilizes a limited number of redundant cells to effectively provide redundancy.

[Prior art and problems to be solved by the invention]

FIG. 6 schematically shows a configuration example of a conventional redundancy system.

In the illustrated example, the memory cell array includes four blocks 61.
It is divided into ~B4, and each block is further divided into four columns (
CCro~CC1x, =..., CCao =CCa
z). In other words, it has a 4-bit input/output configuration. Additionally, four redundant columns (RCC+-RC
A redundant cell block 86 divided into cells is provided.

According to this configuration, for example, if a defective cell (defective bit) is included in the column CC□ of the second cell block B2, the switching means (not shown) switches between the cell block B2 and the redundant cell block B0. A switching connection is made with. In other words, 4 bits are made redundant at the same time in block units.

Originally, many defective cells are caused by crystal defects, so if multiple defective bits occur, the probability that the multiple defective bits will be concentrated in the same block is:
This is considered to be extremely low compared to the probability that defective bits are distributed and present in each block. In other words, if a plurality of defective bits were to occur, there is a high probability that they would be distributed in each block.

Therefore, with the system that performs redundancy in cell block units as shown in Figure 6, there is no problem if only one defective bit occurs, but if multiple defective bits occur distributed in each block, It becomes impossible to repair all of the defective bits. Therefore, a problem arises in that the repair rate for defective cells is low, and the yield of good products is lowered.

Therefore, considering that the capacity of memory will continue to increase in the future, it is difficult to expect an improvement in yield with the current redundancy system.

The present invention was created in view of the problems in the prior art, and aims to provide a semiconductor memory device that can repair defective cells more efficiently and improve yield.

[Means to solve the problem]

In order to solve the above problem, the present invention focuses on the fact that when multiple defective bits occur, there is a high probability that they will occur distributed across each cell array block, and each cell array block has a normal cell column and a redundant bit. The structure is such that the cell rows can be switched and connected.

Therefore, according to the present invention, as shown in the principle block diagram of FIG. 1, there is provided a semiconductor memory device having a multi-bit output configuration, which comprises a memory cell array divided into a plurality of blocks . Each block is composed of a plurality of regular cell columns 2l to 2n, and a plurality of redundant cell columns 3 are provided corresponding to each of the plurality of blocks. ~
3#l, and information storage circuits 41 to 4 provided corresponding to each of the plurality of blocks and in which address information of the word line or column line to which the defective bit belongs is written in advance.
A plurality of switching circuits 5I to 5I each having a
11, the semiconductor memory device is characterized in that the switching connection between the normal cell column and the redundant cell column is performed for each corresponding block based on the contents of each information storage circuit in the plurality of switching circuits. provided.

[Operation] According to the above-described configuration, a normal cell column (including a defective bit) is replaced with a redundant cell column for each cell array block divided into a plurality of cells. Therefore, when a plurality of defective bits are distributed and generated in each block, it is possible to repair all the defective bits, thereby improving the yield.

Note that other structural features and details of the operation of the present invention will be explained using the embodiments described below with reference to the accompanying drawings.

[Embodiment] FIG. 2 shows a circuit configuration of a semiconductor memory device as an embodiment of the present invention.

The memory of this embodiment has a 4-bit human output configuration (so-called
4-bit configuration), the memory cell array is divided into multiple blocks, and each block has four regular columns lO0.
~103 (CC,.~CC+j, CCto~CCt
) and one redundant column 11 (RCC
l, RCCz.

It consists of...). The structure of each column will be explained in detail later.

Reference numeral 12 denotes a data manual buffer, which buffers the data in response to the 4-pinto manual data D1.4 and outputs a total of four pairs of complementary input data along with complementary signals of each bit. 13 indicates a light amplifier;
In response to an external write enable signal WEX, the 4-bit complementary input data from the data manual buffer 12 is amplified, and the corresponding pair of data lines, DX,
,~03. Output to DX3. For each data line pair, DX
, ~IDXI are the corresponding columns IO0~l, respectively.
Connected to Oz. 14°.

14X, ~14i, and 14h are npn type transistors constituting emitter followers, respectively;
Corresponding columns IO0 to 10z and data line pair D
0°, OX,. ~mouth,. , DX3°. Also, 15° to 153 are respectively for the data line pair,
. ,DX6゜～mouth. 9 mouths X. a sense amplifier (S/A) for amplifying the data appearing on the S/A;
Buffer the data from A and output data D
. . 7 shows a data output cover sofa that is output to the outside.

Reference numeral 20 denotes a row address buffer and decoder, which buffers the row address signal RAdd and selects one of the plurality of word lines 'HL and -WLn. This word line l1IL.

. . . -Ln are arranged in common in each column described above (in the illustrated example, in the vertical direction of the paper surface). Similarly, 21 is a column address buffer and decoder, which is a circuit for buffering the column address signal CAdd and selecting one of a plurality of decode lines DEC (four in the illustrated example). .

22° to 221 indicate fuse elements made of polycrystalline silicon or the like, and columns IO0 to IO10. and a specific one of the decode lines DEC.

Further, 23, 23X and 24 each indicate a switch (described later) including a fuse element. The switch 23 connects one of the complementary data lines DX connected to the redundant column 11 and one of the data line pairs 00 to 0. The switch 23X is connected between the other complementary data line DX
and the other DX, DX, of each data line pair. The switch 24 is connected between the plurality of decode lines DEC and the redundancy column 11.

In addition, switches 23 and 23 are installed on the output side of the redundant column it.
A switch 25.25X having the same configuration as X is provided.

26 and 26X indicate emitter followers (described later).

The emitter follower 26 is connected to the switch 25 and each data line pair 0. . ,DX,. ~D. ,DX,. - Yoiguchi.

. ~mouth,. emitter follower 26X
are the switch 25X and the other DX of each data line pair. ~D
X. is connected between.

Next, regarding one configuration example of the column part in FIG.
This will be explained with reference to the figures. Note that each column has the same configuration, so in the illustrated example, column 10a (CC+e)
are shown representatively.

The illustrated column includes a plurality of memory cells MC, ~MCn connected between complementary bit lines BL, BLX and responsive to the levels of word line holes ~-Ln, respectively, and a decode signal DS on a selected decode line. Bit line B in response
P-channel transistors 30 and 30X connect L and BLX to corresponding data lines OL and DLX, an inverter 31 that responds to decode signal port S, and decode signal O
8 and one of the data line pair, a NOR gate 32X that responds to the decode signal O8 and the other data line pair DX, and each output terminal and data line port of the NOR gate 32.32X. The inverter 33.33X connected between DLX and 4 which receives the high potential power supply voltage VCC and constitutes a current switching type switch in response to the signals on the data lines OL and BLX.
npn type transistors 34.34X, 35.35X
and n-channel transistors 36.36X and 37, which function as constant current sources for transistors 34.34X and 35.35X, respectively, in response to the output of inverter 31, and transistors 35. It is composed of a P-channel transistor 38, which functions as a collector resistor of 35X, and a 38X collector resistor.

In the configuration shown in FIG. 3, when the decode signal port S is at "L" level, the column is in the selected state. In this case, the transistors 30 and 30X are turned on, so the data level of the memory cell corresponding to the selected word line is transferred to the data lines DL, DI, and X via the bit lines BL and BLX and the transistors 30 and 30X. communicated. In addition, since the output of the inverter 31 is at the "11" level, the transistors 36, 36X and 37 each function as an original constant current source, thereby causing the current switching type switch (3
4,34L 35.35X) performs a predetermined operation. As a result, one of the collector potentials of the transistors 35.35X becomes "H" level and the other becomes "L" level, and in response, one of the emitter followers 14° and 14X6 is turned on and the other is turned off. Therefore, a pair of data lines D0°,
DX*. A pair of complementary data is outputted to, and the complementary data is input to the corresponding S/A and amplified, and then read out to the outside.

On the other hand, when the decode signal DS is at the "II" level, the column is in a non-selected state. The operation in this case can be inferred from the above operation, so the explanation thereof will be omitted.

Note that when the column shown in FIG. 3 is applied as a redundant column, the signal of the decode line switched and connected by the switch 24 is input as the decode signal, and the data switched and connected by the switches 23 and 23X is input as the data. The signal on the line and DX is input. Further, the complementary signal lines taken out from the redundant columns are switched and connected by switches 25.25X, respectively, and then connected to complementary data lines D0°, DX6° to O1°, and DXi via emitter followers 26.26X. Connected to either pair.

Next, configuration examples of the switch and emitter follower in FIG. 2 will be described with reference to FIGS. 4 and 5.

First, referring to FIG. 4, each switch used in this embodiment has a high potential power line vCC and a low potential power line Vl! f! A fuse element F connected in series between
~F1 and high-resistance resistors P, ~6, and each node NO~N3 of the information storage circuit.
The inverter IVo "" IV3, which responds to the potential of the fuse element and the resistor (connection point of the fuse element and the resistor), constitutes a transfer gate, and the p-channel responds to the potential of the node No-N3 and the output of the inverters IV6 to IV, respectively. Transistors QP, ~QP.

and n-channel transistors N0 to QN.

The information storage circuit is a circuit for semi-permanently storing address information of a column line to which a defective bit belongs, that is, a data line or a bit line.

If it is found that a defective cell (defective bit) is included in the column, in the case of the switch 23, the fuse element F0 corresponding to the data line of the column is cut by a laser or the like. As a result, the level of node NO is “L” level (
VEPs) and transfer gates ((IPo, Q
Each time Ne) becomes open, the data lsD on the redundant column side and the data line are connected. On the other hand, the other fuse elements remain connected, so the levels of each node N1 to N3 are relative to each other. “H Lebel (VCC)”
), the corresponding transfer gates are not conductive, and in the end, only the data line and 00 are connected.

Next, referring to FIG. 5, the emitter follower 26.26X used for the redundant column clamps the base potential of the npn transistors 10 to ↑3 to the "L# level (VF!B)" when non-redundant. It is composed of four sets of circuits consisting of resistors OR, to DR2.

An example of a redundancy method in the memory of this embodiment will be described below.

For the sake of simplicity, let's assume that the memory cell array is divided into two blocks, and that columns 10 and 10 in the first block (second block). (Assume that 10 bits include a defective bit.

In this case, regarding the first (second) block, the fuse element 22 .corresponding to the column concerned. (22□), fuse element F of switch 23 corresponding to data line D1 (0□)
, (F,), data line DX+ (DXz) D, fuse element P+ (Ft) of the corresponding switch 23X, fuse element Fl (P) of the switch 24 corresponding to the decode line
K), data line entrance. Switch 2 corresponding to (010)
No. 5 fuse element p+ (pg) and data line DX
The fuse elements p+ (pz) of the switch 25X corresponding to ++ (DXz.) are each cut with a laser or the like.

This results in column 10 containing the defective bit. (10,
) are inactive, while the complementary data lines, , OX
.

(The D21 port is connected to the complementary data line 1OX on the redundant column side via the switch 23.23X, and is further connected to the complementary data line D+o, DX+o (Dye, DXto
) 2 connection rail (7) TE, the redundant column 11 becomes active. That is, in the first and second blocks, the defective columns 101, 10□ are respectively replaced with redundant columns 11, and all defective cells (2 bits in this case) are relieved.

As described above, according to the configuration of this embodiment, switching connections between regular columns and redundant columns are performed for each cell array block. Therefore, although the conventional method of providing redundancy in units of cell array blocks sometimes made redundancy impossible as described above, when the number of redundant cells provided in the memory is the same, compared to the conventional method, Defective cells can be repaired more efficiently. As a result, it becomes possible to significantly improve the yield.

In the above-described embodiment, the memory cell array is divided into a plurality of blocks, and each block is configured to switch between redundant columns (cell rows) and regular columns (cell rows). As is clear from the summary, the redundancy method is not limited to this.

For example, when providing redundant cell rows for each block, instead of providing them for the regular columns divided in each block, they are provided for the cell rows in the word line direction in each block. It may be configured to switch between redundant rows (cell rows) and regular rows (cell rows), but in this case, the information storage circuit (see Figure 4) consisting of fuse elements and resistors is written with the address information of the word line to which the defective bit belongs.

〔Effect of the invention〕

As explained above, according to the present invention, defective cells can be repaired more efficiently than before by switching and connecting normal cell columns and redundant cell columns for each cell array block divided into a plurality of parts. Can be done. This contributes to improving yield, and this effect becomes more pronounced as the memory capacity increases.

[Brief explanation of the drawing]

FIG. 1 is a principle block diagram of a semiconductor memory device according to the present invention, FIG. 2 is a circuit diagram showing the configuration of a semiconductor memory device as an embodiment of the present invention, and FIG. 3 is a diagram showing the configuration of a column section in FIG. 4 is a circuit diagram showing the configuration of the switch in FIG. 2, FIG. 5 is a circuit diagram showing the configuration of the emitter follower in FIG. 2, and FIG. 6 explains an example of the conventional redundancy system. This is the configuration diagram for doing this. (Explanation of symbols) 1, ~1m... (cell array) block, 2, ~2n
... Regular cell row, 31-3m... Redundant cell row, 4, -4-... Information storage circuit, 51-5-... Switching circuit. Figure 2 is a circuit diagram showing the configuration of the switch shown in Figure 4. A circuit diagram showing the configuration of the emitter follower in Figure 2.

Claims (1)

[Claims] 1. A semiconductor memory device with a multi-bit input/output configuration, comprising a memory cell array divided into a plurality of blocks (1_l to 1_m), each block having a plurality of regular cell rows (2_l to 1_m). ~2_n), a plurality of redundant cell columns (3_l to 3_m) provided corresponding to each of the plurality of blocks, and a plurality of redundant cell columns (3_l to 3_m) provided corresponding to each of the plurality of blocks to which the defective bit belongs. A plurality of switching circuits (5_l to 5_m) each including an information storage circuit (4_l to 4_m) in which address information of a word line or a column line is written in advance, each information storage circuit in the plurality of switching circuits. 1. A semiconductor memory device characterized in that a normal cell column and a redundant cell column are switched and connected for each corresponding block based on the contents of the cell column. 2. The information storage circuit includes the same number of fuse elements as the plurality of regular cell columns, and the address information indicating the defective bit is defined by cutting any one fuse element. The semiconductor memory device according to claim 1.