JPH03150600A - Method for conversion decoding and conversion decoder - Google Patents

Abstract

PURPOSE:To reduce the influence of block distortion which causes the generation of a noise or deterioration in quality by processing a decoded signal at the border of blocks selectively by a filter. CONSTITUTION:Block border parts between (k-1)th and (k)th, (k)th and (k+1)th, and (k+1)th and (k+2)th blocks are denoted as (a) - (c) and parts other than the block borders (a) - (c) are denoted as A - C. Namely, the (k)th block consists of a half of (a) and a half of (b) and the (k+1)th block consists of a half of (b) and a half of (c). A selector 24 selects and outputs the output of the conver sion decoder 21 which is delayed by a delay element 27 at A - C and the output of the filter 22 at (a) - (c). The filter 22 has low-pass characteristics so as to reduce the sensation of the block distortion by smoothing the signal at the block borders. Consequently, the influence of the block distortion which causes the generation of a noise and deterioration in quality is reducible.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to band compression technology for signals such as voice/music, and in particular to band compression technology that performs band compression after linearly converting an input signal obtained in the time domain to another domain. Regarding decoding techniques.

(Prior art) Bandwidth compression is the process of reducing the amount of information contained in audio/music signals using lines with limited transmission capacity in order to efficiently transmit the information. Adaptive differential pulse code modulation [AD PCM] (digital
Coding on Waveforms, (Di
Digital Coding of Waveforms
), Prentice Hall Co.
e-Hal 1), 1984, p. 308; (hereinafter referred to as "Reference 1")) and adaptive transform coding [ATC]
(IEE Transactions on
Ainis Sp (IEEE TRANSACTION
S ON ASSP) Volume 27, No. 1, 1979, 89
-95 page reference: (hereinafter referred to as "Reference 2")) is known.

The outline of ATC will be briefly explained below according to Document 2.

FIG. 5 is a block diagram showing an example of the configuration of the ATC. In an encoder comprising linear transformation, bit allocation, and quantization, an input signal is supplied to a linear transformation circuit 3 via an input terminal 1. In general, discrete values are supplied to the input terminal 1, and a linear transformation circuit 8 performs N-point discrete linear transformation in units of input samples equal to a predetermined integer N. N is called the block length. As this N-point discrete linear transformation,
Walsh-7 Damard transform (WAT), discrete Fourier transform (DFT), discrete cosine transform (DCT), KL transform (KLT), etc. are used. The total number N of transform coefficients output from the linear transform circuit 3 are each quantized by a quantizer 4 according to a bit allocation to be described later, and then supplied to a multiplexing circuit 5. The quantizer 4 includes a number of quantizers equal to the block length N, and each transform coefficient is quantized by a dedicated quantizer. The bit allocation circuit 6 calculates the quantization bit allocation corresponding to the amplitude of the transform coefficient and supplies it to the quantizer 4. The multiplexing circuit 5 multiplexes the quantized transform coefficients supplied from the quantizer 4 and the information used for bit allocation supplied from the bit distribution circuit 6, and sends the multiplexed information to the transmission line 8.

In the decoder, which consists of bit allocation, inverse quantization, and linear inverse transformation, the multiplexed signal from the transmission line 8 is separated by a separation circuit 9, and the signal from the quantizer 4 is sent to the inverse quantizer 10, which performs bit allocation and linear inverse transformation. The signal from circuit 6 is supplied to bit allocation circuit 11. The bit allocation circuit 11 determines the bit allocation for each transform coefficient in exactly the same manner as the bit allocation circuit 6 of the encoder.

The transform coefficients dequantized by the dequantizer 10 according to the bit allocation determined by the bit allocation circuit 11 are converted again into a total number N of time domain signal samples by the linear inverse transform circuit 12, and are sent to the output terminal 14. Supplied.

There are several types of allocation methods in bit allocation circuits, but here we will use the method described in Document 2 as the sixth method.
This will be explained with reference to Figures (a) and (b).

This method minimizes the squared quantization error when dequantized in the decoder. In order to reduce the amount of auxiliary information regarding bit allocation, the transform coefficients are thinned out once, and then the interpolated values are Optimize the number of bits using The bit allocation circuit I shown in FIG.
). The conversion coefficients obtained by the linear conversion circuit 3 of FIG. 5 are supplied to the intermittent circuit 42 via the input terminal 41 of FIG. 6(a). The thinning circuit 42 squares each of the N conversion coefficients, and performs thinning by 1/M using the average value of each integer value M (M is a divisor of N) as a representative value. The obtained L=N/H sample values are each quantized by a quantizer 43 and supplied to an output terminal 44 and an inverse quantizer 45. The quantizer 43 and inverse quantizer 45 may be omitted in some cases. In the interpolation circuit 46, after taking the base-2 logarithm, M times linear interpolation is performed in the logarithm domain. Using the interpolated signal, the quantizer 4 in FIG.
The bit allocation in is performed by the bit number optimization circuit 47 according to the following equation.

Here, R8 is the first conversion coefficient (i=1.2...
. The result is transmitted to the output terminal 48 and fed to the quantizer 4. IEE Transactions on AnisSP (IEE Transactions on ANISP) has shown that the squared quantization error can be minimized by allocating bits using equation (1).
IBEE TRANSACTIONS ON AS
SP) Vol. 25, No. 4, 1977, pages 299-309; (hereinafter referred to as "Reference 3"). The thinned signal obtained at the output terminal 44 is sent to the transmission line 8 as auxiliary information via the multiplexing circuit 5 shown in FIG. On the other hand, the bit allocation circuit 11 shown in FIG. 5 is configured as shown in FIG. 6(b). The signal from the separation circuit 9 of FIG. 5 is supplied to the interpolation circuit 46 via an input terminal 49. The bit allocation circuit θ in the encoder includes a quantizer 43 and an inverse quantizer 45
, the bit allocation circuit 11 in the decoder also has a corresponding inverse quantizer 45. The interpolation circuit 46 and the bit number optimization circuit 47 perform the same interpolation and bit number optimization as the interpolation circuit 46 and the bit number optimization circuit 47 in the encoder described above.

Therefore, signals for completely equal bit allocation are obtained at the output terminal 48 in FIG. 6(a) and the output terminal 50 in FIG. 6(b), and corresponding signals are obtained on the encoder side and the decoder side. quantization/inverse quantization is performed.

In the explanation so far, the signal supplied from the bit allocation circuit 6 to the multiplexing circuit 5 as auxiliary information is the square value of the thinned-out transform coefficient obtained at the output terminal 44 in FIG. 6(a). However, the purpose of transmitting this signal to the decoder is to share approximate values of transform coefficients used for bit allocation between the encoder and the decoder. As methods for transmitting auxiliary information for this purpose, methods using PARCOR coefficients, ADPCM, vector quantization, and the like are known in addition to the square value of thinned-out transform coefficients.

In the encoder, the input signal can also be normalized in order to obtain transform coefficients whose amplitude does not depend on the power of the input signal at the output of the linear transform circuit 3 shown in FIG. In this case, as shown in FIG. 7, the input signal is normalized through the normalization circuit 2 and then supplied to the linear conversion circuit 3. In the decoder, the output of the linear inverse transform circuit 12 is subjected to processing opposite to that of the normalization circuit 2 in the inverse normalization circuit 13, and then sent to the output terminal 1.
4. The reference value used for normalization is the multiplexing circuit 5
The signal is multiplexed with the signals from the quantizer 4 and the bit allocation circuit 6, and is transmitted to the decoder via the transmission path 8.

On the decoder side, the signal is separated from the signal supplied to the dequantizer 10 and bit allocation circuit 11 by the separation circuit 9, and then transmitted to the denormalization circuit 13. Figure 8(a),(b)
2 shows the configurations of the normalization circuit 2 and the denormalization circuit 13, respectively. An input signal sample is supplied from the input terminal 1 of FIG. 7 to the input terminal 61 of FIG. 8(a).

After the input signal samples are temporarily stored in buffer 62,
The N samples are collectively scaled by a multiplier 63 and supplied to an output terminal 65. The output signal from the output terminal 65 is supplied to the linear conversion circuit 3 shown in FIG. The multiplier of the multiplier 63 is the reciprocal of the average value of the input sample power for one block. This value is the reciprocal of the variance for an input signal with an average of zero, and can be calculated from the variance value determined by the variance calculation circuit 64. The variance value determined by the variance calculation circuit 64 is used by the multiplier 63 to normalize the input sample, and at the same time is supplied to the multiplexing circuit 5 in FIG. 7 via the output terminal 66, and after multiplexing, It is conveyed to the decoder as auxiliary information. On the other hand, in the inverse normalization circuit of FIG. 8(b), the signal from the linear inverse transform circuit 12 of FIG. 7 is supplied to the multiplier 68 via the input terminal 67. The multiplier 68 denormalizes the output signal using the variance value obtained through the input terminal 69 and sends it to the buffer 70.
Accumulate in. The dispersion value obtained at the input terminal 69 is transmitted from the encoder via the multiplexing circuit 5, transmission line 8, and separation circuit 9 shown in FIG. Buffer 70 sequentially sends N decoded sample values to output terminal 1 of FIG. 7 via output terminal 71.
4.

(Problem to be Solved by the Invention) In transform coding, each block is coded completely independently of its adjacent blocks, so if adjacent samples belong to different blocks, they will be affected by each other's deterioration when decoded. There is no correlation. Therefore, block distortion occurs due to waveform discontinuity between these adjacent samples, that is, between adjacent blocks, and is perceived as noise or quality deterioration.

An object of the present invention is to provide a transform decoding method and transform decoder that can reduce the effects of such block distortion.

(Means for Solving the Problems) The present invention provides a method for converting and decoding a signal that has been converted and encoded in order to compress and transmit/storage the information amount of a signal such as voice/music. It is characterized in that the signal processed by the filter is processed by a filter, and the signal processed by the filter is selected near the block boundary, and the converted and decoded signal is selected and output in the center of the block.

The present invention also provides a transform decoder, a filter that processes a signal received from the transform decoder, and a transform decoder that processes the output of the filter and the transform decoder in the vicinity of a block boundary using the signal received from the transform decoder. The present invention is characterized in that it includes at least a selector that selects and outputs the filter output, and the output of the transform decoder in the central part of the block.

(Operation) The transform decoding method and transform decoder of the present invention process the transform decoded signal with a filter, and the transform decoded signal is processed in the vicinity of the block boundary, and the transform decoded signal is used in the center of the block. By selecting and decoding output, the waveform can be smoothed and the influence of block distortion can be reduced.

(Example) Next, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention. The transform encoded signal supplied to the input terminal 20 is transmitted to the transform decoder 2.
1 and decoded. The conversion decoder 21 includes the decoder portion shown in FIG. 5 or 7 described in the conventional example, that is, the separation circuit 9, the inverse quantizer 10, and the bit allocation circuit 11.
, a linear inverse transform circuit 12, an inverse normalization circuit 13, and other general decoders can be used.

The decoded signal is supplied to filter 22 and delay element 27.

The filter 22 performs a filter operation on the input signal to reduce block distortion, and then sends the output signal to the selector 24.
supply to. The delay element 27 delays the signal supplied from the conversion decoder 21 by MT seconds (M is a positive integer), and
Supply to 4. The selector 24 selects the output signal of the filter 22, which has been subjected to block distortion countermeasures near the block boundary.
At other times, the converted decoded signal supplied from the converted decoder 21 via the delay element 27 is selected and transmitted to the output terminal 25. The selection operation of the selector 24 is performed by the conversion decoder 21
This is done using information about the boundaries provided by the processor.

FIG. 2 shows the decoded signal waveform in the fourth block (-1, ni, ni-) to explain the operation of the selector 24 in FIG. 1. In Figure 2, a, b.

C is -1 and +1 respectively. ni+1 and ni+2
Represents the block boundary between the blocks. Also,
A, B, and C represent portions of a, b, and c other than the block boundaries. In other words, the kth block is 1/2 of a, B, and b.
From 1/2 of b, the k+1+1st lock is 1/2 of b and C
and 1/2 of C.

The selector 24 in FIG. 1 outputs the output of the conversion decoder 21 delayed by the delay element 27 in A, , B, and C to a.

In b and c, the output of the filter 22 is selected and used as the output.

Filter 22 has low-pass characteristics to smooth the signal at block boundaries and reduce the perception of blockiness. However, which low-pass characteristics are most effective depends on the characteristics of the target signal. In the present invention, the filter 22 can also be configured to automatically change its characteristics depending on the input signal. Figure 3 shows filter 2 for this purpose.
2 is another embodiment of the present invention in which the filter 2 is replaced with an adaptive filter 26. The difference between FIG. 1 and FIG. 3 is that the filter 22 becomes an adaptive filter 26, and the subtracter 23 for finding the difference between the output of the transform decoder 21 and the output of the adaptive filter 26 and feeding it back to the adaptive filter 26 is used. It is something that has been added. The adaptive filter 26 is configured such that its output is equal to the output of the transform decoder 21 delayed by MTT seconds, i.e. the subtractor 23
The adaptive operation is performed so that the output of becomes zero. For adaptive filters, see Adaptive Filter Theory, Adaptive FilterThe
ory), Prentice Hall Co.
ice-Hall), 1986), and includes FIR type, IIR type, lattice type, etc. Furthermore, adaptive algorithms for adaptive filters include LMS, least square error (LS), and the like. Hereinafter, the operation of the adaptive filter 26 will be explained in detail using FIG. 4, taking the LMS algorithm as an example of an FIR filter.

FIG. 4 shows a block diagram of the adaptive filter 26 of FIG. 3. The output signal 36 of the conversion decoder 21 and the output signal 39 of the subtracter 23 in FIG. 3 are input to this filter, and an output signal 37 to the selector 24 is output.

delay elements 304, 302 each providing a delay of T seconds;
..., 3ONs are connected in this order, and each can be realized by a flip-flop. here,
The number of taps N is a positive integer, and the data period of the signal 36 is T seconds. Input signal 36 and delay element 30 ((i4, 2.
..., N) are output from multipliers 31o and 31, respectively.
1. Multiplier 31J (j.o, 1.2.
. . ., N), each coefficient, which is the output of the delay element 34J, is multiplied by the input signal, and then all the multiplication results are input to the adder 35 and added. Adder 35
The output signal 37 is supplied to the selector 24 as the output of the adaptive filter 26 in FIG. On the other hand, the signal 39 is multiplied by 2α (α is a positive constant) in the multiplier 38, and then multiplied by the multiplier 32j
is supplied to Multipliers 32o, 32. , respectively, the signal 36 or the delay element 30 . The signal supplied from the multiplier 38 is multiplied by the output of the multiplier 38, and the result is supplied to the adder 33j. Adder 33. Now, multiplier 32. The signal transmitted from the delay element 34J and the output signal of the delay element 34J are added and supplied to the delay element 34J. Delay element 34. The output of is supplied to the multiplier 31j as an output signal representing the coefficient,
3. will be returned to. The above operation can be expressed by the following equation.

cLll,,=cL+2α・eL−XL・・・・・・・
...(2) However, C5 is the coefficient vector of the adaptive filter 26 at time LT and the delay element 34J in FIG.
(j=0.l, 2.....,N) output, eL
is the output of the subtracter 23 at time LT, xL is the time
The input signal vector at T and signal 36 of FIG. 4 and delay element 30. (i・1,2...

This is the output of N). In order to stabilize the operation of the adaptive filter and shorten the convergence time, XL in equation (2) may be normalized by the power of XL and used. This is known as the NLMS algorithm, and the following formula % Formula % (3) 1.1 is an absolute value operator.

Although the operation of the filter is causal, there is a delay of MT seconds in the path from the transform decoder 2117- to the selector 24, so the adaptive filter 26 isometrically
This means that the current signal is estimated using the signal obtained in the past few seconds. That is, the output of the subtractor 23 becomes the estimation error of the adaptive filter 26. At this time, the coefficient for the output of the delay element 30M (1≦M≦N) in FIG. there's a possibility that. When the coefficients of the adaptive filter become stable in this state, the adaptive filter 26 no longer performs any filter processing. Therefore, this coefficient is forcibly set to zero.

This means that multiplier 31. , 32M, adder 331. ,
, delay element 34. , and the signal line connecting the multiplier 31□ and the adder 35 can also be realized by deleting from the configuration of FIG. 4. In the embodiment of FIGS. 1 and 2, the delay element 27 can also be omitted. In this case M=O
Thus, the filter 22 and the adaptive filter 26 operate as a predictor that predicts the current signal using past signals.

8- Referring to FIG. 2 again, in sections A, B, and C, the decoded signal is output without passing through the adaptive filter, and in sections a, b, and c, it is output after being processed by the adaptive filter. That is,
The output of the transform decoder 21, which should serve as a reference signal for updating coefficients, is a desirable output in which the decoded signal does not suffer from block distortion in sections A, B, and C, but suffers from block distortion in sections a, b, and c. , which is not a desirable signal. Therefore, interval a
.

In cases b and c, correct estimation errors are not supplied from the subtracter 23 to the adaptive filter 26. Therefore, in the present invention, the section A,
In B and C, adaptive operation of the adaptive filter is performed, and the sections a,
It is also possible to stop the adaptive operation in b and c and configure the adaptive filter 26 to perform more accurate estimation. This corresponds to multiplier 38 to multiplier 32 . This can be easily realized by providing a switch on the path leading to the multiplier 32j and forcibly setting the signal supplied to the multiplier 32j to zero in sections a, b, and c.

(Effects of the Invention) As described in detail above, according to the present invention, by selectively processing the decoded signal at the block boundary with a filter, noise generated due to waveform discontinuity between adjacent blocks can be reduced. It is possible to provide a transform decoding method and a transform decoder that can reduce the influence of block distortion that causes quality deterioration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a block diagram showing the operation of the selector 24 shown in FIG.
FIG. 3 is a block diagram showing another embodiment of the present invention, FIG. 4 is a diagram showing details of the configuration of an adaptive filter, and FIG. 5 is a diagram showing a conventional filter. A block diagram showing an example, FIGS. 6(a) and 6(b) are diagrams showing details of the bit allocation circuit ■ and bit allocation circuit ■ in FIG. 5, FIG. 7 is a diagram showing another conventional example, and FIG. figure(
7a) and 7(b) are diagrams showing details of the normalization circuit and the denormalization circuit in FIG. 7; In the figure, 20 is an input terminal, 21 is a conversion decoder, and 22
24 is a filter, 24 is a selector, 25 is an output terminal, 26 is an adaptive filter, and 27 is a delay element.

Claims (8)

[Claims] (1) When decoding a transform-encoded signal to compress and transmit/storage the amount of information in a signal such as voice/music, the transform-decoded signal is processed with a filter, and the A method of transform decoding, characterized in that the signal processed by the filter is selected and the transform decoded signal is decoded and output in the central part of the block. (2) The transform decoding method according to claim 1, wherein the block central portion selects and outputs a signal obtained by delaying the transform decoded signal. (3) The coefficient corresponding to the input sample at the current time of the filter is zero, and the other coefficients are adaptively updated according to the difference between the output of the filter and the output of the transform decoder. The conversion decoding method according to claim 1 or 2. (4) The transform decoding method according to claim 3, wherein the filter stops updating coefficients near a block boundary in transform decoding. (5) Processing a transform decoder and the signal received from the transform decoder when decoding a transform encoded signal to compress and transmit/storage the information amount of a signal such as voice/music. a filter, and the output of the filter and the output of the transform decoder are selected and output using a signal received from the transform decoder near the block boundary and the output of the transform decoder in the center of the block. A transform decoder comprising at least a selector that performs the following steps. (6) The transform decoder according to claim 5, further comprising a delay element in the center of the block for delaying the output of the transform decoder and then supplying the output to the selector. (7) The filter includes a coefficient whose value is zero corresponding to the input sample at the current time, and other coefficients that are adaptively updated according to the difference between the output of the filter and the output of the transform decoder. The transform decoder according to claim 5 or 6, characterized in that: (8) The transform decoder according to claim 7, wherein the filter includes a switch for stopping coefficient updating near a block boundary in transform decoding.