JPH0315023A - Liquid crystal driving circuit - Google Patents
Liquid crystal driving circuitInfo
- Publication number
- JPH0315023A JPH0315023A JP15095789A JP15095789A JPH0315023A JP H0315023 A JPH0315023 A JP H0315023A JP 15095789 A JP15095789 A JP 15095789A JP 15095789 A JP15095789 A JP 15095789A JP H0315023 A JPH0315023 A JP H0315023A
- Authority
- JP
- Japan
- Prior art keywords
- output
- signal
- segment
- liquid crystal
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 11
- 239000000758 substrate Substances 0.000 abstract description 7
- 230000006866 deterioration Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 7
- 239000013078 crystal Substances 0.000 description 2
- 230000002542 deteriorative effect Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3681—Details of drivers for scan electrodes suitable for passive matrices only
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3685—Details of drivers for data electrodes
- G09G3/3692—Details of drivers for data electrodes suitable for passive matrices only
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Liquid Crystal Display Device Control (AREA)
- Liquid Crystal (AREA)
Abstract
Description
【発明の詳細な説明】
〈産業上の利用分野〉
本発明は、MOS}ランジスタによって構成される液晶
駆動回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a liquid crystal drive circuit constituted by MOS transistors.
〈従来の技術〉
肢晶駆動回路は、第3図に示すように液晶表示装置1に
セグメント出力信号i1,...,1n を出力するセ
グメント信号出力回路2と、バノクプレート出力信号H
l.・・・.Hmを出力するバンクプレート信号出力回
路3とから収る。<Prior Art> As shown in FIG. 3, a limb crystal drive circuit sends segment output signals i1, . .. .. , 1n, and a banok plate output signal H.
l.・・・. The bank plate signal output circuit 3 outputs Hm.
従来のセグメント及びバノクプレート出力信号は第4図
に示すようなものであり、これらの信号を出力するため
の回路として第5図に示すような構成をとっている。第
5図fatはセグメント信号出力回路,第5図(blは
バノクプレート信号出カ着路である。Conventional segment and banok plate output signals are as shown in FIG. 4, and a circuit for outputting these signals has a configuration as shown in FIG. 5. In FIG. 5, fat is a segment signal output circuit, and FIG. 5 (bl is a banok plate signal output route.
このセグメント信号出力回路のVA.VBl”ll..
フレーム1(S=H)で(dVA =AA1 . vn
=VBB,7L/−ム2(S=L)TUVA=AAz
.Vn =vD2となるように制御される。各デュー
ティにて、信号lぎHで,フレーム1の時にトランジス
タPa,Nbがオンして− VAI レベルを出力し
、フレーム2の時にトランジスタPb1Naがオンして
− Vlll レベルを出力し,液晶表示点灯、信号
i=Lで,フレーム1の時にトランジスタPb,Naが
オンして−Vlll レベルを出力し、フレーム2の
時にトランジスタPa,NbがオンしてVA2 レベル
全出力し、非点灯となる。VA of this segment signal output circuit. VBl”ll..
At frame 1 (S=H) (dVA=AA1.vn
=VBB,7L/-mu2(S=L)TUVA=AAz
.. It is controlled so that Vn = vD2. At each duty, when the signal is l to H, transistors Pa and Nb turn on in frame 1 and output -VAI level, and in frame 2, transistor Pb1Na turns on and outputs -Vllll level, and the liquid crystal display lights up. , when the signal i=L, the transistors Pb and Na turn on in frame 1 and output the -Vllll level, and in the frame 2, the transistors Pa and Nb turn on and output the full VA2 level, turning off the light.
このセグメント信号出力回路にて,トランジスタPa.
Nb及びPb.Naが抱合せになっている。通常の出力
バノフrPa.Naのみでは、フレームlの時にNaが
オンしてVII1 レベルを出?する時と、フレーム
2の時にPaがオンしてVA2 レベルを出力する時
に、Na,Paのトランジスタにパノクゲートバイアス
がかかり(Naの基板電位VB2 に対してNaのソー
ス電位がVBI と高〈なる、筐たPaの基板電位VA
I と対してPaのソース電位がV人2と低くなるため
),トランジスタのオン抵抗が大きくなり、負荷である
夜晶を駆動しきらず,フレーム1の時にVAIレベルか
らVB レベル、フレーム2の時にVB■l
レベルからV人2 レベルへの出力信号波形がなまり、
表示品位が悪化してしまうC第6図参照)。In this segment signal output circuit, transistor Pa.
Nb and Pb. Na is conjugated. Normal output Banoff rPa. With only Na, does Na turn on at frame l and the VII1 level is output? When Pa is turned on in frame 2 and outputs the VA2 level, a panoch gate bias is applied to the transistors Na and Pa (the source potential of Na is as high as VBI with respect to the substrate potential VB2 of Na). The substrate potential VA of Pa
Since the source potential of Pa becomes low (V2 compared to I), the on-resistance of the transistor becomes large, and the night crystal, which is the load, cannot be driven completely, and the voltage changes from VAI level to VB level in frame 1 and to VB level in frame 2. The output signal waveform from VB ■l level to V person 2 level becomes dull,
The display quality deteriorates (see Figure 6).
このバノクゲートバイアスによるオン抵抗の悪化を補償
するために、Pb,Nbの2つのトランジスタを付加し
,トランジスタゲートとして,いかなる場合にも小さい
オン抵抗でレベルを出力できるようにし,出力信号波形
のな1り金防ぎ、表示品位を良好に保−ている。In order to compensate for the deterioration of the on-resistance due to this Banok gate bias, two transistors, Pb and Nb, are added, and as transistor gates, the level can be output with a small on-resistance in any case, and the output signal waveform is This prevents unnecessary charges and maintains good display quality.
〈発明が解決しようとする課題〉
従来の方法では、セグメント信号出力回路の出カバノフ
ァ部に4つのトランジスタが必要であり非常に大きな面
積を必要としていた。<Problems to be Solved by the Invention> In the conventional method, four transistors were required in the output buffer section of the segment signal output circuit, which required a very large area.
本発明は、表示品位を悪化させることなく、通常の出力
ハノファと同様に2つのトランジスタにてセグメント信
号出力回路の出力バノファ部を構成できる方法を提供す
ることを目的としている。SUMMARY OF THE INVENTION An object of the present invention is to provide a method in which the output vanofer section of a segment signal output circuit can be configured with two transistors in the same way as a normal output vanofa, without deteriorating the display quality.
く課題を解決するための手段〉
本発明の液晶駆動回路は、セグメント出力信号とパノク
プレート出力信号の各出力回路を持ち、その出力信号の
各デューティの初期に短いディスチャージ期間を持たせ
る構成としたことを特徴とするものである。Means for Solving the Problems> The liquid crystal drive circuit of the present invention has each output circuit for a segment output signal and a panoch plate output signal, and is configured to have a short discharge period at the beginning of each duty of the output signal. It is characterized by:
〈実施例〉 以下,実施例に基づいて本発明を詳細に説明する。<Example> Hereinafter, the present invention will be explained in detail based on examples.
本発明に係るセグメント及びバノクプレート信号出力回
路を第1図(al及び(blに示す。この回路はP基院
,NウエルのCMOSプロセスにて考察したものである
。基本的にトランジスタPaの基板電位(正確にはNウ
ェルの電位)をPaのソース電位と同じVAに固定し、
1た、信号Tによってセグメント及びバノクプレート出
力信号の各デ二ーテイの初期に短いデイスチャージ期間
を持つような構成としている。The segment and banok plate signal output circuit according to the present invention is shown in FIG. (To be exact, the potential of the N well) is fixed at VA, which is the same as the source potential of Pa,
Furthermore, the structure is such that the signal T provides a short discharge period at the beginning of each digital of the segment and banok plate output signals.
本回路による出力信号を第2図に示す。Figure 2 shows the output signal from this circuit.
セグメント信号出力回路のトランジスタPaのバノクゲ
ートバイアス対策として.Paの基板電位C正確にぱN
ウェルの電位)をPaのソースと同電位にv人に固定し
てある。内部のOジノクとは分離してPaのみを単独の
ウエルにて構成すればウェルの電位をVAにすることが
可能であり、V人がVAI . VA2 と変化しても
基板(ウエル)とンースが同電位となるのでバノクゲー
トバイアスがかからない構戊とすることができる。しか
し、トランジスタNaの基板電位iVn2 レベルに固
定であるため、Paのように、基板(Nウェル)とソー
スの電位を同一にすることができず,バ・ノクゲートバ
イアスを防ぐことができない。そこで回路構底を第1図
のようにし、信号Tによって、セグメント及びバノクプ
レート出力信号の各デューティの初期に短いデイスチセ
ージ期間を持たせる。つまり,第2図に示すセグメント
及びバノクプレート信号を出力するようにする。このよ
うな信号が出力されれば、V人1 レベル出力時ニ,液
晶にチャージアノブされた電荷は、ディスチャージ期間
に,バノクゲートバイアスのかからない状a(T=Hの
時に、■n=VB2であるため)で小さいオン抵抗のN
aにて短時間にディスチャージされ、その後vn=Vn
+ となり、NaによーてVB1 レベルが出力さ
れる。このため、バノクゲートバイアスのかかった状態
での大きなオン抵抗であるNaにて負荷である液晶を駆
動する必要がなくなり,波形がな1ることぱ無く,表示
品位も良好となる。As a countermeasure for banok gate bias of transistor Pa of segment signal output circuit. Pa's substrate potential C is exactly PaN
The well potential) is fixed to the same potential as the source of Pa. By configuring only Pa in a single well, separated from the internal Ojinoku, it is possible to set the well potential to VA. Even if VA2 changes, the substrate (well) and the well have the same potential, so a structure can be created in which no banok gate bias is applied. However, since the substrate potential of the transistor Na is fixed at the iVn2 level, unlike Pa, the potentials of the substrate (N well) and the source cannot be made the same, and it is not possible to prevent the gate bias. Therefore, the circuit structure is made as shown in FIG. 1, and the signal T is used to provide a short destination period at the beginning of each duty of the segment and banok plate output signals. That is, the segment and banok plate signals shown in FIG. 2 are output. If such a signal is output, the charge annoborated to the liquid crystal at the time of V person 1 level output will be in the state a (when T = H, n = VB2) during the discharge period, where no banok gate bias is applied. ) with small on-resistance N
It is discharged for a short time at a, and then vn=Vn
+, and the VB1 level is output by Na. Therefore, there is no need to drive the liquid crystal as a load with Na, which has a large on-resistance when a banok gate bias is applied, and the waveform never drops, resulting in good display quality.
く発明の効果〉
以上述べてきたように,本発明によれば、表示品位を悪
化させることなく、セグメント信号出力回路の出力バノ
ファ部を2つのトランジスタで構成することができ、よ
り小さな面積にて液晶駆動回路を構成でき、実用的には
極めて有効である。Effects of the Invention> As described above, according to the present invention, the output vanofer section of the segment signal output circuit can be configured with two transistors without deteriorating the display quality, and the output can be configured with a smaller area. It is possible to configure a liquid crystal drive circuit, and is extremely effective in practice.
?1図は木発明に係るセグメント信号出力回路及びバノ
クプレート信号出力回路の回路図,第2図は本発明に係
るセグメント出力信号及びバノクプレート出力信号の波
形図、第3図は液晶表示システムのブロノク図,第4図
は従来のセグメント出力信号及びバノクプレート出力信
号の波形図、第5図は従来のセグメント信号出力回路及
びバノクプレート信号出力回路の回路図、第6図idP
a,Naのみの詩のセグメ■ント出力信号波形図である
。? 1 is a circuit diagram of a segment signal output circuit and a banok plate signal output circuit according to the invention, FIG. 2 is a waveform diagram of a segment output signal and a banok plate output signal according to the invention, and FIG. 3 is a bronc diagram of a liquid crystal display system. Fig. 4 is a waveform diagram of a conventional segment output signal and banok plate output signal, Fig. 5 is a circuit diagram of a conventional segment signal output circuit and banok plate signal output circuit, and Fig. 6 is a waveform diagram of a conventional segment output signal and banok plate signal output circuit.
FIG. 6 is a segment output signal waveform diagram of a poem with only a and Na.
Claims (1)
出力回路を持ち、その出力信号の各デューティの初期に
短いディスチャージ期間を持たせる構成としたことを特
徴とする液晶駆動回路。1. A liquid crystal drive circuit characterized in that it has an output circuit for a segment output signal and a back plate output signal, and is configured to have a short discharge period at the beginning of each duty of the output signal.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1150957A JP2502152B2 (en) | 1989-06-13 | 1989-06-13 | LCD drive circuit |
DE19904018805 DE4018805A1 (en) | 1989-06-13 | 1990-06-12 | Drive circuit for LCD - has segment and rear plate drive circuits and discharges cells shortly before changes in corresp. data signal levels |
US07/839,703 US5220313A (en) | 1989-06-13 | 1992-02-24 | Device for driving a liquid crystal display device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1150957A JP2502152B2 (en) | 1989-06-13 | 1989-06-13 | LCD drive circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0315023A true JPH0315023A (en) | 1991-01-23 |
JP2502152B2 JP2502152B2 (en) | 1996-05-29 |
Family
ID=15508129
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1150957A Expired - Fee Related JP2502152B2 (en) | 1989-06-13 | 1989-06-13 | LCD drive circuit |
Country Status (2)
Country | Link |
---|---|
JP (1) | JP2502152B2 (en) |
DE (1) | DE4018805A1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07160216A (en) * | 1993-12-07 | 1995-06-23 | Komatsu Ltd | Transmission type liquid crystal mask marker and method of driving liquid crystal mask |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS509395A (en) * | 1973-05-23 | 1975-01-30 | ||
JPS5474330A (en) * | 1977-11-25 | 1979-06-14 | Sanyo Electric Co Ltd | Dynamic driving method for liquid crystal |
JPH026921A (en) * | 1988-06-25 | 1990-01-11 | Fujitsu Ltd | Method for driving liquid crystal display device |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6059389A (en) * | 1983-09-12 | 1985-04-05 | シャープ株式会社 | Circuit for driving liquid crystal display unit |
-
1989
- 1989-06-13 JP JP1150957A patent/JP2502152B2/en not_active Expired - Fee Related
-
1990
- 1990-06-12 DE DE19904018805 patent/DE4018805A1/en active Granted
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS509395A (en) * | 1973-05-23 | 1975-01-30 | ||
JPS5474330A (en) * | 1977-11-25 | 1979-06-14 | Sanyo Electric Co Ltd | Dynamic driving method for liquid crystal |
JPH026921A (en) * | 1988-06-25 | 1990-01-11 | Fujitsu Ltd | Method for driving liquid crystal display device |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07160216A (en) * | 1993-12-07 | 1995-06-23 | Komatsu Ltd | Transmission type liquid crystal mask marker and method of driving liquid crystal mask |
Also Published As
Publication number | Publication date |
---|---|
DE4018805C2 (en) | 1992-09-10 |
JP2502152B2 (en) | 1996-05-29 |
DE4018805A1 (en) | 1990-12-20 |
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