JPH03149919A - Frequency multiplying circuit - Google Patents

Abstract

PURPOSE:To simplify the capacitance by using an internal reference signal to measure the period of an input signal, and outputting a signal having an equal period to that of a desired frequency signal based on a multiple set externally and on the measured period of the input signal. CONSTITUTION:A periodic signal is inputted to an input terminal 1, a differentiating circuit 2 differentiates the input signal and a signal forming circuit 3 forms a signal starting the measurement of a period measuring counter 5. The period measuring counter 5 measures the period of an input signal based on the reference clock of an oscillator 4. Then the output of the period measuring counter 5 is read in a latch circuit 6 in a timing next to the time of the differentiating signal obtained from the input signal. A frequency division ratio setting circuit 7 decides the frequency division ratio of a variable frequency division circuit 9 based on a magnification of frequency set at an external setting terminal 8, applies variable frequency division and outputs the result to an output terminal 10. Thus, the multiple circuit is constituted of only a digital circuit, and the consideration of the variable in the circuit component or the like is not required.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a frequency multiplication method κ.

[Prior Art] There is a conventional frequency multiplier circuit called P,LL (7,z-locked loop).

[Problem to be Solved by the Invention] However, the above-mentioned conventional technology could not be constructed using digital technology alone. That is, the phase difference between the input signal and the reference signal is detected, the phase difference is converted into a voltage value, and the WOO (voltage variable oscillator) is controlled to obtain the required frequency signal.

As a result, it was necessary to design circuits using a mixture of analog and digital technologies, which caused major problems when converting to KIa.

Therefore, the present invention solves such problems.
The purpose of this is to provide a multiplier circuit that can be constructed using only digital technology and has an innovative construction.

[Measures A2 for Solving the Problems] The frequency transmitting circuit of the present invention includes a differentiating circuit that differentiates a periodic human input signal, a signal forming circuit that forms a signal from the output signal of the differentiating circuit, and a signal forming circuit that performs measurement using the output of the signal forming circuit. A period measurement force counter that starts the period measurement force counter, a latch circuit that takes in the output of the period measurement force counter at the timing of the signal forming circuit output, a frequency division ratio setting circuit that determines the division ratio from the latch circuit output data and external setting data, and a frequency division circuit. According to the above structure of the present invention, the period of the input signal is determined by using the internal reference signal. The variable frequency dividing circuit operates to output a signal equivalent to the period of the desired frequency signal from the externally set magnification and the period of the measured input signal.

[Embodiment] FIG. 1 is a block circuit diagram in an embodiment of the present invention. Reference numeral 1 denotes an input terminal for inputting an input signal, into which a periodic signal is input. (FIG. 2(α)) The input signal is differentiated by the differentiating circuit 2 (FIG. 2(b)), and the signal forming circuit 5 forms a signal that causes the period measuring force counter 5 to start measurement. The period measuring unit 5 measures the period of the input signal (difference B between the second differential signals) based on the reference clock of the oscillator 40. Then, at the next timing of the differential signal of the input signal (at the end of the differential signal period B shown in Figure 2), the output of the period measuring force counter 5 is read into the latch circuit 6, and the frequency multiplier set at the external setting terminal 8 is set. Basically, the frequency division ratio setting circuit 7 determines the frequency division ratio of the variable frequency division circuit 9, performs variable frequency division, and outputs the result to the output terminal 10. (FIG. 2(C)) For example, if the period of the input signal is T, the setting magnification of the external setting terminal is ■, and the reference clock of the oscillator 40 is f, then the output path of the period measuring force counter 5 has a period of =87. It is expressed as

If the magnification is N, then it is sufficient to output a frequency signal with a period of /N-/M.

In other words, the output frequency is /T-/, . . . If the variable frequency divider circuit is set at a division ratio of 4, a signal with a frequency twice as high as the input signal will be output.

[Effects of the Invention] As described above, according to the configuration of the present invention, it is possible to configure the IC using only digital circuits, which makes it extremely easy to manufacture ICt, and as a result, it becomes an inexpensive IC. I can do things. In other words, in terms of performance, since it is performed only by digital processing, it is not affected by the characteristics of the circuit, so there is no need to take into account variations in circuit elements, making design very easy. Since there is no decrease in yield due to this, manufacturing is very easy and inexpensive6. Moreover, since it can be realized with a simple circuit configuration rather than a mixed analog/digital circuit, it can be realized with a high integration density and a zero manufacturing process, and the chip size can be reduced, making it possible to realize an even cheaper manufacturing process. Furthermore, the circuit configuration has the advantage that it is very easy to design and can be configured with conventionally used frequency divider circuits, counters, etc.

Explanation of the opening of the eastern part of the world FIG. 1 is a block circuit diagram of a multiplier circuit according to the present invention.

The taz diagram is the timing chart of Figure 1.

1...--Input terminal 2--Differentiating circuit 5--Signal forming circuit 4--1 Oscillator 5・−・・・・・・Period measurement force counter 6−−−−−
--- Latch circuit 7 --- Frequency division ratio setting circuit 8 --- External setting terminal 9 --- One-time variation frequency dividing circuit 1o −−・・−・−・Output terminal or more 1 applicant Seiko Epson Co., Ltd. agent Patent attorney Kizobe Suzuki (and 1 other person) Figure 1

Claims (1)

[Claims] (1) A differentiation circuit that differentiates a periodic input signal, a signal formation circuit that forms a signal from the output signal of the differentiation circuit, a period measurement counter that starts measurement based on the output of the signal formation circuit, and a signal formation that uses the output of the period measurement counter. A latch circuit that captures data at the timing of circuit output, a frequency division ratio setting circuit that determines the division ratio from the latch circuit output data and external setting data, and a variable frequency division circuit that determines the division ratio based on the division ratio setting circuit output. A frequency multiplier circuit comprising: