JPH0314821Y2 - - Google Patents
Info
- Publication number
- JPH0314821Y2 JPH0314821Y2 JP3296682U JP3296682U JPH0314821Y2 JP H0314821 Y2 JPH0314821 Y2 JP H0314821Y2 JP 3296682 U JP3296682 U JP 3296682U JP 3296682 U JP3296682 U JP 3296682U JP H0314821 Y2 JPH0314821 Y2 JP H0314821Y2
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- circuit
- load
- amplifier
- current
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000001514 detection method Methods 0.000 claims description 13
- 238000010586 diagram Methods 0.000 description 7
- 230000010355 oscillation Effects 0.000 description 3
- 238000013459 approach Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000000087 stabilizing effect Effects 0.000 description 1
Landscapes
- Control Of Amplification And Gain Control (AREA)
Description
【考案の詳細な説明】
本考案は負荷回路に所望の電圧または電流を供
給する回路に係り、特にその回路の安定化回路に
関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit for supplying a desired voltage or current to a load circuit, and particularly to a stabilizing circuit for the circuit.
第1図は従来の電圧・電流制御回路のブロツク
図である。3は電力増幅器であり、入力端子1に
印加された入力信号を増幅し、その出力信号を電
流検出抵抗器5(抵抗値RI)を介して負荷回路
7に供給する。負荷回路7に流れる電流は抵抗器
5と増幅器11により検出され、増幅器3の入力
側に帰還される。そして電流制御を行う場合には
負荷回路7に流れる電流が所望値になるように制
御される。また負荷回路7の電圧は電圧ホロワ9
を介して増幅器3の入力側に帰還され、電圧制御
を行う場合には負荷回路7の電圧が所望値になる
ように制御される。即ち入力端子1に所望の負荷
電圧または電流を得るための信号が印加され、そ
して前述帰還動作により回路全体がこれら所望値
が得られるように動作する。電圧制御と電流制御
のどちらかを行うかは、入力端子1に印加する信
号の大きさの選択と共に、上記の増幅器11,9
のどちらの出力信号を帰還するかを選択すればよ
い。なおこの回路の詳細については本出願人が以
前に出願した特開昭58年第121812号に述べられて
いる。以上の説明より帰還制御動作は当業者にと
つて自明であると思われるが、さらに詳述すれ
ば、電力増幅器3には制御用として差動増幅器
(演算増幅器)が一般に使用されるから、電力増
幅器3の一方の入力端子に所望の負荷電圧または
負荷電流を得るための信号を印加し、他方の入力
端子側に増幅器11または9の出力信号を選択的
に切換入力すればよい。なお、本考案の要旨はか
かる帰還制御動作ではないことは勿論である。 FIG. 1 is a block diagram of a conventional voltage/current control circuit. A power amplifier 3 amplifies the input signal applied to the input terminal 1 and supplies the output signal to the load circuit 7 via the current detection resistor 5 (resistance value R I ). The current flowing through the load circuit 7 is detected by the resistor 5 and the amplifier 11 and fed back to the input side of the amplifier 3. When current control is performed, the current flowing through the load circuit 7 is controlled to a desired value. Also, the voltage of the load circuit 7 is determined by the voltage follower 9
The voltage is fed back to the input side of the amplifier 3 via the voltage control circuit 7, and when performing voltage control, the voltage of the load circuit 7 is controlled to a desired value. That is, a signal for obtaining a desired load voltage or current is applied to the input terminal 1, and the entire circuit operates to obtain these desired values through the feedback operation described above. Whether to perform voltage control or current control is determined by the selection of the magnitude of the signal applied to input terminal 1 and by the amplifiers 11 and 9 described above.
It is only necessary to select which output signal to feed back. The details of this circuit are described in Japanese Unexamined Patent Publication No. 121812 of 1982, which was previously filed by the present applicant. From the above explanation, the feedback control operation is thought to be obvious to those skilled in the art, but to explain in more detail, since a differential amplifier (operational amplifier) is generally used in the power amplifier 3 for control, A signal for obtaining a desired load voltage or load current may be applied to one input terminal of the amplifier 3, and the output signal of the amplifier 11 or 9 may be selectively inputted to the other input terminal. It goes without saying that the gist of the present invention is not such a feedback control operation.
上記回路において、電流検出抵抗器5と負荷回
路7との結合線にノイズが入らないようにするた
め、この結合線を包囲してガード13が使用され
る。そしてこのガード13は電圧ホロワ9の出力
端子と接続され、該出力端子と同電位に保持され
る。なおこのガード13は負荷回路7に微少電流
を流す場合に特に必要である。また負荷回路7に
は広範囲の可変電圧を供給すること、9は電圧ホ
ロワで動作することおよび電力消費を軽減するこ
とを考慮して、電圧ホロワ9の電源の基準電位B
は増幅器3の出力電圧を基準としている。また負
荷回路7の基準電位Aは増幅器3の電源の基準電
位を基準としている。 In the above circuit, in order to prevent noise from entering the coupling line between the current detection resistor 5 and the load circuit 7, a guard 13 is used to surround this coupling line. This guard 13 is connected to the output terminal of the voltage follower 9 and held at the same potential as the output terminal. Note that this guard 13 is especially necessary when a minute current is passed through the load circuit 7. In addition, considering that the load circuit 7 is supplied with a variable voltage over a wide range, the voltage follower 9 operates as a voltage follower, and power consumption is reduced, the reference potential B of the power supply of the voltage follower 9 is
is based on the output voltage of amplifier 3. Further, the reference potential A of the load circuit 7 is based on the reference potential of the power supply of the amplifier 3.
しかしながら従来回路は次のような欠点を有す
る。即ちガード13により生ずるガード容量15
の影響により電流制御系が不安定になり、発振を
起こしやすくなる。ガード容量値をCg、電圧ホ
ロワ9の増幅器の利得をA5、カツトオフの角周
波数をω5とすると、Ycなるアドミタンスが等価
的に電流検出抵抗器5に並列に入つたことにな
る。そしてYc=jωCg/(1+A5)=jωCg/{1
+(ω5/jω)}となり、ω<ω5の帯域ではYc≒
jωCg・(jω/ω5)=−ω2Cg/ω5となる。よつて、
RIの値により、特にRIが大のとき(微少電流の
とき)、電流検出抵抗器の全インピーダンスが負
性領域に入り発振を起す場合がある。 However, the conventional circuit has the following drawbacks. That is, the guard capacity 15 generated by the guard 13
The influence of this makes the current control system unstable, making it more likely to cause oscillation. If the guard capacitance value is Cg, the gain of the amplifier of the voltage follower 9 is A5 , and the cutoff angular frequency is ω5 , then an admittance Yc is equivalently entered in parallel with the current detection resistor 5. And Yc=jωCg/(1+A 5 )=jωCg/{1
+(ω 5 /jω)}, and in the band of ω < ω 5 , Yc≒
jωCg・(jω/ω 5 )=−ω 2 Cg/ω 5 . Afterwards,
Depending on the value of R I , especially when R I is large (minimum current), the total impedance of the current detection resistor may enter the negative region and cause oscillation.
本考案は上記欠点を除去するためになされたも
ので、第2図は本考案の一実施例を示すブロツク
図である。第1図と同一部分には同一符号を付し
て示した。第2図の回路が第1図と異なる点は、
電圧ホロワ9の出力端子と基準電位点Aとの間に
ローパスフイルタを設け、抵抗器17とコンデン
サ19との結合点とガード13とを接続したこと
である。 The present invention has been devised to eliminate the above-mentioned drawbacks, and FIG. 2 is a block diagram showing one embodiment of the present invention. The same parts as in FIG. 1 are designated by the same reference numerals. The difference between the circuit in Figure 2 and that in Figure 1 is as follows:
A low-pass filter is provided between the output terminal of the voltage follower 9 and the reference potential point A, and the guard 13 is connected to the connection point between the resistor 17 and the capacitor 19.
第3図は第2図の等価回路である。電流検出抵
抗器5と並列にアドミタンスYiが、負荷回路7
と並列にアドミタンスYXがそれぞれ挿入された
ことになる。ここでYi,YXは次式で表わされる。 FIG. 3 is an equivalent circuit of FIG. 2. An admittance Yi is connected to the load circuit 7 in parallel with the current detection resistor 5.
This means that admittance Y X is inserted in parallel with . Here, Yi and YX are expressed by the following formula.
Yi=jωCg・f(ω)/(1+A5)
Yx=jωCg(1−f(ω))
f(ω)=1/1+jωCF・RF=1/1+(jω/ω
FIL)
CFはコンデンサ19の容量値、RFは抵抗器17
の抵抗値である。 Yi=jωCg・f(ω)/(1+A 5 ) Yx=jωCg(1−f(ω)) f(ω)=1/1+jωC F・R F =1/1+(jω/ω
FIL ) C F is the capacitance value of capacitor 19, R F is resistor 17
is the resistance value of
上記式より、ω<ω5において
Yi=jωCg・〓〓/1+(ω5/jω)=jωCg・ωFI
L/ω5
よつて、Yiはもともと負性領域ではなくなり、
その結果発振する要因は除去される。From the above formula, at ω<ω 5 , Yi=jωCg・〓〓/1+(ω 5 /jω)=jωCg・ω FI
Since L /ω 5 , Yi is no longer in the negative region to begin with,
As a result, the factors that cause oscillation are removed.
なおYXが負荷回路7に並列に入ることになる
が、フイルタはローパスフイルタであるためωが
大きくなるにつれfωは零に近づき、YXはjωCgに
近づく。よつてガード容量がそのまま負荷として
見えるだけであり、影響はない。またこの容量負
荷は、抵抗器5を流れる電流が電力増幅器3の出
力電圧に対して進相となるように働くので、この
意味でも電流制御系は安定化することになる。 Note that Y X is input in parallel to the load circuit 7, and since the filter is a low-pass filter, as ω increases, fω approaches zero and Y X approaches jωCg. Therefore, the guard capacitance is simply seen as a load and has no effect. Further, this capacitive load works so that the current flowing through the resistor 5 becomes phase advanced with respect to the output voltage of the power amplifier 3, so that the current control system is stabilized in this sense as well.
第4図は本考案の他の実施例を示したブロツク
図である。第2図と異なる点は電圧ホロワ9の電
源の基準点を電力増幅器3の電源の基準点と同一
にした点である。この場合には、ガード容量13
の影響が第1図の場合と同様に負荷回路7に並列
に挿入された形で現われ、電圧制御系の安定性が
悪くなるが、ローパスフイルタを接続することに
より第2図の場合と同様に上記欠点が除外され
る。 FIG. 4 is a block diagram showing another embodiment of the present invention. The difference from FIG. 2 is that the reference point of the power source of the voltage follower 9 is made the same as the reference point of the power source of the power amplifier 3. In this case, the guard capacity is 13
As in the case of Fig. 1, the effect appears in the form of being inserted in parallel to the load circuit 7, which worsens the stability of the voltage control system, but by connecting a low-pass filter, it can be reduced as in the case of Fig. 2. The above drawbacks are excluded.
以上説明したことより明らかなように、本考案
によれば本来のガード機能を損うことなく従来の
欠点を除去しうる。 As is clear from the above explanation, according to the present invention, the drawbacks of the conventional device can be eliminated without impairing the original guard function.
第1図は従来の電圧・電流制御回路のブロツク
図、第2図は本考案の一実施例による電圧・電流
制御回路のブロツク図、第3図は第2図の一部等
価回路図、第4図は本考案の他の実施例のブロツ
ク図である。
3:電力増幅器、5:電流検出抵抗器、7:負
荷回路、9:電圧ホロワ、13:ガード、15:
ガード容量。
FIG. 1 is a block diagram of a conventional voltage/current control circuit, FIG. 2 is a block diagram of a voltage/current control circuit according to an embodiment of the present invention, and FIG. 3 is a partial equivalent circuit diagram of FIG. FIG. 4 is a block diagram of another embodiment of the present invention. 3: Power amplifier, 5: Current detection resistor, 7: Load circuit, 9: Voltage follower, 13: Guard, 15:
Guard capacity.
Claims (1)
器の出力信号を電流検出抵抗器とガードを有する
結線手段とを介して負荷回路に供給し、前記電流
検出抵抗器の両端子間電圧または負荷電圧を選択
的に前記電力増幅器の他方の入力端子側に帰還し
て負荷電流または負荷電圧を所望値に制御する回
路において、前記両端子間電圧を検出する電流検
出用増幅器と、前記負荷回路に入力側が接続され
た負荷電圧検出用増幅器と、前記負荷電圧検出用
増幅器の出力端と前記ガードとの間に接続された
ローパスフイルタと、前記電流検出用増幅器また
は前記負荷電圧検出用増幅器の出力信号を選択的
に前記電力増幅器の他方の入力端子側に帰還する
切換手段とを備えたことを特徴とする電圧・電流
制御回路。 An output signal of a power amplifier that receives an input signal at one input terminal is supplied to a load circuit via a current detection resistor and a connection means having a guard, and the voltage between both terminals of the current detection resistor or the load voltage is The circuit selectively feeds back to the other input terminal side of the power amplifier to control the load current or load voltage to a desired value, the circuit comprising: a current detection amplifier for detecting the voltage between the two terminals; and an input side connected to the load circuit. Selecting a connected load voltage detection amplifier, a low pass filter connected between an output terminal of the load voltage detection amplifier and the guard, and an output signal of the current detection amplifier or the load voltage detection amplifier. 1. A voltage/current control circuit comprising: a switching means for feeding back to the other input terminal side of the power amplifier.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3296682U JPS58138413U (en) | 1982-03-09 | 1982-03-09 | Voltage/current control circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3296682U JPS58138413U (en) | 1982-03-09 | 1982-03-09 | Voltage/current control circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS58138413U JPS58138413U (en) | 1983-09-17 |
JPH0314821Y2 true JPH0314821Y2 (en) | 1991-04-02 |
Family
ID=30044539
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3296682U Granted JPS58138413U (en) | 1982-03-09 | 1982-03-09 | Voltage/current control circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58138413U (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5559905B1 (en) * | 2013-04-24 | 2014-07-23 | 株式会社エーディーシー | Electronic circuit |
-
1982
- 1982-03-09 JP JP3296682U patent/JPS58138413U/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS58138413U (en) | 1983-09-17 |
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