JPH03148133A - Plating method for bump electrode of semiconductor device - Google Patents

Plating method for bump electrode of semiconductor device

Info

Publication number
JPH03148133A
JPH03148133A JP28603289A JP28603289A JPH03148133A JP H03148133 A JPH03148133 A JP H03148133A JP 28603289 A JP28603289 A JP 28603289A JP 28603289 A JP28603289 A JP 28603289A JP H03148133 A JPH03148133 A JP H03148133A
Authority
JP
Japan
Prior art keywords
wafer
plating
bump electrode
conductive film
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP28603289A
Other languages
Japanese (ja)
Inventor
Tadashi Igarashi
正 五十嵐
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP28603289A priority Critical patent/JPH03148133A/en
Publication of JPH03148133A publication Critical patent/JPH03148133A/en
Pending legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To prevent occurrence of an improper chip by forming a conductive film on the entire surface of a wafer, electrically conducting the film with an electrode pin on the rear surface of the wafer, and plating a bump electrode. CONSTITUTION:A conductive film 22 of aluminum, etc., is formed on the entire surface of a wafer 21 to be formed with a bump electrode by vacuum depositing, etc., the front surface of the wafer 21 is coated with a mask material 23 such as resist, and so patterned as to open only at a part to be desired to be formed with the bump electrode. Then, it is so set in a rack 25 that the rear surface of the wafer 21 is brought into contact with an electrode pin 24, an O-ring 26 is mounted at the peripheral edge to seal the space of the rear surface of the wafer 21 against the atmosphere, the wafer 21 is sucked and held by vacuum evacuating, then dipped in a plating solution 27, and plated by supplying a plating current. Thus, an improper chip is eliminated to be stably plated with the bump electrode.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、半導体装置にバンプ電極を形成する際のメッ
キ方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a plating method for forming bump electrodes on a semiconductor device.

(従来の技術) 従来、このような分野の技術としては、例えば実開昭6
1−182031号に記載されるものがあった。
(Prior art) Conventionally, as a technology in this field, for example,
There was one described in No. 1-182031.

第2図は従来の半導体装置のバンプ電極のメッキ方法の
説明図である。
FIG. 2 is an explanatory diagram of a conventional plating method for bump electrodes of a semiconductor device.

この図に示すように、ウェハ1上にバンプ電極をメッキ
で形成する際に、真空蒸着等の方法により、メッキ電流
を流すための導電性被膜2を施し、その後、レジスト等
のマスク材3を用いて、メッキをつけたい部分のみを開
孔するようにパターニングする。その状態で、マスク材
3の上からウェハ1表面に電極用ピン4を突き立て、ウ
ェハ1の裏面側から加圧することより、このビン4がマ
スク材3を突き破ってマスク材3直下の先に施した導電
性被膜2まで達するようにする。このように、メッキ電
流が電極用ピン4からウェハl上の導電性被膜2に流れ
るような状態にした上で、メッキ液5中に浸し、メッキ
を行うようにしていた。
As shown in this figure, when forming bump electrodes on a wafer 1 by plating, a conductive film 2 is applied by a method such as vacuum evaporation to allow the plating current to flow, and then a mask material 3 such as a resist is applied. Using this method, pattern the holes so that only the areas where you want to plate them are drilled. In this state, by sticking the electrode pin 4 into the surface of the wafer 1 from above the mask material 3 and applying pressure from the back side of the wafer 1, the pin 4 breaks through the mask material 3 and extends directly below the mask material 3. Make sure that it reaches the applied conductive coating 2. In this manner, the plating current was made to flow from the electrode pins 4 to the conductive coating 2 on the wafer l, and then the wafer was immersed in the plating solution 5 to perform plating.

また、上記のメッキ方法の他に、第3図に示すような方
法もある。即ち、第2図と同様に、真空蒸着等の方法に
より、ウェハ11表面に導電性被膜12を施し、その後
、レジスト等のマスク材13を用いて、メッキをつけた
い部分のみを開孔するようにバターニングする。更に、
ウェハ11の裏面から真空引きを行い、ウェハ11真面
に電極用ピン14を接触させ、メッキ電流を導通させる
。なお、ここで、15はマスクゴムである。
In addition to the above plating method, there is also a method as shown in FIG. That is, as in FIG. 2, a conductive film 12 is applied to the surface of the wafer 11 by a method such as vacuum deposition, and then a mask material 13 such as resist is used to open holes only in the areas where plating is desired. Butter it. Furthermore,
A vacuum is drawn from the back surface of the wafer 11, and the electrode pins 14 are brought into contact with the front surface of the wafer 11 to conduct plating current. In addition, here, 15 is mask rubber.

(発明が解決しようとする課題) しかしながら、上記した第1のメッキ方法では、電極用
ピン4が導電性被膜2まで突き破り、ウェハ1に達して
しまうと、半導体チップが不良となるため、電極用ピン
4の数や形状は厳しく制約される。また、電極用ピン4
はマスク材3を突き破ってメッキ電流を導通させるもの
であるが、マスク材3をうまく突き破れなかった場合に
は導通が不安定になり易いという問題があった。
(Problem to be Solved by the Invention) However, in the first plating method described above, if the electrode pins 4 break through to the conductive coating 2 and reach the wafer 1, the semiconductor chip becomes defective. The number and shape of the pins 4 are strictly limited. In addition, electrode pin 4
The plating current penetrates through the mask material 3 and conducts the plating current, but there is a problem in that if the mask material 3 cannot be penetrated successfully, the conduction tends to become unstable.

また、第2のメッキ方法によれば、上記第1のメッキ方
法における問題点は解決されるが、電極用ビンエ4がウ
ェハ11裏面のシリコンに直接接触しているため、ウェ
ハ11内の半導体チップ構造成いはウェハ11表面に施
された導電性被膜12とシリコンとの接触状態によって
は、全く導通しないという現象が起こる。また、ウェハ
11表面や内部における電気抵抗の差異を考慮してメッ
キ電流値を設定しなければならない等、課題が多く、安
定したメッキを行うことは困難であった。
Further, according to the second plating method, the problems in the first plating method are solved, but since the electrode binder 4 is in direct contact with the silicon on the back surface of the wafer 11, the semiconductor chips inside the wafer 11 are Depending on the structure and the state of contact between the conductive film 12 applied to the surface of the wafer 11 and silicon, a phenomenon occurs in which there is no conduction at all. Further, there are many problems such as the need to set the plating current value in consideration of differences in electrical resistance on the surface and inside of the wafer 11, and it has been difficult to perform stable plating.

更に、電極用ピンと導通性被膜との接触が不安定であっ
た場合、マスク材を突き破って、良好な接触をもたらす
ように、何回も作業を繰り返さなければならないといっ
た問題があった。
Furthermore, if the contact between the electrode pin and the conductive film is unstable, there is a problem in that the process must be repeated many times in order to break through the mask material and bring about good contact.

本発明は、以上述べた不良チップの発生と、メッキ電流
の導通の不安定及び作業性の低下という問題点を除去し
、不良チップの発生がなく、バンプ電極のメッキ形成を
安定して行い得る半導体装置のバンプ電極のメッキ方法
を提供することを目的とする。
The present invention eliminates the above-mentioned problems of the occurrence of defective chips, unstable conduction of plating current, and deterioration of workability, and enables stable plating of bump electrodes without the occurrence of defective chips. An object of the present invention is to provide a method for plating bump electrodes of a semiconductor device.

(課題を解決するための手段) 本発明は、上記目的を遠戚するために、半導体装置のバ
ンプ電極のメッキ方法において、ウェハの全面に導電性
被膜を施し、ウェハ裏面で前記導電性被膜と電極用ピン
との電気的導通を行い、バンプ電極のメッキを行うよう
にしたものである。
(Means for Solving the Problems) In order to achieve the above object, the present invention provides a method for plating bump electrodes of semiconductor devices, in which a conductive film is applied to the entire surface of a wafer, and the conductive film is removed from the back surface of the wafer. The bump electrode is plated by electrically connecting with the electrode pin.

(作用) 本発明によれば、上記したように、バンプ電極を形成し
ようとするウェハの全面に真空蒸着等の方法によって導
電性被膜を施し、しかる後、ウェハ表面にマスク材を塗
布し、バンプ電極を形成したい部分だけを開孔した状態
にし、ウェハの裏面側に電極用ピンを接触させ、メッキ
電流を導通させてバンプ電極を形成する。
(Function) According to the present invention, as described above, a conductive film is applied to the entire surface of the wafer on which bump electrodes are to be formed by a method such as vacuum deposition, and then a mask material is applied to the wafer surface, and the bump electrodes are formed on the wafer. A hole is opened only in the part where an electrode is to be formed, an electrode pin is brought into contact with the back side of the wafer, and a plating current is conducted to form a bump electrode.

(実施例) 以下、本発明の実施例について図面を参照しながら詳細
に説明する。
(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

第1図は本発明の実施例を示す半導体装置のバンプ電極
のメッキ方法の説明図である。
FIG. 1 is an explanatory diagram of a method of plating bump electrodes of a semiconductor device showing an embodiment of the present invention.

この図に示すように、真空蒸着等によりアルミニウム等
の導電性被膜22をバンプ電極を形成しようとするウェ
ハ21の全面、つまり表・裏・側面に施し、ウェハ21
の表裏で電気的導通がとれるようにしておく。
As shown in this figure, a conductive film 22 made of aluminum or the like is applied to the entire surface of the wafer 21 on which bump electrodes are to be formed, that is, the front, back, and side surfaces, by vacuum evaporation or the like.
Make sure that there is electrical continuity between the front and back sides.

その後、ウェハ21の表面側にレジスト等のマスク材2
3を塗布し、バンプ電極を形成したい部分だけを開孔す
るようにバターニングした状態にしておく。
After that, a mask material 2 such as a resist is placed on the front side of the wafer 21.
3 and leave it in a patterned state so that holes are formed only in the areas where bump electrodes are to be formed.

そこで、ウェハ21の裏面が電極用ピン24と接触する
ように、ラック25にセットする。このラック25はウ
ェハ21を保持、固定すると共に、通電することができ
る。つまり、ウェハ21の裏面の周縁にOリング26を
設置することにより、ウェハ21裏面の空所を外気に対
して密閉し、真空引きによってウェハ2工を吸着し、ウ
ェハ21の保持を行うと共に、ウェハ21への通電を行
わせる。
Therefore, the wafer 21 is set on the rack 25 so that the back surface thereof is in contact with the electrode pins 24. This rack 25 holds and fixes the wafer 21 and can be energized. That is, by installing the O-ring 26 around the periphery of the back surface of the wafer 21, the space on the back surface of the wafer 21 is sealed from the outside air, the wafer 2 is attracted by vacuum, and the wafer 21 is held. The wafer 21 is energized.

このようにして、ウェハ21を保持した状態でメッキ液
27に浸した後、メッキ電流を流してメッキを行う。
In this way, after holding the wafer 21 and immersing it in the plating solution 27, plating is performed by applying a plating current.

なお、本発明は上記実施例に限定されるものではなく、
本発明の趣旨に基づいて種々の変形が可能であり、これ
らを本発明の範囲から排除するものではない。
Note that the present invention is not limited to the above embodiments,
Various modifications are possible based on the spirit of the present invention, and these are not excluded from the scope of the present invention.

(発明の効果) 以上、詳細に説明したように、本発明によれば、導通性
被膜をウェハの全面に施した上で、ウェハ裏面からメッ
キ電流の導通をとるようにしたので、次のような効果を
奏することができる。
(Effects of the Invention) As described above in detail, according to the present invention, a conductive film is applied to the entire surface of the wafer, and the plating current is conducted from the back surface of the wafer, so that the following effects can be achieved. This effect can be achieved.

(1)電極用ピンをマスク材の上から突き立てないため
、不良チップの発生がなくなる。
(1) Since the electrode pins are not pushed up from above the mask material, the occurrence of defective chips is eliminated.

(2)導電性被膜によってウェハの全面が覆われている
ので、電気的導通が良く、半導体装置の素子構造及び製
造方法に拘わらず、安定したメッキを行うことができる
。例えば、PN接合が逆バイアスになっていてもよく、
また、ウェハの裏面に絶縁膜が残っていてもよい。
(2) Since the entire surface of the wafer is covered with a conductive film, electrical conductivity is good, and stable plating can be performed regardless of the element structure and manufacturing method of the semiconductor device. For example, the PN junction may be reverse biased,
Further, an insulating film may remain on the back surface of the wafer.

(3)電極用ピンは直接メッキ液に触れないため、メッ
キされることがなく、メンテナンスが不要である。
(3) Since the electrode pins do not come into direct contact with the plating solution, they are not plated and maintenance is unnecessary.

(4)電極用ピンでマスク材を突き破る必要がないため
、ピンの形状を自由に変えることができる。
(4) Since there is no need to break through the mask material with electrode pins, the shape of the pins can be changed freely.

(5)メッキ液の流れを阻害するものがなくなるため、
均一なメッキが可能となる。
(5) There is no obstruction to the flow of the plating solution,
Uniform plating is possible.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の実施例を示す半導体装置のバンプ電極
のメッキ方法の説明図、第2図は従来の半導体装置のバ
ンプ電極のメッキ方法の説明図、第3図は従来の他の半
導体装置のバンプ電極のメッキ方法の説明図である。 21・・・ウェハ、22・・・導電性被膜、23・・・
マスク材、24・・・電極用ピン、25・・・ラック、
26・・・Oリング、27・・・メッキ液。
FIG. 1 is an explanatory diagram of a method of plating bump electrodes of a semiconductor device showing an embodiment of the present invention, FIG. 2 is an explanatory diagram of a method of plating bump electrodes of a conventional semiconductor device, and FIG. 3 is an explanatory diagram of a method of plating bump electrodes of a conventional semiconductor device. FIG. 3 is an explanatory diagram of a method of plating bump electrodes of the device. 21... Wafer, 22... Conductive film, 23...
Mask material, 24... Electrode pin, 25... Rack,
26...O ring, 27...Plating liquid.

Claims (1)

【特許請求の範囲】[Claims]  ウェハの全面に導電性被膜を施し、ウェハ裏面で前記
導電性被膜と電極用ピンとの電気的導通を行い、バンプ
電極のメッキを行うことを特徴とする半導体装置のバン
プ電極のメッキ方法。
A method for plating bump electrodes of a semiconductor device, comprising applying a conductive film to the entire surface of a wafer, establishing electrical continuity between the conductive film and electrode pins on the back side of the wafer, and plating the bump electrodes.
JP28603289A 1989-11-04 1989-11-04 Plating method for bump electrode of semiconductor device Pending JPH03148133A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28603289A JPH03148133A (en) 1989-11-04 1989-11-04 Plating method for bump electrode of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28603289A JPH03148133A (en) 1989-11-04 1989-11-04 Plating method for bump electrode of semiconductor device

Publications (1)

Publication Number Publication Date
JPH03148133A true JPH03148133A (en) 1991-06-24

Family

ID=17699093

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28603289A Pending JPH03148133A (en) 1989-11-04 1989-11-04 Plating method for bump electrode of semiconductor device

Country Status (1)

Country Link
JP (1) JPH03148133A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003326419A (en) * 2002-05-09 2003-11-18 Sony Corp Plating method, plating device, and polishing method, polishing device, and method for manufacturing semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003326419A (en) * 2002-05-09 2003-11-18 Sony Corp Plating method, plating device, and polishing method, polishing device, and method for manufacturing semiconductor device

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