JPH03145722A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH03145722A JPH03145722A JP28522589A JP28522589A JPH03145722A JP H03145722 A JPH03145722 A JP H03145722A JP 28522589 A JP28522589 A JP 28522589A JP 28522589 A JP28522589 A JP 28522589A JP H03145722 A JPH03145722 A JP H03145722A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor substrate
- ions
- implanted
- temperature
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 239000012535 impurity Substances 0.000 claims abstract description 26
- 150000002500 ions Chemical class 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 25
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 18
- 239000007788 liquid Substances 0.000 claims abstract description 18
- 238000000034 method Methods 0.000 claims abstract description 15
- 238000000137 annealing Methods 0.000 claims abstract description 11
- 230000005465 channeling Effects 0.000 claims abstract description 10
- 239000013078 crystal Substances 0.000 claims abstract description 9
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 9
- 239000001307 helium Substances 0.000 claims abstract description 8
- 229910052734 helium Inorganic materials 0.000 claims abstract description 8
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims abstract description 8
- 238000001816 cooling Methods 0.000 claims abstract description 5
- 238000002513 implantation Methods 0.000 claims description 7
- 230000003213 activating effect Effects 0.000 claims 1
- 238000005468 ion implantation Methods 0.000 abstract description 14
- 230000007547 defect Effects 0.000 abstract description 6
- 238000009792 diffusion process Methods 0.000 abstract description 5
- 238000004904 shortening Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 6
- 238000009826 distribution Methods 0.000 description 5
- 239000007787 solid Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000007943 implant Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 230000008929 regeneration Effects 0.000 description 1
- 238000011069 regeneration method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26593—Bombardment with radiation with high-energy radiation producing ion implantation at a temperature lower than room temperature
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に関し、特に不純物活性
領域の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing an impurity active region.
イオン注入は半導体に不純物を導入する技術としてＬＳ
Ｉの製造に広く用いられている。イオン注入は熱平衡状
態を経ない物理的過程を利用する技術であるため、不純
物の量と深さを正確に制御できる。即ち、基板に注入さ
れるイオンによる電流を測定することにより注入量の精
度を極めて高くすることができ、また注入深さについて
はイオン−固体衝突の解明が進んでおり、基板とイオン
の種類、注入エネルギーが与えられれば注入分布はかな
り正確に予測し得る。Ion implantation is a technique used to introduce impurities into semiconductors.
It is widely used in the production of I. Ion implantation is a technology that uses a physical process that does not go through a thermal equilibrium state, so the amount and depth of impurities can be precisely controlled. In other words, by measuring the current caused by ions being implanted into the substrate, the accuracy of the implantation amount can be made extremely high, and the depth of implantation can be determined by elucidating ion-solid collisions, and by measuring the type of substrate and ions, Given the implant energy, the implant distribution can be predicted fairly accurately.
さて、固体中に入射したイオンは固体中の原子と衝突し
ながら進入し、次々にエネルギーを失って最後に静止す
るわけであるが、衝突がランダムに起こるために静止す
る位置はある平均値の回りに分布を持っている。その結
果、イオン注入によって形成した不純物領域のプロファ
イルは第４図に示すようなガウス分布で近似できる形と
なる。Now, an ion that enters a solid enters while colliding with atoms in the solid, loses energy one after another, and finally comes to rest, but since collisions occur randomly, the position at which it comes to rest is a certain average value. It has a distribution around it. As a result, the profile of the impurity region formed by ion implantation has a shape that can be approximated by a Gaussian distribution as shown in FIG.
さらにイオンチャネリングを避けるためにイオン注入を
行う際に基板に立てた法線に対して打ち込み面を７度傾
けて行うことにより、不純物領域のプロファイル上のイ
オン進入深さに対して幅を広げないようにされていた。Furthermore, in order to avoid ion channeling, when performing ion implantation, the implantation surface is tilted at 7 degrees with respect to the normal to the substrate, so that the width does not increase with respect to the ion penetration depth on the profile of the impurity region. It was like that.
〔発明が解決しようとする課題］
前記従来の半導体装置の製造方法ではイオン注入の性質
上不純物プロファイルがガウス分布になり、急峻な不純
物プロファイルの得られる半導体装置の製造方法を実現
することが困難であった。[Problems to be Solved by the Invention] In the conventional semiconductor device manufacturing method described above, the impurity profile has a Gaussian distribution due to the nature of ion implantation, and it is difficult to realize a semiconductor device manufacturing method that can obtain a steep impurity profile. there were.
また、イオン注入に対し打ち込み面を７度傾けて行って
もチャネリングを完全に防止することができず、不純物
領域プロファイルにばらつきを生しさせるという問題や
、イオンと固体原子の衝突により格子欠陥が発生し、結
晶性の回復のために高温のアニールを施さなければなら
ないという問題があった。Furthermore, even if the implantation surface is tilted at 7 degrees with respect to ion implantation, channeling cannot be completely prevented, leading to problems such as variations in the impurity region profile and the formation of lattice defects due to collisions between ions and solid atoms. There was a problem in that high-temperature annealing had to be performed to restore crystallinity.
本発明は以上のような従来の問題点を解消するためにな
されたもので、急峻な不純物プロファイルとなる特性が
得られ、かつイオン注入による欠陥の回復のためのアニ
ールを低減できる半導体装置の製造方法を得ることを目
的としＣいろ。The present invention has been made in order to solve the above-mentioned conventional problems, and is aimed at manufacturing a semiconductor device that can obtain characteristics that provide a steep impurity profile and can reduce annealing for recovering defects caused by ion implantation. C color with the purpose of obtaining the method.
この発明に係る半導体装置の製造方法は、半導体基板の
格子点におりＪる原子の振動を小さくづるために液体窒
素または液体・＼リウムにより半導体基板を各々液体窒
素温度または液体ヘリウム温度まで冷却する工程と、該
半導体基板の主面側にチャネリングを促すために半導体
基板の結晶軸方向にイオン注入する工程と、低温でのア
ニールにより不純物の活性化を行う工程とを含み不純物
活性領域を形成するものである。In the method for manufacturing a semiconductor device according to the present invention, the semiconductor substrate is cooled to liquid nitrogen temperature or liquid helium temperature using liquid nitrogen or liquid lium, respectively, in order to reduce vibrations of atoms located at lattice points of the semiconductor substrate. forming an impurity active region; It is something.
（作用〕
この発明においては、以上のような方法としたから、形
成される不純物活性領域は、急峻なプロファイル特性を
持つものとなり、さらにイオン注入による格子欠陥が低
減でき、不純物の熱拡散による再分布を抑制し、高温で
のアニールを不要とすることができる。(Function) In this invention, since the method described above is adopted, the formed impurity active region has a steep profile characteristic, furthermore, lattice defects caused by ion implantation can be reduced, and regeneration by thermal diffusion of impurities can be reduced. It is possible to suppress the distribution and eliminate the need for high-temperature annealing.
以下、この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第１図は本発明の半導体装置の製造方法を示す図であり
、図において、１は半導体基板、２は冷却装置である。FIG. 1 is a diagram showing a method for manufacturing a semiconductor device according to the present invention. In the diagram, 1 is a semiconductor substrate and 2 is a cooling device.
次に製造方法について説明する。Next, the manufacturing method will be explained.
先ず、半導体基板１を冷却装置２−トにのせ、液体窒素
あるいは液体ヘリウムにより、液体窒素温度あるいは液
体ヘリウム温度まで冷却する。First, the semiconductor substrate 1 is placed on a cooling device 2 and cooled to liquid nitrogen or liquid helium temperature using liquid nitrogen or liquid helium.
次にイオンチャネリングを起こすように半導体基板Ｉの
結晶軸の方向にイオン注入を行う。例えば、Ｓｉ （
１００）基板の場合、半導体基板に立てた法線方向に相
当する軸方向にイオン注入する。Next, ions are implanted in the direction of the crystal axis of the semiconductor substrate I so as to cause ion channeling. For example, Si (
100) In the case of a substrate, ions are implanted in the axial direction corresponding to the normal direction to the semiconductor substrate.
次に低温でのアニールにより不純物の活性化を行い、注
入されたイオンの熱拡散による再分布を防ぐ。Next, the impurities are activated by annealing at a low temperature to prevent redistribution of the implanted ions due to thermal diffusion.
以下、本発明による半導体装置の製造方法の作用効果に
ついて述べる。The effects of the method for manufacturing a semiconductor device according to the present invention will be described below.
本発明による半導体装置の製造方法ではイオン注入は半
導体基板の結晶軸方向に行われるので、注入されたイオ
ンはチャネリングを起こし、半導体基板の格子点にある
原子と近接衝突を起こすことなく結晶軸に囲まれた空間
を交互に相対する軸への接近を繰り返しつつ通過する。In the method for manufacturing a semiconductor device according to the present invention, ion implantation is performed in the direction of the crystal axis of the semiconductor substrate, so the implanted ions cause channeling and follow the crystal axis without causing close collision with atoms at lattice points of the semiconductor substrate. It passes through the enclosed space by repeatedly approaching opposing axes.
その結果、従来のイオン注入のように衝突がランダムに
起こるわけでなく、エネルギーの損失の割合が同程度と
なり、イオンの静止する位置のばらつきが小さくなり、
急峻なプロファイルを持つようになる。As a result, collisions do not occur randomly as in conventional ion implantation, and the rate of energy loss is about the same, reducing the variation in the positions at which the ions rest.
It will have a steep profile.
ここで、室温でチャネリング注入を行う場合、半導体基
板の格子点にある原子は格子点の位置を中心とする格子
振動をしており、また、振動に際して結晶軸からはずれ
ている時点がある。このような時点に注入されたイオン
が通過すると衝突を起こし、イオンは結晶軸から外れて
しまう。この現象はデイチャネリングと呼ばれ、このた
めに不純物プロファイルは第２図に示すように２つのピ
ークの重なり合った形となる。この図において表面側で
のピークは格子振動によりデイチャネリングしたイオン
の成分によるものであり、深い位置側でのピークはチャ
ネリングしたイオンの成分によるものである。Here, when channeling implantation is performed at room temperature, atoms at lattice points of the semiconductor substrate undergo lattice vibration centered on the position of the lattice point, and there are times when the atoms deviate from the crystal axis during the vibration. If ions implanted at such a point pass through the crystal, they will collide, causing the ions to deviate from the crystal axis. This phenomenon is called day channeling, and as a result, the impurity profile takes the form of two overlapping peaks, as shown in FIG. In this figure, the peak on the surface side is due to the components of ions de-channeled due to lattice vibration, and the peak on the deep side is due to the components of channeled ions.
本発明では基板を液体窒素温度あるいは液体ヘリウム温
度にまで冷却するので格子振動は小さくなり、デイチャ
ネリングするイオンの成分が少なくなる。その結果、不
純物プロファイルは第３図に示ずようなチャネリングし
た成分による象、峻なプロファイルとなる。また、チャ
ネリングにおける注入されたイオンは格子点の原子と小
角散乱のみを繰り返すだけで半導体基板中に進入できる
ので、格子原子は格子位置からあまり動かず、結果とし
て格子欠陥は生しにくくなる。よって従来のイオン注入
において必要であった結晶性の回復のための高温でのア
ニールは必要でなくなり、注入されたイオンの活性化の
ための低温アニールのみでよくなり、熱拡散による注入
されたイオンの再分布の程度を減少させることができる
。In the present invention, since the substrate is cooled to liquid nitrogen temperature or liquid helium temperature, lattice vibration becomes small and the number of ion components to be dechanneled is reduced. As a result, the impurity profile becomes a steep profile due to channeled components as shown in FIG. In addition, ions implanted during channeling can enter the semiconductor substrate by simply repeating small-angle scattering with atoms at lattice points, so lattice atoms do not move much from their lattice positions, and as a result, lattice defects are less likely to occur. Therefore, high-temperature annealing to restore crystallinity, which was necessary in conventional ion implantation, is no longer necessary, and only low-temperature annealing is required to activate the implanted ions, allowing the implanted ions to be removed by thermal diffusion. The degree of redistribution of can be reduced.
このような本実施例では、Ｌ ＣＣ（Ｌｉｇｈｔｌｙ
Ｃ。In this embodiment, L CC (Lightly
C.
ｎｃｅｎｔｒａｔｉｏｎ Ｃｈａｎｎｅｌ） ）ランジ
スタのようにＭＯＳトランジスタのチャネルの表面が低
濃度で不純物濃度が象、峻に変化する構造を有する半導
体装置を生成できる。)) It is possible to produce a semiconductor device having a structure, such as a transistor, in which the surface of the channel of a MOS transistor is lightly doped and the impurity concentration changes sharply.
以上のように本発明によれば、不純物濃度が急峻に変化
する構造を有する半導体装置を容易に生成でき、さらに
イオン注入による格子欠陥を低減でき、不純物の熱拡散
による再分布を抑制し、高温でのアニールを不要とする
効果がある。As described above, according to the present invention, it is possible to easily produce a semiconductor device having a structure in which the impurity concentration changes sharply, furthermore, it is possible to reduce lattice defects caused by ion implantation, suppress the redistribution of impurities due to thermal diffusion, and This has the effect of eliminating the need for annealing.
第１図は本発明の一実施例による半導体装置の製造方法
を示す図、第２図は室温でチャネリング注入を行った時
に得られる不純物プロファイルを示す図、第３図は基板
を冷却してチャネリング注入を行った時に得られる不純
物プロファイルを示す図、第４図は従来のイオン注入に
よって得られる不純物プロファイルを示す図である。
１は半導体基板、２は冷却装置である。
なお図中同一符号は同−又は相当部分を示す。FIG. 1 is a diagram showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, FIG. 2 is a diagram showing an impurity profile obtained when channeling implantation is performed at room temperature, and FIG. 3 is a diagram showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 4 is a diagram showing an impurity profile obtained by conventional ion implantation. 1 is a semiconductor substrate, and 2 is a cooling device. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
するために液体窒素または液体ヘリウムにより半導体基
板を各々液体窒素温度または液体ヘリウム温度まで冷却
する工程と、 該半導体基板の主面側にチャネリングを促すように半導
体基板の結晶軸方向にイオン注入する工程と、 低温でのアニールにより不純物の活性化を行う工程とを
含み不純物活性領域を生成することを特徴とする半導体
装置の製造方法。(1) Cooling the semiconductor substrate with liquid nitrogen or liquid helium to liquid nitrogen temperature or liquid helium temperature, respectively, in order to reduce vibrations of atoms at lattice points of the semiconductor substrate, and channeling on the main surface side of the semiconductor substrate. 1. A method for manufacturing a semiconductor device, comprising a step of implanting ions in the direction of a crystal axis of a semiconductor substrate in a manner that promotes impurity implantation, and a step of activating impurities by annealing at a low temperature to generate an impurity active region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28522589A JPH03145722A (en) | 1989-10-31 | 1989-10-31 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28522589A JPH03145722A (en) | 1989-10-31 | 1989-10-31 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03145722A true JPH03145722A (en) | 1991-06-20 |
Family
ID=17688726
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28522589A Pending JPH03145722A (en) | 1989-10-31 | 1989-10-31 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03145722A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06252082A (en) * | 1993-02-25 | 1994-09-09 | Nec Corp | Ion implantation method |
| EP2150632A1 (en) * | 2007-06-06 | 2010-02-10 | OPC Laser Systems LLC | Method for eliminating defects from semiconductor materials |
-
1989
- 1989-10-31 JP JP28522589A patent/JPH03145722A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06252082A (en) * | 1993-02-25 | 1994-09-09 | Nec Corp | Ion implantation method |
| EP2150632A1 (en) * | 2007-06-06 | 2010-02-10 | OPC Laser Systems LLC | Method for eliminating defects from semiconductor materials |
| JP2010528970A (en) * | 2007-06-06 | 2010-08-26 | オーピーシー レーザー システムス エルエルシー | Method for removing defects from semiconductor materials |
| EP2150632A4 (en) * | 2007-06-06 | 2012-06-20 | Opc Laser Systems Llc | Method for eliminating defects from semiconductor materials |
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