JPH03145233A - Digital audio equipment - Google Patents

Abstract

PURPOSE:To prevent a digital audio signal from being discontinuous by detecting a level of a digital audio signal so as to make a margin of a digital buffer memory close to an initial setting value. CONSTITUTION:A serial data signal 24 with deteriorated jitter being an output of a reception means 21, a bit clock 25 and a word clock 26 are inputted to a memory control means 31 and also to a level detector 38. The internal circuit of the level detector 38 compares the inputted digital audio signal with a prescribed level and the signal 24 is discriminated to be a non-audio part when the state of a prescribed level or below is consecutive for a prescribed time or over and a non-audio part detection signal 39 is outputted. Then the memory control means 31 adjusts a write signal by the input of the signal 39 to make a difference between a write address and a read address of the digital buffer memory 32 close to an initial setting value. Thus, discontinuous digital audio signal is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a self-clock digital audio device that self-generates a clock from a transmitted digital audio signal.

BACKGROUND OF THE INVENTION In recent years, digital sound sources have become widespread, primarily in the form of compact discs for consumer use, and are expanding further to include laser discs, digital audio chips, and satellite broadcasting. Digital audio signals are characterized by the ability to easily transmit and reproduce audio with lower distortion and a larger dynamic range than analog audio, and special processing that is difficult to achieve with analog, such as filtering with constant group delay, is possible with digital audio signals. This can be achieved using processing technology without being affected by variations in elements such as resistors, capacitors, and coils.

The digital audio equipment mentioned above has come to adopt a digital transmission method that outputs not only demodulated analog audio signals but also digital audio signals as they are during playback. Furthermore, DA units and digital amplifier devices for receiving and reproducing digital audio signal output are being actively developed.

An example of the above-mentioned conventional digital audio equipment will be described below with reference to the drawings.

FIG. 4 shows a block diagram of an example of a conventional digital audio device. In FIG. 4, 1 is a transmitting digital audio device, 2 is a receiving digital audio device, 11 is a digital audio signal demodulating means, 12 is a crystal oscillator, 13 is a digital audio signal transmitting device, and 21 is a digital audio signal transmitting device. 22 represents a PLL means, and 23 represents arithmetic processing means such as filtering.

The operation of the digital audio device configured as described above will be described below.

In the transmitting digital audio device 1, the demodulating means 11 demodulates a modulated digital signal read from a medium such as a compact disk (not shown), and generates a three-wire digital audio signal as shown in FIG. , a serial data signal 14, a pit clock 15, and a word clock 16. This demodulation means is a crystal oscillator 1
2 as a reference clock, and therefore, the precision of the output serial data signal 14, pit clock 15, and word clock 16 in the time axis direction is crystal precision. The serial data signal 14, the pit clock 15, and the word clock 16 are input to the transmitting means 13, and are digital audio signals 19 of a self-clocking type such as pi-phase modulation including the synchronization pattern shown in FIG.
The signal is modulated and sent to the receiving digital audio device 2.

In the receiving digital audio device 2, the digital audio signal 19 is first input to the receiving means 21, and the serial data signal 24, the pit clock 25, and the word clock 2 are input to the receiving means 21.
It is separated and demodulated into 6. This receiving means 21 operates based on the clock generated by the PLL means 22. The serial data signal 24, the pit clock 25, and the word clock 26 are input to the arithmetic processing means 23, and after being subjected to filtering processing, the D/A (not shown)
It is input to a converter and converted into an analog signal, or sent as a digital signal to other digital audio equipment.

Optical cables and coaxial cables are mainly used for transmission from the transmitting digital audio device 1 to the receiving digital audio device 2, but it is inevitable that the jitter of the digital audio signal 19 increases during transmission. Depending on the configuration of the PLL means 22 configured inside the receiving means 21, the received serial data signal 24, pit clock 25, and word clock 26 may be different from the serial data signal 14, pit clock 15, and word clock 26 before transmission. , the jitter is considerably worse than that of the word clock 16, which had crystal accuracy in the time axis direction.

Therefore, in order to eliminate the deterioration of jitter, a digital audio device as shown in FIG. 7 has been proposed. (Patent Application Hei 1-
See the specification attached to No. 31792>.

FIG. 7 shows a block diagram of an improved example of conventional digital audio equipment. In FIG. 7, components common to those in FIG. 4 are represented by the same numbers, and descriptions of parts that perform common operations will be omitted. Further, 27 represents a crystal oscillator, 31 represents a memory control means, and 32 represents a digital buffer memory.

The serial data signal 24 with deteriorated jitter, the pit clock 25 and the word clock 26 output from the receiving means 21 are inputted to the memory control means 31 . The memory control means 31 controls the data signal 33 and address signal 34 of the digital buffer memory 32, and according to the input serial data signal 24, pit clock 25, and word clock 26,
If there is an input, it operates to sequentially write digital audio signals into the digital buffer memory 32.

On the other hand, the arithmetic processing means 23 has its own crystal oscillator 27 to output a crystal-accurate digital audio signal.
This crystal oscillation! A pit clock 29 and a word clock 30 created by frequency-dividing the clock of S27 are input to the memory control means 31. The memory control means 31 sequentially reads digital audio signals from the digital buffer memory 32 in accordance with the output pit clock 29 and the word clock 30 and outputs them as serial data signals 28 to the arithmetic processing means 23. In this manner, jitter superimposed during transmission is removed by reading out the digital audio signal once written in the digital buffer memory 32 using a crystal-accurate clock.

Problems to be Solved by the Invention However, in the conventional configuration as shown in FIG. If a sufficient amount of time passes, the write address will catch up with the read address, or conversely, the read address will catch up with the write address, resulting in a point at which the digital audio signal becomes discontinuous.

The present invention solves the above-mentioned conventional problems, and is a digital audio device equipped with a finite digital buffer memory. It is an object of the present invention to provide a DigiMole audio Ia device that does not cause discontinuity.

Means for Solving the Problems In order to solve the above problems, the digital audio equipment of the present invention includes a digital buffer memory that temporarily stores a digital audio signal, and a digital audio device that continuously maintains the amplitude level of the digital audio signal at a predetermined level for a predetermined period of time or more. , and a memory control means for bringing the margin of the digital buffer memory closer to an initial setting value based on the output of the level detector.

The digital audio device of the present invention has the above-described configuration, so that when the amplitude level of the input digital audio signal is continuously lower than a predetermined level for a predetermined period of time or more, the margin of the digital buffer memory is brought close to the initial setting value. The write address can be controlled to ensure that the write address does not catch up with the read address, or vice versa, causing a discontinuity point in the digital audio signal. .

Embodiment Below, regarding a digital audio device according to an embodiment of the present invention,
This will be explained with reference to the drawings.

FIG. 1 shows a block diagram of a digital audio device according to a first embodiment of the present invention. In FIG. 1, components common to FIGS. 4 and 7 are represented by the same numbers. Further, 38 represents a level detector.

The operation of the digital audio device configured as described above will be explained, focusing on the differences from the examples shown in FIGS. 4 and 7.

The jitter-deteriorated formal data signal 24, pit clock 25, and word clock 26 output from the receiving means 21 are input to the memory control means 31, and at the same time, they are also input to the level detector 38. Inside the level detector 38, the input digital audio signal is compared with a predetermined level, and when the state of being below the predetermined level continues for a predetermined time or more, it is determined that the manually input digital audio signal is a silent part. Then, a silent portion detection signal 39 is output. This silent part detection signal 39 is transmitted to the memory control means 3.
1 is input. When the silent part detection signal 39 is input, the memory control means 31 adjusts the signal written to the digital buffer memory 32, and operates to bring the difference between the write address and the read address of the digital buffer memory 32 close to the initial setting value. do.

An example of how to adjust addresses will be explained in more detail.

The simplest method is to quench all of the digital buffer memory 32 when the silent part detection signal 39 is input, and restart the write address and read address from the initial setting values. However, with this method, immediately after being cleared, there is no sound until the read address advances to the initial value of the write address.
When a very short silent section is played back, the silent section may become too long, causing an unnatural feeling.

Therefore, in order to prevent this problem from occurring,
The adjustment may be performed one sample at a time each time a sample digital audio signal is input. For example, if the silence detection signal 39 is input and the address difference between writing and reading is larger than the initial setting value, if one sample of silence signal is input, this signal will not be written and will be sent to the write address. is not incremented. Then, since reading is performed normally, the address difference is adjusted to be smaller by one sample. Conversely, if the silence detection signal 39 is input and the address difference between writing and reading is smaller than the initial setting value, if one sample of silence signal is further input, 2
Writes a sample of silence signal. Then,
Since reading is performed normally, the address difference is adjusted to increase by one sample.

FIG. 2 is a block diagram of another embodiment of the present invention, which is a digital audio device implemented by software using a general-purpose digital signal processor, and FIG. 3 is a flowchart of the software. . In FIG. 2, components common to FIGS. 4 and 7 are represented by the same numbers. Further, 41 represents a digital signal processor, and 42 represents a data memory of the digital signal processor.

The operation of the digital audio device configured as described above will be described with reference to the flowchart in FIG. 3, focusing on the differences from the examples shown in FIGS. 4 and 7.

Input/output of digital audio signals to/from the digital signal processor 41 is performed via an input register and an output register inside the digital signal processor 41. Receiving means 2
Serial data signal 2 with worsened jitter, which is the output of 1
4, bit clock 25 and word clock 26
is input to the input register of the digital signal processor 41. Further, a digital audio signal is outputted from the output register in response to an output pit clock 29 which is a frequency-divided oscillation clock of the crystal oscillator 27 operating the arithmetic processing means 23, and a word clock 3°. The output is complete and it is required to transfer the next digital audio signal to the output register. If there is an output request, the next digital audio signal is read from the data memory 42 and the read address is incremented. If there is no output request, it is checked whether a new digital audio signal has been input to the input register, and if there is no input, the process returns to the start. If there is an input, the amplitude level of the input signal is compared with a predetermined value. If the input signal is at a predetermined level or higher, the input signal is written into the memory, the write address is incremented, and then the process returns to the start. If the level is below the predetermined level, check how long the state of being below the predetermined level has continued in the past. If it is less than the predetermined time, write the input signal to memory and increment the write address, then
Return to start. If this continues for a predetermined period of time or longer, the address difference will be adjusted. That is, if the address difference is greater than or equal to the initial setting value, the input digital audio signal is ignored and the process returns to the start without doing anything. If the address difference is less than the initial setting value, the operation of writing the input signal to the memory and incrementing the write address is repeated twice. By doing this, since reading is performed normally, the address difference is adjusted in the direction of approaching the initial setting value one sample at a time.

Effects of the Invention As described above, the digital audio device of the present invention includes a digital buffer memory that temporarily stores a digital audio signal, and a digital audio device that detects that the amplitude level of the digital audio signal is continuously smaller than a predetermined level for a predetermined period of time or more. By providing a level detector for detection and a memory control means for bringing the margin of the digital buffer memory closer to the initial setting value using the output of the level detector, the write address can catch up with the read address, Alternatively, the read address may catch up with the write address, or conversely, the read address may catch up with the write address, causing a point at which the digital audio signal becomes discontinuous. It is possible to avoid this.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a digital audio device that is a first embodiment of the invention, FIG. 2 is a block diagram of a digital audio device that is a second embodiment of the invention, and FIG. 3 is a block diagram of a digital audio device that is a second embodiment of the invention. FIG. 4 is a block diagram of the example of conventional digital audio equipment shown in FIG. 1, FIG. 5 is a waveform diagram showing an example of a 3-wire digital audio signal, and FIG. 7 is a waveform diagram showing an example of a pi-phase modulated digital audio signal including a synchronization pattern.
The figure is a block diagram of a second example of conventional digital audio equipment. 1...Digital audio equipment for reception, 2...
- Digital audio equipment for transmission, 11... Demodulation means, 12... Crystal oscillator, 13... Transmission means, 21... Receiving means, 22... ...P
LL means, 23... Arithmetic processing means, 27...
...Crystal oscillator, 31...Memory control means, 32...Digital buffer memory, 3
8...Level detector.

Claims (1)

[Claims] A self-clock digital audio device that self-generates a clock from a transmitted digital audio signal includes a digital buffer memory that temporarily stores the digital audio signal, and a digital audio device whose amplitude level remains constant for a predetermined period of time or more. What is claimed is: 1. A digital audio device comprising: a level detector that detects that the level is lower than a predetermined level; and memory control means that uses the output of the level detector to bring a margin of a digital buffer memory closer to an initial setting value.