JPH03144999A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To conduct a test with a small operation margin in a short time by setting a relatively high or low level which is written in a memory cell to the intermediate value between a relatively high and a relatively low level in normal mode in response to a test mode. CONSTITUTION:Signals, the inverse of RAS, the inverse of CAS, and the inverse of W (write enable signal), are inputted to a timing circuit 20. The circuit 20 supplies a test signal T to a write amplifier 30 when the signals, the inverse of CAS and the inverse of W, are at L level. When data is written in the memory cell MC, external input data is inputted from an input pin Din to a data input buffer 40 and a signal IWD and a signal, the inverse of IWD are supplied to the amplifier 30. In response to the test signal T, the amplifier 30 sets one of the 1st relatively high level and 2nd relatively low level, which are written in the cell MC, to the intermediate level between the 3rd relatively high level and 4th relatively low level, which are written in the normal mode, to generate a write voltage, thereby performing writing operation.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor memory device, and in particular, to writing to a memory cell of a dynamic random access memory (hereinafter referred to as DRAM) having a plurality of memory cells during testing. This invention relates to shortening test time by suitably performing tests.

[Conventional technology]

The density of semiconductor memory has increased fourfold in just three years. Increasing the capacity means a rapid increase in RAM test time, which reduces productivity.

Shortening test time is essential in memory production as it leads to price increases. Memory cell write.

Not only in read tests, but also in more time-consuming combination tests such as input signal timing conditions for errors that cannot be detected in these tests, address signal address order specification, etc., most malfunctions occur in memory cells with small operating margins. be. Therefore, there is a need to efficiently test the operating margins of these memory cells.

FIG. 10 is a block diagram showing a schematic configuration of a conventional DRAM.

In FIG. 10, DRAMI is memory cell array 2.
．． Row address buffer 3. Column address buffer 4
．． Row decoder5. Column decoder 6, sense amplifier 7
, an input/output circuit (I10 circuit) 8 and a control circuit 9. As shown in FIG. 11, the memory cell array 2 includes a plurality of memory cells MC each consisting of a transfer gate TG consisting of an N-channel MOS transistor and a cell capacitor C8 in which mH "level" or "L" level information is stored, arranged in a matrix. They are arranged in a shape. Row address buffer 3 receives an external row address signal and generates an internal row address signal. Further, column address buffer 4 receives an external column address signal and generates an internal column address signal. Row decoder 5 and column decoder 6 respectively decode internal row and column address signals to select the corresponding row and 9 columns of memory cell array 2.

The sense amplifier 7 detects and amplifies the information stored in the selected memory cell MC of the memory cell 2, and outputs I10.
Readout through circuit 8. In addition, in order to control the timing of various DRAMI operations, clock, chip selection,
A control circuit 9 to which read/write control signals are externally applied is provided as a peripheral circuit.

In FIG. 8, which is a schematic diagram of the memory cell array 2 shown in FIG. 10 and its peripheral portion, a plurality of word lines WL
A plurality of bit line pairs BL, BL are arranged so as to intersect (WL, WLany., WLn). The bit lines constitute folded bit lines, and each bit line pair BL, B
In L, a memory cell MC is located at the intersection of one word line WL and one of the pair of bit lines BL or BL.
is connected. Further, dummy word lines DWL, DWL connected to the dummy word line control circuit 10 are arranged so as to intersect the bit line pair BL, BL. A dummy cell DCo is provided at the intersection of the dummy word line DWLo and the bit line BL, and the dummy word line DWL,
A dummy cell DC is provided at the intersection between the bit line BL and the bit line BL.

Each bit line pair BL, BL has a signal φ8. precharges each bit line pair potential to a predetermined potential vBL in response to
A precharge/equalization circuit 11 for balancing is provided. Further, each bit line pair BL, BL has a sense amplifier 7a which is activated in response to signals SE, SE from the sense amplifier drive circuit 12, and detects and amplifies the potential difference between the corresponding bit line pair BL, BL. provided. A plurality of word lines WL are connected to a row decoder 5. Each bit line pair BL, BL is selectively connected to data input/output line pair I1 via transfer gates TO, TI in I10 circuit 8a in response to an address decode signal from column decoder 6.
0. Connected to I10.

FIG. 12 shows one pair of bit lines BL, BL and word line WLo in the memory cell 2 shown in FIG. 11.

FIG. When reading data, first, the bit lines BL, BL are precharged to a certain voltage and then disconnected from the precharge circuit 11a to be in a floating state. Next, the row decoder 5 selects one word line WL.
is selected. As a result, the transfer gate TG of the memory cell MC connected to the word line WL becomes conductive, and the data stored in the cell capacitor C8 in the memory cell MC is read onto the bit line BL or BL. For example, when the potential of the word line WLo is raised to the 4H" level, the memory cell M is placed on the bit line BL.
Data of C' is read.

On the other hand, when none of the word lines WL is selected, the dummy word lines DWL, both of which are at 'L' level,
, DWLl, only the dummy word line DWLl is "
The level becomes H2, and the potential in dummy cell DC1 is read onto bit line BL.

At this time, the potential of the bit line BL provides a reference potential for the bit line BL. After that, bit line pair BL
, BL is amplified by the sense amplifier 7a. Column decoder 6 turns on any one set of transfer gates To, Tl, and data on a pair of bit lines BL, BL connected thereto is read out to data input/output line pair I10, Ilo.

Here, each bit line pair BL when data continues to be output.

Consider the change in potential appearing on BL.

As shown in FIG. 12, the stray capacitance of each bit line BL, BL is set to 1 by C1 memory cell MC and the cell capacitor capacitance of dummy cells DC, DC is C8. The charge stored in the cell capacitor of memory cell MC becomes C3vcc (vcc write) when "H" level data is stored, and becomes 0 (Ov write) when aL@ level data is stored. ). Also, dummy cell DCo.

DC cell capacitor has CsV cc/2 (V C
C/2 write) charge is stored. Bit line pair BL
, BL are set to V before the read operation. , /2, the charge on each bit line BL, BL is CBv
It becomes oC/2.

In FIG. 12, for example, when data is read from the memory cell MC' onto the bit line BL and a potential from the dummy cell DC1 is read onto the bit line BL, charge storage is achieved before and after data reading. Considering this, the respective potentials v and - of the bit lines BL and BL can be obtained from the following equations.

BL BL CBvcc/2+C8(1/2±1/2)vo.

-(CB+C3)VBL ・(1)(+ is ″H
When writing the level, - is when writing the L” level) Cs V cc/ 2 + Cs V cc/ 2”
(CB+Cs)Vπ...(2) From this,
The potential difference ΔvBL between the bit lines BL and BL is expressed by the following equation.

'"BL-"BL-"BL [Problem to be solved by the invention] When the cell capacitor capacitance C8 of the memory cell MC is small,
From equation (3), bit line pair BL when successive occurrences.

The potential difference of BL becomes smaller, and the successive output margin decreases. As a result, the sense amplifier 7a may malfunction and cause a bit defect.

This operation margin defect is the main cause of malfunction, but in order to detect memory cell defects including this defect, write/read tests, tests in combination with input signal timing conditions, etc. are performed. However, as the capacity of semiconductor memories increases, there is a problem in that each test takes a very long time.

The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a dynamic semiconductor memory device that can test memory cells with a small operating margin in a short time.

[Means to solve the problem]

The present invention relates to a semiconductor memory device including a plurality of memory cells consisting of one insulated gate field effect transistor and one capacitor, in response to a signal in a predetermined state different from that during normal operation being applied to an external terminal. at least one of a relatively high first level and a relatively low second level written to the memory cell in response to the test mode detection means for detecting the test mode detecting the test mode; is set to an intermediate level between a relatively high third level and a relatively low fourth level written in the normal mode.

[Effect]

In the semiconductor memory device according to the present invention, in response to the test mode, a relatively high first
or the relatively low level of at least one of the second novels, and the relatively high level of the third novel written during normal mode.
Since the level is set to a level between the fourth level and the relatively low fourth level, the potential difference between the bit line pair becomes small when data is read from the memory cell, making it possible to test memory cells with a small operating margin in a short time. can.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic block diagram showing an embodiment of a semiconductor memory device according to the present invention. For simplicity, the portion of the memory cell array 2 equivalent to that shown in FIG.
Paired bit line BL.

Only BL and word lines WL, WL are shown. This embodiment compares at least one of a relatively high first level written to a memory cell MC and a relatively low second level written in a normal mode in response to a timing condition of a human input signal. This is set at an intermediate level between the third level, which has a high target, and the fourth level, which has a relatively low target. For this purpose, a timing detection circuit 20 is provided, and this timing detection circuit 20 includes a RAS signal (row address strobe signal), a CAS signal (column address strobe signal), and a W signal (write enable signal).
is given. The timing detection circuit 20 outputs the test signal T to the write amplifier 30 if the CAS signal and the W signal are at the 'L' level when the RAS signal falls to the 'L' level.
give to

When writing data to the memory cell MC, external input data is input from the external data input bin Din to the data manual buffer 40, and the data is input to the IWD according to the manual data.
and the IWD signal to write amplifier 30. The write amplifier 30 includes a test mode switching circuit as will be described in detail later, and uses the IWD signal and the IWD signal to select the data input/output line pair I10 . A data write voltage to the memory cell MC is generated at I10. This signal is transmitted to the selected bit line pair BL, BL, and data is written into the designated memory cell MC.

2 is a circuit diagram showing the timing detection circuit 20 of FIG. 1, and FIG. 3 is a circuit diagram showing the write amplifier 30 of FIG. 1. A more specific configuration of an embodiment of the present invention will be described below with reference to FIGS. 2 and 3.

In FIG. 2, the CAS signal is inverted by an inverter 201 and input to one input terminal of a three-way AND gate 203, and an N-channel MOS transistor 206
source. The W signal is inverted by an inverter 202 and input to one input terminal of a three-way AND gate 203, and is also input to an N-channel MOS transistor 20.
7 sources. RAS signal is inverter 2
04, the one-shot pulse generation circuit 20
5 is input. The one-shot pulse generation circuit 205 generates a one-shot pulse at the falling timing of the RAS signal, and this pulse is generated by the three-man AND gate 2.
It is input to the 1 input terminal of 03. 3 person AND gate 20
The output of 3 is the N-channel MOS transistor 206 and 2
You can input to gate 07. The drain outputs of transistors 206 and 207 (N-channel MOS) are connected to the inverter 20.
8 and 209, and 210 and 211, respectively, are connected to the inputs of latch circuits LC and LC2. The outputs of the latch circuits LC and LC2 are input to an AND gate 222, and a test signal T is derived as an output of the AND gate 222.

Next, the write amplifier 30 will be explained with reference to FIG. The write amplifier 30 has a test mode switching circuit 330.
, a normal data write voltage generation circuit 340 , and a test mode write voltage generation circuit 350 . Test mode switching circuit 330 connects inverter 301. N channel M
OS) transistor (hereinafter referred to as NMOS>302.P channel MOS transistor (hereinafter referred to as PMOS) 30
3 and inverter 304. PMO8305゜NM
Two changeover switches for IWD signals each consisting of a set of OS 306, and an inverter 307°NMOS 308.
PMO8309 set and inverter 310. PMO8
It is composed of a total of four changeover switches, two changeover switches for IWD signals each consisting of a set of NMOS 311 and NMOS 312. The test signal T is manually applied to the gate of the changeover switch, and depending on the changeover, the IWD signal and IW
The D signal is input to normal mode write voltage generation circuit 340 or test mode write voltage generation circuit 350.

The normal mode write voltage generation circuit 340 is an NMOS 313
, NMOS314, NMOS315, and NMOS316, and the IWD signal is input to the gate of NMO8, and a write voltage to the memory cell MC is generated on the data input/output line pair 110°Ilo. The test mode write voltage generation circuit 350 includes an NMOS 317 and an NMOS
318 and NMOS319 and NMOS 320 and NMOS
322 and NMOS324 and PMO8321 and PMOS
323, high resistance 325, and high resistance 326,
IWD signal and the IWD signal are input to the gates of NMO3317-320, and the write voltage to memory cell MC is applied to data input/output line pair I10. Occurs at I10.

FIG. 4 is a timing chart for explaining the operation of the timing detection circuit 20 shown in FIGS. 1 and 2. The operation of an embodiment of the present invention will be described below with reference to FIGS. 2 to 4.

When the power is turned on, one pair of inverters 208 and 209 of the timing detection circuit 20 and another pair of inverters 21
The outputs of the latch circuits LC and LC2 composed of the latch circuits LC and 211 are set to the "L" level. Therefore, the output of the AND gate 222 (test signal T) is at the "L" level in the normal operating state.

From this state, when the RAS signal falls, the CAS signal and W
When the signal goes to L" level, the mode shifts to the test mode. That is, as shown in FIG. A pulse is applied to one input terminal of the 3-power AND gate 203. At this time, if the CAS signal and the W signal are at "L" level, each signal is inverted by the inverters 201 and 202 and the 3
Human power AND game 1203 is opened. As a result, the one-shot pulse causes NMOS 206 and 207 to conduct.

II due to conduction of NMOS206.207
The CAS signal and the W signal, which have fallen to the "L" level, are applied to latch circuits LC and LC2, respectively, which are composed of inverters 208 and 209 and 210 and 211. As a result, the output of each latch circuit LC and LC2 is The signal is inverted and "H" level is applied to both of the AND gates 222. Therefore, the test signal T which is the output of the AND gate 222 becomes "H" level and enters the test state. After that, the RAS signal, CAS signal and W The signal timing conditions are normal conditions, and if the above conditions are not met, NMO
Since S206゜207 is not conductive, the latch circuit LC1
°LC2 is not inverted and the test state is maintained.

When the test signal T becomes 'H' level, the inverter 304 of the test mode switching circuit 330 shown in FIG.
The two changeover switches consisting of the set of PMO3305 and NMOS306 and the set of inverter 310, PMO8311 and NMOS312 become conductive, and the IWD
The test mode write voltage generation circuit 35
given to 0. Depending on the input data, one of the IWD signals is at the 'H' level and the other is at the 'L' level. For example, when the IWD signal is “H# level,”
When the D signal is “L” level, NMO8317εNMO
8320 becomes conductive and the threshold voltage of the 4MO8321 and NMOS324 whose drains and gate electrodes are connected is α(>0), the data input/output line pair I10.
I10 has a potential of vcc-α and +α, respectively. On the other hand, IWD No. 18 is “L@level” and IWD signal is “H”
level, data input/output line pair I10. I10 has a potential of +α and vcc-α, respectively. in any case
v in normal mode as fin” level and “L” level
cc", the potential of Vcc-"++a is applied to the data input/output line pair I10. Bit line BL connected to I10
, BL to the designated memory cell MC.

Note that during normal operation when the test signal T is at the 'L' level, IWD and the IWD signal are transferred to the NMO 33 of the normal mode write voltage generation circuit 340 via the test mode switching circuit 330.
13 to 316 gates, and data input/output line pair I
10. V on one side of I10. A potential of 0 is applied to the other, and a potential of Ov is applied to the other.

Here, consider changes in the potential appearing on each bit line pair BL, BL when data is read from the memory cell MC in the test mode. The stray capacitance of each bit line BL, BL is C1, and the cell capacitance of the memory cell MC and dummy cell DC (see figure '!J12) is Cs. The charge accumulated in the memory cell MC becomes C8 (vcc-α) when data of 1H" level is stored, and becomes "
When L'' level data is stored, it becomes C8α. Also, the charge of C8vl cc/2 is stored in the dummy cells DC and DC.Bit line pair BL.

BL is set to V before the read operation. . /2, the charge on each bit line BL, BL is CBvcc/2.
It becomes 2. For example, data is read from the memory cell MC' onto the bit line BL, and the dummy cell DC1 is read onto the bit line BL.
Considering that when the potential from the bit line BL,
The potentials v and - of BL are determined by the following equations.

BL BL Cv /2+C when memory cell MC' is at 'H' level
8(vcc-α) C0 - (CB+C3)VB and Cv /2+C3vcc/2 B CC -(c +c)v100S Cv when memory cell MC' is at g L 11 level
/2+C8α CC ll1l (C10C3)vBL CV /2+C3vcc/2 CC -(CB+C3)v-anus and +I3...(4)...(5>...(8)...(7) This Therefore, the potential difference ΔvBL between the bit line pair BL is expressed by the following equation.

Expressions (8) and (9) are expressed as (3
When compared with the equations (8) and (9>), the read potential difference ΔV in the DRAM of this embodiment is smaller than the read potential difference ΔVBLL in the conventional DRAM.

As an example, in a normal memory cell MC, C:C
-10:1. Set to Vcc-5V. When this S, Cs −. , 1 CB+C8, so in equations (8) and (9>, C8,.”
O, ia (V) Cs + Cs If α-1(v) is the value of α, then 1ΔvBL””0.
25-0.1-0.15 (V), which is O.tV smaller than the conventional read potential difference of 0.25V. However, if the sensitivity of the sense amplifier 7a is set to 0.06 (V), the normal memory cell MC can be sufficiently sensed by the sense amplifier 7a.

On the other hand, in a memory cell MC with a small operating margin, the cell capacitor capacitance C is set to, for example, C(1/3).
Assuming C8, C8,a - (1,03a(V) CB+C8 Similarly to the above, the value of α is α-1(v)εS lever, I
ΔVBL+ -0,08-0,03-0,05(V)
Therefore, the sensitivity becomes lower than the sensitivity (0.08 V) of the sense amplifier 7a, and a defective memory cell can be detected. In other words, according to this embodiment, when a memory cell MC with a small operating margin is read, the successive potential difference tends to become less than the sensitivity of the sense amplifier 7a, so that there is an advantage that a defective memory cell MC can be easily detected. .

In addition, in FIG. 3, in the test mode write voltage generation circuit 350, PMO 3321, PMOS 323 and N
The threshold voltage vth of the four transistors MO8322 and NMO8324 was made equal, but the set of PMO8321 and PMOS 323 and the set of NMOS 322 and NMO
It is sufficient that the threshold values are the same in the 8324 sets, and the threshold value of either one of the sets may be Ov. Furthermore, instead of using the MOs 3321 to 324 whose gates and sources are connected, the NMOs 8317 to 320 may be high resistance transistors.

FIG. 5 is a schematic block diagram showing an embodiment of a semiconductor memory device according to the present invention. The embodiment shown in FIG. 5 changes the levels of the signals SE, SE output from the sense amplifier drive circuit 50 according to the timing conditions of the human input signal, and changes the write voltage to the memory cell MC from the above embodiment. Similarly to ε, this is set to an intermediate level in the normal mode.

Although the above-described embodiment shows the case where the write mode is used, this embodiment adopts a method of setting the write level to an intermediate level when refreshing the memory cell MC.

Figure 6 shows the sense amplifier drive circuit 50W4 shown in Figure 5.
It is a schematic diagram of the side. Hereinafter, other embodiments of the present invention will be described in detail with reference to FIG. The sense amplifier drive circuit 50 includes 8MO5401, NMO8405, and NMOS
406 and NMO3407 and NMOS408εPMO34
02, PMO8403, and PMO8404. N.M.
O3404 and NMO8405 are SE in response to signals φ8P and φ8N.

Connect the SE wire to the power supply side and the ground side. The test signal T output from the timing detection circuit 20 similar to that shown in FIG. 1 is given to the gate of the PMO 3403 (!1.
2 and the gate of NMOS 407, which switches between test mode and normal mode.

At the time of testing, the test signal T goes to "H" level, and the PMO 8402 and the NMOS 406 become conductive. NMO8401 and NMO8408 have their drains and gate electrodes connected, and have a threshold voltage V 2 . Therefore, the potential applied to the SE and SE lines during testing is (
Power supply voltage V - L threshold voltage V ) and CCth
The low potential side is (threshold voltage V), and these potentials are written into the memory cell MC through the sense amplifier 7a during refreshing. Therefore, as in the embodiment described above, when a memory cell MC with a small operating margin is read, the read potential difference tends to be less than the sensitivity of the sense amplifier 7a, so that defective memory cells can be easily detected.

Note that in the normal mode, the test signal T is at the "L" level, so the PMO 3403 and the NMOS 407 are in a conductive state. Therefore, the potentials applied to the SE and SE lines in the normal mode are (power supply voltage vco) on the high potential side and (Ov) on the low potential side.

In the above embodiment, the human input signals (CAS, RAS,
The timing detection circuit 20 generates the test signal T when the input signal (W signal) satisfies a predetermined timing condition different from normal timing, but when the input signal is at a voltage level different from normal timing, or when the input signal The test signal T
may be generated. An example thereof will be explained below.

FIG. 7 is a circuit diagram showing a high voltage detection circuit that detects that the CAS signal is at a higher voltage level than normal. In this high voltage detection circuit 6o, when the CAS signal is at a normal voltage level, the NMOSs 60f, 601, . . .
601 becomes non-conductive, and the potential of node 603 becomes "L" level due to the action of 1 2 n pull-down resistor 602. Therefore, the inverter 604,
605, the voltage detection signal S at the "L° level" is output. In the DRAM, the maximum value of the "H" level of the input signal is specified as 6.5V, but if the CAS signal exceeds this, Then, NMO8601, 601, -60
1n2 becomes conductive (for example, if the threshold of each NMO8601 is 0.5V and n-13, the total threshold is 0.5
X13 meals will be 6.5v. ), the potential of node 603 is “
H'' level. Therefore, inverters 604, 605
A voltage detection signal S at the 'H' level is outputted via the 'H' level voltage detection signal S.

This voltage detection signal S can be used as a test signal T.

Note that once the node 603 reaches the "H" level, the PMO 860
6 becomes conductive, so even if the CAS signal becomes the normal voltage level, the voltage detection signal S (test signal T) remains "H".
level is maintained. To release this, DRA
Turn off the power supplied to M and then turn off the power supplied to V. It is sufficient to reduce C to 0■. Note that a RAS signal or a W signal may be used instead of the CAS signal.

FIG. 8 is a block diagram showing a configuration for generating the test signal T using the RAS signal and the above-mentioned high voltage detection circuit 60. A signal obtained by inverting the RAS signal by an inverter 80 and a voltage detection signal S are input to an AND gate 90. When the RAS signal goes to the "L" level and the high voltage detection circuit 60 detects that the CAS signal is at a higher voltage level than normal, the AND gate 90 outputs the "H level" test signal T. Ru.

FIG. 9 is a block diagram showing a configuration for generating the test signal T using the timing detection circuit 20 and high voltage detection circuit 60 described above. The timing detection circuit 20 detects that the CAS signal and the W signal are at "L" level when the RAS signal falls, and the high voltage detection circuit 60 detects that the CAS signal is at a higher voltage level than normal. When this occurs, an "H" level test signal T is generated via the AND gate 70.

〔Effect of the invention〕

As described above, according to the present invention, there is provided a test mode detection means for detecting a test mode in response to a signal in a predetermined state different from that during normal operation being applied to an external terminal, and In response to the mode detecting means detecting the test mode, at least one of a relatively high first level written to the memory cell or a relatively low second level is set to a relatively low level written to the memory cell in the normal mode. Since the level is set to an intermediate level between the high third level and the relatively low fourth level, the potential difference between the bit line pair becomes small when data is read from the memory cell, making it possible to test memory cells with a small operating margin. The effect is that it can be done in a short time.

[Brief explanation of the drawing]

1 is a schematic block diagram showing a DRAM which is an embodiment of a semiconductor memory device according to the present invention, FIG. 2 is a circuit diagram of a timing detection circuit in FIG. 1, and FIG. 183 is a circuit diagram of a write amplifier in FIG. 1. 4 is a timing diagram for explaining the operation of the timing detection circuit, and FIG. 5 is a schematic diagram showing another embodiment of the semiconductor memory device according to the present invention.
FIG. 6 is a schematic diagram of the surroundings of the sense amplifier drive circuit in FIG. 5, FIGS. 7 to 9 are diagrams showing configuration examples for generating test signals, and FIG. 10 is a schematic diagram of a conventional DRAM. 11 is a block diagram showing a schematic configuration of the memory cell array portion in FIG. 10, and FIG. 12 is a diagram schematically showing a pair of bit lines in the memory cell array portion in FIG. 11. In the figure, MC is a memory cell, WL is a word line, and BL
, BL is a bit line pair, 20 is a timing detection circuit, 30
is a write amplifier, and 40 is a data input buffer. Note that the same symbols in each figure indicate the same or equivalent parts.

Claims (1)

[Claims] (1) In a semiconductor memory device including a memory cell consisting of one insulated gate field effect transistor and one capacitor, in response to a signal in a predetermined state different from that during normal operation being applied to an external terminal. test mode detection means for detecting a test mode, and in response to the test mode detection means detecting the test mode, a relatively high first level or a relatively low first level written to the memory cell; A semiconductor memory device characterized in that at least one of the two levels is set to an intermediate level between a relatively high third level and a relatively low fourth level written in a normal mode.