JPH03143116A - Phase locked loop circuit and digital signal processor - Google Patents

Abstract

PURPOSE:To form a phase locked loop circuit operated always stably by selected the time width of a 1st pulse signal to be a half of one period of the output signal of a voltage controlled oscillator in a phase locked loop circuit having the voltage controlled oscillator, a phase comparator and a filter. CONSTITUTION:An output signal Tc goes to an H level at the rise of an input pulse signal 100 and goes to an L level at the fall of an inverting output signal 300 coming succeedingly. Simultaneously a TS signal goes to H in this timing and the output signal Tc goes to an L level at the rise of an output signal 200 coming succeedingly. When a phase comparator 21 is operated in such a manner, the pulse width of signals TS, TD is a half the output signal period independently of the duty of the output signal 200 and the inverting output signal 300. Thus, the output current characteristic of a smooting filter 12 with respect to the phase difference between the input pulse signal 100 and the output signal 200 is stable independently of the duty of the output signal of the voltage controlled oscillator 14.

Description

[Detailed description of the invention] [Industrial application fields] The present invention relates to a phase locked circuit.

[Prior art] As a conventional phase synchronization circuit, Japanese Patent Application Laid-Open No. 63-21771
The one described in Publication No. 9 is known.

The configuration of this phase locked circuit is shown in FIG.

As shown in the figure, the 1-phase synchronized circuit includes a phase comparator 1 which compares the phases of an input pulse signal and an output signal of a voltage controlled oscillator and detects a phase difference, a smoothing filter 12 which smoothes the output of the phase comparator, Loop filter 13 connected to this smoothing filter and voltage controlled oscillation controlled by the voltage generated by the loop filter! It is composed of I'ji14.

FIG. 14 shows a specific circuit configuration of the phase comparator 11.

FIG. 15 and FIG. 16 show operation timing charts of the phase comparator 11.

Fig. 15 is an operation timing chart when the duty of the output signal 200 of the voltage controlled oscillator]-4 is smaller than 50%, and Fig. 16 is an operation timing chart when the duty of the output signal 1200 is larger than 50%. be.

At the rising edge of the input pulse signal 100, the Tc signal becomes uH'', and at the next falling edge of the output signal 200, it becomes II L II.
The signal becomes s-times "Jl" and becomes 'L' at the rising edge of the primary output signal 200. At the same time, at this edge, T
The n signal becomes (IH") and becomes IIL" at the next falling edge of the output signal 200.

Here, the difference between the pulse width of the Tc signal and the TD double signal pulse width is the phase difference between the input pulse signal 100 and the binding force signal 200.

The smoothing filter 12 converts this phase difference into a voltage, 'r
5 and outputs a current proportional to this voltage to the loop filter 13. FIG. 17 shows the output characteristics of this smoothing filter 12.

The loop filter 13 is composed of a resistor RP and a capacitor ff1cp. Of course, loop filters with other configurations may be used. The current output from the smoothing filter 12 is converted into a voltage by the loop filter 13, which controls the voltage controlled oscillator 14 and changes the frequency of its output (57chin 200).By operating the phase locked circuit in this way, The phase of the output signal 200 can be made to match the phase of the input pulse signal 100.

[Problems to be Solved by the Invention] The phase comparator circuit according to the prior art can output a DCffi current proportional to the phase difference, and can obtain a stable output signal in a synchronous state.

However, there is a problem in that the characteristics of the smoothing filter vary depending on the duty of the output signal 200 of the voltage controlled oscillator 14, such as the smoothing filter characteristics shown above (FIG. 17).

That is, the characteristics of the smoothing filter 12 are expressed by the following 2 equations (%) where GQ is the sampling servo gain and influences the transient characteristics of the smoothing filter, TI is the pulse width of the output signal 200, and gm is the transistor M1 and the resistor Ri ', C1 is the capacitance for the integrating circuit.

Ic is the train current of the transistor M2, which becomes the output current of the smoothing filter. ΔΦ is the input pulse signal 10
0 and the output signal 200.

It is desirable that the sampling servo gain GQ is 1, and if it is 2 or more, oscillation occurs.

Output signal @・200 pulse width T. If it varies.

The sampling servo gain GQ also changes proportionally.

Also, the output current I. As shown in FIG. 17, the linear range and slope vary. As the linear range changes, the capture range of the phase-locked circuit decreases, and as the slope changes, the loop gain of the phase-locked circuit changes.

An object of the present invention is to provide a phase-locked circuit that always operates stably, regardless of the pulse width of the output signal of the phase-locked circuit.

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a voltage controlled oscillator that outputs an output signal with a frequency corresponding to a control voltage, a first pulse signal, and a first pulse signal. a phase comparator that outputs a second pulse signal having a time width that is the time width plus a time width corresponding to a phase difference between the synchronized signal and the voltage-controlled oscillator output signal;

An integrating circuit is provided which receives the output of the phase comparator, performs a charging operation during a second pulse signal period, and performs a discharging operation during a first pulse signal period, and controls the control voltage value of the voltage controlled oscillator based on the output voltage of the integrating circuit. a smoothing filter that determines the phase-locked circuit, the phase-locked circuit comprising means for setting the time width of the first pulse signal to half the time width of one period of the voltage-controlled oscillator output signal. A phase-locked circuit is first provided.

In addition, in order to achieve the above object, a voltage controlled oscillator that outputs an output signal of a frequency according to a control voltage, a first pulse signal, a synchronized signal and a phase locked circuit output in the time width of the first pulse signal. a phase comparator that outputs a second pulse signal with a time width added to the time width according to the phase difference between the phase comparator and the phase comparator; a smoothing filter comprising: an integrating circuit that performs a discharge operation for one pulse signal period; a means for sampling and holding the output voltage of the integrating circuit; and a means for outputting a current according to the voltage held by the sample-holding means; A phase synchronized circuit has a loop filter that outputs the control voltage of the voltage controlled oscillator from the output current of the filter, and the time width of the first pulse No. A second aspect of the present invention provides a phase-locked circuit characterized by comprising means for halving the time width.

In order to achieve the above object, the present invention also provides a voltage controlled oscillator that outputs a normal phase signal and a negative phase signal having a frequency corresponding to a control voltage, a synchronized signal, and the positive phase signal and the negative phase signal. A first pulse signal having a time width of half of one period of the voltage controlled oscillator output from the edges in the same direction, and a synchronized signal and the positive phase signal or the negative phase signal in the time width of the first pulse signal. a phase comparator that outputs a second pulse signal having a time width added to the time width according to the phase difference between the phase comparator and the phase comparator; A third aspect of the present invention provides a phase locked circuit comprising: an integrating circuit that performs a discharging operation for one pulse signal period; and a smoothing filter that determines a control voltage value of a voltage controlled oscillator based on the output voltage of the integrating circuit. provide.

The present invention also provides a voltage controlled oscillator that outputs an output No. 4g with a frequency corresponding to a control voltage, a means for adjusting the duty of the voltage controlled oscillator output signal to 50%, and a voltage controlled oscillator using the adjusted voltage controlled oscillator output signal. RS1 pulse signal with a time width of half of one period of the oscillator output signal, and the time width of the first pulse signal plus the time width corresponding to the phase difference between the synchronized signal and the voltage-controlled oscillator output signal. a phase comparator that outputs a second pulse No. 44 having a width of 44; and an integrating circuit that receives the output of the phase comparator, performs a charging operation during the second pulse signal period, and performs a discharging operation during the first pulse signal period. , a smoothing filter that determines the control voltage value of the voltage controlled oscillator based on the output voltage of the integrating circuit;

In addition, the present invention also provides a voltage controlled oscillator that outputs an output signal with a frequency corresponding to a control voltage, a first pulse signal, and a synchronized signal and a voltage controlled oscillator output in the time width of the first pulse signal. a phase comparator that outputs a second pulse signal with a time width added to the time width according to the phase difference between the phase comparator and the phase comparator;
A smoothing filter comprising an integrating circuit that performs a charging operation on a variable capacitance capacitor and a discharging operation during a first pulse signal period, and that determines a control voltage value of a voltage controlled oscillator based on an output voltage of the integrating circuit.

Fifth, a phase-locked circuit having the following is provided.

Furthermore, a one-chip LSI characterized by having the phase synchronization circuit described above is provided.

Further, a fifth aspect of the present invention provides a digital signal processing device comprising the phase synchronized circuit or the one-chip LSI.

[Function] According to the first phase-locked circuit according to the present invention, the smoothing filter receives the first pulse signal having a time width half the period of the voltage-controlled oscillator output signal from the phase comparator, and the first A second pulse signal having a time width obtained by adding a time width corresponding to the phase difference between the synchronized signal and the phase-locked circuit output signal to the time width of the pulse signal is received, and an integrator circuit calculates the second pulse signal period. A charging operation is performed, a discharging operation is performed during the first pulse signal period, and the control voltage value of the voltage controlled oscillator is determined based on the output voltage of the integrating circuit.

Further, according to the first phase-locked circuit according to the present invention, the smoothing filter receives the first pulse signal having a time width of half of one period of the voltage-controlled oscillator output signal from the phase comparator, and the first pulse signal from the phase comparator. A second pulse signal having a time width obtained by adding a time width corresponding to the phase difference between the synchronized signal and the phase-locked circuit output signal to the time width of the signal is received, and the integrating circuit performs a charging operation for the second pulse signal period. and performs a discharging operation during the first pulse signal period, samples and holds the output voltage of the integrating circuit, and outputs a current according to the voltage held by the sample and hold means.

Further, according to the third phase locked circuit according to the present invention, the voltage controlled oscillator outputs the normal phase signal and the negative phase signal having frequencies according to the control voltage, and the phase comparator outputs the synchronized signal and the negative phase signal. A first pulse signal having a time width of half of one period of the voltage controlled oscillator output signal and a first pulse signal having a time width of half of one cycle of the voltage controlled oscillator output signal are generated from the edges in the same direction of the positive phase (i) signal and the negative phase signal. A second pulse signal having a time width obtained by adding a time width corresponding to a phase difference between the synchronization signal and the normal phase signal or the negative phase signal is output.

Further, according to the fourth phase-locked circuit according to the present invention, the output signal of the voltage controlled oscillator has its duty adjusted to 50%, and then the phase comparator outputs the voltage from the adjusted voltage controlled oscillator output signal. Controlled oscillator output (a first pulse signal with a time width of half of one cycle of No. A second pulse signal having the added time width is output.

Further, according to the fifth phase-locked circuit according to the present invention, the capacitance of the variable capacitance capacitor included in the integrating circuit of the smoothing filter is adjusted as appropriate so that the transient characteristics of the smoothing filter have a desired value. be done.

Further, the etip LSI outputs a clock whose phase is synchronized with the input signal by the phase synchronization circuit. Alternatively, the output of the built-in phase synchronized circuit (i) is used as a clock to process digital 43 seconds.

Further, the digital signal processing device according to the present invention processes a digital signal using the output signal of the phase synchronized circuit or the one-chip LSI as a clock.

(Left below) [Embodiment 1] A first embodiment of the phase-locked circuit according to the present invention will be described below.

FIG. 1 also shows the configuration of the phase locked circuit according to this embodiment.

The phase synchronized circuit has an input pulse signal 100 and an output signal 20.
A phase comparator 21 that detects the phase difference between the 0 and negative phase output signals 300, and the output signals Tc, T, , T of the phase comparator 21
A smoothing filter 12 that smoothes D, a loop filter 13 that converts the output of the smoothing filter 12 into voltage and determines the characteristics of the phase locked circuit, and changes the frequency of the output signal 200 and the negative phase output signal 300 depending on the output voltage of the loop filter 13. It is comprised of a voltage controlled oscillator 14 that causes

Although the loop filter 13 is composed of a resistor R1 and a capacitor CF, it is of course possible to use a loop filter having another configuration.

FIG. 11 shows the configuration of the voltage controlled oscillator of this phase locked circuit.

Voltage controlled oscillator 14 includes current source transistor Q5. Q6
．． Q7. Q8. Switching transistor Q3. Q4
, emitter follower transistor Ql, Q2, load resistance Zv, diode Di.

D2, level shift circuits 16 and 17, and timing capacitor C0, output signal 2 is controlled by control voltage Vcont.
00, the frequency of the negative phase output signal 300 changes.

Due to the symmetry of the circuit configuration, this voltage control circuit has an output signal of 200 and a negative phase output signal of 3 as shown in FIG.
Even if the duty of 00 changes, the time from the rising edge of the output signal 200 to the rising edge of the negative phase output signal 300 is half of one cycle of the output signal 200. Of course, when looking at falling edges, it is also half of one cycle.

Next, the configuration of the phase comparator 21 is shown in FIG.

The phase comparator is a D type flip-flop 701.70
2,703 and 704 and NAND gates 705 and 7
06 and inverter gates 707, 708, 709 and 7
10 and AND gate doors 11, 71.2 and 713, the input signals Z are the input pulse signal 100, the output signal 200 of the voltage controlled oscillator and the negative phase output signal 300, and the output signals are Tc, Ts and TD. .

FIG. 3 shows a timing chart of the operation of the phase comparator 21.

First, at the rising edge of the input pulse signal 100, T
The c4R signal becomes 11 T (TI) and becomes II L II at the next rising edge of the negative phase output signal 300.

At the same time, at this timing T s (g is (l HII
Then, at the next rising edge of the output signal 200, it becomes sr L". Further, at this timing, the TD double signal becomes 'H', and at the next rising edge of the negative phase output signal 300, it becomes lJ L II.

When the phase comparator operates in this manner, the T, 1C8- and TD times signal pulse widths become half of the period of the output signal 200 and the negative phase output signal 300, regardless of their duty.

Therefore, the output current characteristics of the smoothing filter 12 with respect to the phase difference between the input pulse signal 100 and the output signal 200 are stable regardless of the duty of the output signal of the voltage controlled oscillator 14 (see the beginning of the smoothing filter characteristics in FIG. 4).

In addition, the transient characteristics of the smoothing filter 12 are determined by the voltage controlled oscillator 1.
It can be made constant regardless of the duty of the output signal of No. 4.

Next, a second embodiment of the phase locked circuit according to the present invention will be described.

FIG. 5 shows the configuration of a phase locked circuit according to a second embodiment.

The phase locked circuit according to this embodiment includes a phase comparator 1, a smoothing filter 12, a loop filter 13, and a voltage controlled oscillator 14.
．． and a duty adjustment circuit 15.

The phase comparator 11 compares the phases of the input pulse signal 100 and the output clock 220 of the duty adjustment circuit 15, and outputs the phase difference as Tc, TS, and TD multiplied signals. Smoothing filter 12, loop filter 13, voltage controlled oscillator 14
The operation is similar to that shown in FIG. The duty adjustment circuit 15 corrects the duty of the output signal 200 of the voltage controlled oscillator 14 to 50%, and outputs the output clock 200.
Output as 20.

FIG. 6 shows the configuration of this duty adjustment circuit 15.

In the figure, the differential comparator 18 compares the output signal 200 of the voltage controlled oscillator 14 and the reference voltage Vvef, and if the output signal 200 is higher in voltage than the reference voltage Vvef, the output clock 220 is On the other hand, if the output signal 200 is lower in voltage than the reference voltage V vef, the output clock 220 is set to Low -Lev.
Make it el.

FIG. 8 shows this duty FA'! The operation of the Ii circuit 15 is shown in a timing chart.

As shown in FIG. 8, even if the duty of the output signal 200 is not exactly 50%, if there is a certain deviation, the duty can be reduced to 50% by adjusting the reference voltage V vef.
An output clock 220 can be obtained.

FIG. 7 shows another configuration of the duty adjustment circuit 15.

In this configuration, a mono multivibrator 19 is used as a duty adjustment circuit, and the time constant composed of a capacitor C8 and a resistor R8 is adjusted to obtain the pulse width T necessary for triggering the output signal 200. , pulse @T is set to be half the period of the output signal 200.

As a result, as shown in the operation timing chart shown in FIG. 9, an output clock 220 with a duty of 50% can be obtained for the output signal 200 with a duty of not 50%. Therefore, the output current characteristics of the smoothing filter 12 can be made stable regardless of the duty of the output signal of the voltage controlled oscillator 14. In addition, the smoothing filter 12
The transient characteristics of can be made constant regardless of the duty of the output signal of the voltage controlled oscillator 14.

Next, a third embodiment of the phase locked circuit according to the present invention will be described.

In this embodiment, the smoothing filter 12 corrects fluctuations in the transient characteristics of the smoothing filter 12 due to the duty of the output signal 200 of the voltage controlled oscillator 14. Therefore, the phase comparator 11. Loop filter 13. Voltage controlled oscillator 1-
4 operates in the same manner as the conventional phase locked circuit described above (see FIG. 13). Furthermore, the overall configuration of the phase locked circuit is the same as the conventional one. However, the internal configuration of the smoothing filter 12 is different.

FIG. 10 shows the configuration of the smoothing filter (2) of the 4'0 synchronous circuit according to this embodiment.

As shown in FIG. 10, the smoothing filter 12 is connected to a current source 1
, invert logic circuit 801, 802° 803, INV
I, MOS transistor M21M3. M4. , M5. ,
M6. M7. M8. M9゜MIO, Ml 1. Ml2.
Ml3. Ml4°Ml, 5. Ml6, resistance R,, R2,
Capacity C0□, C work 2゜C1, switch S work +S2+...
- Consists of S7 and capacitor CS.

This circuit extracts charges from the capacitors 011 to CLfl when a signal operating on the basis of the current 1 is inputted, and injects charges when the T゜ signal is input. T, when the signal is input M
The voltage of the capacitor Cs is M 1-4 when l3 is turned on and charge is stored in the capacitor fC5.

The current ■ in the differential amplifier consisting of Ml5. The current generated from the source ■□. Difference with I. is output to Loop Gale Tae 3.

Here, as shown in equation (1), the sampling servo gain GQ of the smoothing filter 12 is a function of TD and C, so the duty of the output signal 200 is not 50%,
When Tn changes, the total capacitance C□ is changed by closing an appropriate number of switches S□ to 81.
Correct the variation in T o. As a result, GQ can be kept constant regardless of the duty of the output signal of the voltage controlled oscillator 14.

As described above, according to the first and second embodiments, in the phase locked circuit, the signal TD input to the smoothing filter is inputted to the voltage controlled oscillator 14 regardless of the duty of output No. 3 of the voltage controlled oscillator 114. It can be a pulse signal with a time width that is half the period of the output signal, and therefore GQ can be kept constant, so the transient characteristics of the smoothing filter can be kept constant, and the output current of the smoothing filter can be kept constant. It is possible to keep the characteristics constant.

Further, according to the third embodiment, TD affecting GR
By correcting the variation, GQ can be kept constant regardless of the duty of the output signal of the voltage controlled oscillator 14, and therefore the transient characteristics of the smoothing filter can be kept constant.

Further, according to one or more embodiments, the sampling servo gain GC of the smoothing filter 2 can always be 1 regardless of the duty of the output signal 200 of the voltage controlled oscillator 14, and the linear phase comparison range can also be set to the leading side. The ranges on the delay side are made equal, and a decrease in the capture range can be suppressed.

Furthermore, the loop gain of the phase-locked circuit does not vary and remains constant, resulting in a stable output signal from the voltage controlled oscillator. Due to the above effects, when applied to a magnetic disk device, for example, it is possible to realize a reduction in data reproduction margin loss.

Furthermore, since the phase synchronized circuit according to this embodiment mainly achieves its functions through digital signal processing, it can be easily incorporated into an LSI.

Furthermore, by including the phase synchronized circuit according to this embodiment, the digital signal processing device can process digital signals using a stable clock.

[Effects of the Invention] As described above, according to the present invention, it is possible to provide a phase-locked circuit that always operates stably without depending on the pulse 1INTD of the output signal 200.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a phase locked circuit according to the first embodiment of the present invention, FIG. 2 is a circuit diagram showing the configuration of a phase comparator, and FIG. 3 is a timing diagram showing the operation of the phase comparator. 4 is a characteristic diagram showing the characteristics of the smoothing filter, FIG. 5 is a block diagram showing the configuration of the phase synchronization circuit according to the second embodiment, FIG. 6 is a circuit diagram showing the configuration of the duty adjustment circuit, Fig. 7 is a circuit diagram showing another configuration of the duty adjustment circuit, Fig. 8 is a timing chart showing the operation of the duty adjustment circuit, Fig. 9 is a timing chart showing the operation of another duty adjustment circuit, and Fig. 10 is a timing chart showing the operation of the duty adjustment circuit. A circuit diagram showing the configuration of the smoothing filter according to the third embodiment, FIG. 11 is a circuit diagram showing the configuration of the power generation control oscillator, FIG. 12 is a timing chart showing the operation of the power generation control oscillator, and FIG. 13 is a circuit diagram showing the configuration of the power generation control oscillator. FIG. 14 is a block diagram showing the configuration of a phase synchronization circuit according to the prior art; FIG. 14 is a circuit diagram showing the configuration of the phase comparison circuit; FIGS. 15 and 16 are timing charts showing the operation of the phase comparison circuit; FIG. is the characteristic diagram showing the characteristics of the smoothing circuit, the first
FIG. 8 is a block diagram showing the structure of the smoothing filter. 21... Phase comparator, 12... Smoothing filter, 13
...Loop filter, 14...Voltage controlled oscillator, 1
5... Duty adjustment circuit, 100... Input pulse signal, 200... Output signal, 300... Phase output signal.

Claims (1)

[Claims] 1. A voltage controlled oscillator that outputs an output signal with a frequency corresponding to a control voltage, a first pulse signal, and a synchronized signal and a voltage controlled oscillator output signal in the time width of the first pulse signal. a phase comparator that outputs a second pulse signal with a time width added to the time width according to the phase difference between the phase comparator and the first pulse signal; A phase-locked circuit comprising: an integrating circuit that performs a discharging operation for a pulse signal period of A phase synchronized circuit comprising means for setting a time width to half of one period of a voltage controlled oscillator output signal. 2. A voltage controlled oscillator that outputs an output signal with a frequency corresponding to a control voltage, a first pulse signal, and a time width of the first pulse signal according to the phase difference between the synchronized signal and the phase locked circuit output signal. a phase comparator that outputs a second pulse signal with a time width added to the time width of the phase comparator; a smoothing filter equipped with an integrating circuit that performs the following, a means for sampling and holding the output voltage of the integrating circuit, a means for outputting a current according to the voltage held by the sample-holding means, and a voltage control based on the output current of the smoothing filter. a loop filter that outputs a control voltage of an oscillator; and a phase-locked circuit comprising means for setting the time width of the first pulse signal to half the time width of one cycle of the voltage-controlled oscillator output signal. A phase-locked circuit characterized by: 3. A voltage controlled oscillator that outputs a positive phase signal and a negative phase signal having frequencies according to the control voltage, and a voltage controlled oscillator output signal from the synchronized signal and edges in the same direction of the positive phase signal and the negative phase signal. a first pulse signal having a time width half of one period of a phase comparator that outputs a second pulse signal with a time width; and an integration circuit that receives the output of the phase comparator, performs a charging operation during the second pulse signal period, and performs a discharging operation during the first pulse signal period. , a smoothing filter that determines the control voltage value of the voltage controlled oscillator based on the output voltage of the integrating circuit. 4. A voltage controlled oscillator that outputs an output signal with a frequency according to the control voltage, means for adjusting the duty of the voltage controlled oscillator output signal to 50%, and 1 of the voltage controlled oscillator output signal from the adjusted voltage controlled oscillator output signal. A first pulse signal with a time width that is half the period, and a second pulse signal with a time width that is the time width of the first pulse signal plus a time width that corresponds to the phase difference between the synchronized signal and the voltage controlled oscillator output signal. a phase comparator that outputs a pulse signal; and an integrating circuit that receives the output of the phase comparator and performs a charging operation during a second pulse signal period and a discharging operation during a first pulse signal period, and the output voltage of the integrating circuit is A phase locked circuit comprising: a smoothing filter that determines a control voltage value of a voltage controlled oscillator based on; 5. A voltage controlled oscillator that outputs an output signal with a frequency corresponding to a control voltage, a first pulse signal, and a time width of the first pulse signal that corresponds to the phase difference between the synchronized signal and the output signal of the voltage controlled oscillator. a phase comparator that outputs a second pulse signal with a time width added to the time width of the phase comparator;
an integrating circuit that performs a charging operation on a variable capacitance capacitor and a discharging operation during a first pulse signal period, and a smoothing filter that determines a control voltage value of the voltage controlled oscillator based on the output voltage of the integrating circuit. Phase-locked circuit. 6. A one-chip LSI comprising the phase locked circuit according to claim 1, 2, 3, 4 or 5. 7. A digital signal processing device comprising the phase synchronized circuit according to claim 1, 2, 3, 4 or 5, or the 1-chip LSI according to claim 7.