JPH03142790A - Differential amplifier and non-volatile storage equipped with the same - Google Patents

Abstract

PURPOSE:To obtain a high-speed sense circuit for non-volatile memory by providing a signal receiving means to operate a first resistor as a pull-down resistor when a control signal is in a first state and to operate a second resistor as the pull-down resistor when the signal is in the second state. CONSTITUTION:Two cell arrays CA1 and CA2 are provided and when a bit line is selected by one cell array, one correspondent bit line is selected by the other cell array as well. Then, the differential potential of these bit lines is amplified. When the cell array CA2 is not selected, a transistor Q42 is turned ON and a resistor R2 is defined as the pull-down resistor. When the cell array CA1 is not selected, a transistor Q41 is turned ON and a resistor R1 is defined as the pull-down resistor. In such a way, a differential amplifier AMP calculates the H and L bit potentials of the selected cell array with the potential of the bit line in the pulled-down not selected cell array as a reference and can amplify the differential voltage. Thus, a weak voltage such as 0.05V can be defined as the differential voltage and a high-speed processing can be executed.

Description

[Detailed Description of the Invention] [Summary of the Invention] An object of the present invention is to provide a high-speed sense circuit for a nonvolatile memory, regarding a differential amplifier and a nonvolatile memory device equipped with the differential amplifier. A differential amplifier having an input terminal and amplifying a voltage difference between a potential applied to a first input terminal and a potential applied to a second input terminal, the differential amplifier being connected to the first and second input terminals, respectively. a pull-up resistor, first and second resistive elements respectively connected to the first and second input terminals, and receiving a control signal;
A configuration comprising: a signal receiving means for causing the first resistance element to act as a pull-down resistance when the signal is in a first state, and causing the second resistance element to act as a pull-down resistance when the signal is in a second state. shall be.

[Industrial application field]

The present invention relates to a differential amplifier and a nonvolatile memory device equipped with the differential amplifier.

Non-volatile memory retains stored information even when the power is turned off, so it is often used to store programs and data for storage. However, although microprocessors and their peripheral devices have become faster in recent years, the speed of nonvolatile memories has not progressed much. Therefore, there are some cases in which static RAM, which is becoming faster and faster, is used as non-volatile memory by backing up the power supply.

However, non-volatile memories such as EFROM and mask ROM are becoming larger in capacity than static RAM, so it is absolutely necessary to increase the speed of these non-volatile memories.

[Conventional technology]

In a nonvolatile memory, stored information is determined based on whether a current flows through a memory cell or not. Therefore, a current-voltage conversion circuit is used in a sense amplifier that performs this determination. The simplest current-to-voltage conversion circuit is one in which the current to be sensed is passed through a resistor and the potential difference produced across the resistor is detected. Figure 8 shows the outline. WL17WL, beam 1d line, BL.

is the bit line, Q17Q is the EFROM memory cell, Q
c is a column gate, R is a resistor, and output Out is R.

and BL+(Qc). The memory cell Q17Q is of the type with a control gate and a floating gate, stores data I10 with/without charging the floating gate, and allows current to flow when selected with/without charging. It will not flow.

When word lines WL are selectively set to H level by a row decoder and word driver (not shown), and bit lines BL are selected by turning on a column gate Qc by the output of a column decoder (not shown), these word lines WL , and the bit line BL.

The memory cell Q+ at the intersection of is selected, and if it is on, R
Qc Current flows through the Q+-ground path and the output terminal O
If the potential of ut decreases and Q is off, the current will not flow and the potential of the output terminal Out remains unchanged (it remains at the power supply voltage), so that the data stored in memory cell Q is either l or O.
It is determined whether In the EFROM, when the output terminal potential is H, the stored data is O, and when the output terminal potential is L, the stored data is 1.

The same applies to other memory cells. Of course, a memory has many word lines, bit lines, and memory cells, only some of which are shown in FIG.

[Problem to be solved by the invention]

In this current-voltage conversion circuit, in order to increase the amplitude of the output Out, the value of the resistor R must be increased, and R is usually made larger than the on-resistance of the memory cell.

However, if the resistance R is made larger than the on-resistance of the cell, the output O
The L(0-)-'H (high) change of ut is slower than the H-L change. FIG. 10 shows this situation.

Since the L-H change is performed by charging through the resistor R,
A large resistance R slows down this change, which limits the access time.

Therefore, as shown by the dotted line in Figure 9, a transistor is connected in parallel to the resistor R, and this is turned on by the ATD pulse (pulse generated when the address changes), and the output terminal is temporarily turned on.
A method has been developed in which the voltage is forcibly set to H level, and then the selected cell is set to L or remains at H level. FIG. 11 shows the output terminal potential change in this method. Since the H-L change is performed by discharge from the selected cell, it is the same as in FIG. 10, but the L-H change is significantly faster.

However, as memories become more highly integrated, the current that can be passed through memory cells decreases, and the bit line capacitance increases. Therefore, the time required for the output terminal Out to change from HL to HL cannot be ignored. Even in a high-speed EPROM as shown in FIG. 11, the access time is about 100 ns, which is inferior to the 35 ns of a static RAM, or even 25 ns or 20 ns or less.

The present invention aims to improve the above points and provide a high-speed sense circuit for non-volatile memory.

The reason why static RAM is much faster than EFROM and the like is that its sense circuit differentially amplifies the potential difference between a pair of bit lines. The present invention focuses on this point and attempts to enable differential amplification even in nonvolatile memories.

[Means to solve the problem]

As shown in FIG. 1, in the present invention, a sense circuit of a nonvolatile memory is configured with a differential amplifier AMP.

This amplifier AMP has first and second input terminals T17T.

It amplifies and outputs the difference between the potentials applied to these input terminals.

This first. A circuit 10 including a pull-up resistor is connected to the second input terminal T17T, and a circuit 10 including a pull-up resistor is connected to the second input terminal T17T. Second resistance element R+, Rz
A transistor (signal receiving means) Q17 is connected in series to these resistance elements.

Q4□ is connected.

Transistor Q a + receives control signal A directly and transistor Q. receives the signal through an inverter and turns on/off, and when on, the resistive elements R,,R.

Let be the pull-down resistor.

In a non-volatile memory device, the input signal to the differential amplifier AMP is a current flowing through the selected bit line and memory cell. In FIG. 1, the memory device includes first and second memory cell arrays CAI and CAZ. WL+ and WLz are word lines of these cell arrays, BL+ and BLz are the same bit lines, and Q17Q is a memory cell. Although there are generally many of these, only one of each is shown in the figure. RD In RD z
A word line is selected by a row decoder, and a column decoder (not shown) is also provided, and these are column gates Qc+.

Turn Qo on/off.

[Effect]

As shown in Figure 1, EFROM has one bit line,
Since it does not use two lines BL and BL like static RAM, it is difficult to perform differential amplification, so two cell arrays CAB and CAt are provided, and when one bit line is selected in one cell array, the other cell array is However, one corresponding bit line is selected and the potential difference between these bit lines is amplified. However, since word line selection is performed only in one cell array, the bit line in the other cell array remains at the precharged H (high) level. Therefore, connect a pull-down resistor to the non-selected side,
A level intermediate between when the read data is 1 (L level) and when it is O (H level) is taken, and this is used as a reference level to detect 0°1 of the stored data. Resistance element R
1, R2,) transistors Qa+rQ4g are for this purpose and are in the cell array CA.

When is not selected, transistor Q. is turned on and resistor element Rt becomes a pull-down resistor, and when cell array CAI is not selected, transistor Qa+ is turned on and resistor element Q0
Let be the pull-down resistor.

In this way, the differential amplifier AMP can take HIL of the bit line potential of the selected cell array based on the pulled-down potential of the bit line of the unselected cell array, and amplify the difference voltage.

In the method of amplifying the differential voltage, the differential voltage (input voltage) is 0.
A very small voltage such as 0.5 V is required, and the sensitivity is extremely high compared to the conventional absolute value amplification type, which requires several volts.

Two memory cell arrays CA17CA! can be formed by dividing each bit line of one cell array into two at the center. In this case, the resistance and parasitic capacitance of the corresponding bit lines are equal, and it can be expected that the state of change in potential due to pull-up/pull-down is also equal, so that it is suitable as a reference voltage source.

The current path during memory reading is memory cell Q.

When reading out, pull amplifier circuit lO, column gate Qc
+, hit IBt, +, path of memory cell Q, pull-up circuit lO1 resistance element R2, transistor Q. The difference between the currents flowing through both paths becomes the input to the amplifier AMP. Therefore, it can be said to be a current comparison method.

Immediately before starting amplification, it is preferable to short-circuit the input terminals T t and T z to have the same potential, and to start changing the potential from this potential.

This is not shown, but the pulse (
This can be done by using the pulse (ATD) and turning on the shorting means (transistor) connected between the terminals T + and T z with the pulse.

〔Example〕

FIG. 2 shows an embodiment of the memory of the present invention. In this embodiment, the word line is also divided into two at the center, and four cell arrays CA+1
7CA+b, CA2□ CAtb. Row decoder RD17RD has cell arrays CA0 and CA+b,
The column gates and sense amplifiers are placed between the cell arrays CA, and CA z -, CA.
It is placed between Ib and CAtbO, and the column decoder is placed between these cell arrays (in the center). Address A
6. AI, At, ... are input to the address buffer, and A o, A + , A z , ...
...and its inversion A oar A + II A
Z ideas are created and sent to the row decoder and column decoder, where they are used to select word IWL and bit IBL. The output of the sense amplifier, ie, the data stored in the selected cell, is output to the outside through an output buffer. CE is a chip enable signal that enables/disables address buffers, sense amplifiers, etc. OE is an output enable signal.

FIG. 3 shows an embodiment of the sense amplifier. differential amplifier AM
P is composed of three stages of current mirrors CM-1 to CM-3.

The input ends of these current mirrors are provided with transistors Q, ~Q0, which short-circuit the input ends immediately before the start of operation. These transistors Q□~Q0 are p-channel transistors, and when the address changes, a negative pulse of a constant width is generated.
TD% is added and turned on.

In this example, the resistive elements Rt and Rz are n-channel depressing transistors Q 1 ff whose gates are connected to their sources.
, Q t 4. The pull-up resistor of the circuit lO is
It is composed of p-channel transistors Q Is and Q H6 whose gates are connected to the power supply low potential and are always on. Data bus D connected to bit line through column gate
B, DBs has an n-channel transistor Q It +Q
1. is inserted, and the voltage drop caused by this causes the data bus DB to
, the H level of DB$ is limited (for example, limited to about 2■ for a power supply of 5■; this is a means of increasing speed). A Q-th n-channel debris transistor Q17 whose gate is connected to the source is also connected to the data bus, and this is used to stabilize the potential of the data bus. A pair of data buses DB, DB%
An n-channel transistor Qzo is connected between them to short-circuit them. This is turned on/off by a pulse ATD having an opposite phase to ATD+.

A pull-up p-channel transistor Q z a +Q z s is also connected to the output terminal of the differential amplifier AMP, and is turned on/off with a pulse ATD*. Further, this output terminal is connected to a latch flip-flop FF via a multiplexer MPX.

Now, the address is 17 bits from A0 to A16, and the lower A0 to A are column addresses and the upper A7 to A16.
is the row address, and cell array CA17.

In CA + b, the low address A16 is O, CA, □
In CAo, if At6 is 1, the transistor Qar
Give At6 to and A0* to Qdt. With this, when the cell array CA17 in FIG. 2 is selected and CAo is not selected, it is possible to turn off the transistor Q□, turn on Qaz, and connect the pull-down resistor Q to the data bus DB% on the non-selected side. When cell array CAR, is selected and CA17 is selected, transistor Q4. is turned on, Qaz is turned off, and a pull-down resistor Q l is connected to the non-selected data bus DB.
3 can be connected.

Cell array CA t- and CA! , are given the same column address, and therefore, in these cell arrays, corresponding bit lines (there was only one before division) are selected at the same time. The same applies to cell arrays CA17 and CAtb. Cell array CA0 and CA + b, CA□ and CA z >
In this case, the corresponding word lines are selected at the same time, so that the sense amplifiers on both sides produce outputs at the same time.

In the circuit of FIG. 2, 4 bits are read simultaneously, and the output buffer outputs 8 bits simultaneously.

The resistance element Q + s r Q r < is 0. Since it provides an intermediate potential between H and L levels with respect to 1, it has a resistance greater than the on-resistance of the cell.

In FIG. 3, depending on whether the selected cell is on the DB or DB+ side, the H and L outputs of the differential amplifier are reversed for the same stored data. For example, if the H and L appear on the output end SA3 of the current mirror CM-3 when it is on the DB side, the H and L appear on the output end 5A3n side when it is on the DB side, and the H and L appear on the output end SA3 and SA3+ of the current mirror CM-3. In terms of which one is H, it is the opposite. Multiplexer MPX
To deal with this, control signals A, A (above A16
．． For example, when the DB side is selected, it is inverted, and when the DB* side is selected, it is inverted (SA3 and SA3+ are exchanged) and inputted to the flip-flop FF.

FIG. 4 shows an embodiment of the bias circuit 10a.

The Q-th gate of n-channel transistor Q17 has 2
Apply a bias voltage of about V. In addition, the pull amplifier circuit consists of n-channel transistors Q, Q3□, and Q.

and Qxa, and a pulse ATD is applied to the gates of these transistors to connect the input terminal S of the current mirror CM-1.
Pull up AO and SAO$ to about 3■. With this, the data buses DB and DB* are at an H level of about 1 V, allowing high-speed operation.

FIG. 5 shows an embodiment of the current mirror CM-1. Current mirrors CM-2 and CM-3 are also the same circuit. It consists of P-channel transistors Q a + ~Qa4, n-channel transistors Q4s ~ QSo, and complementary inputs IN,
Complementary output OUT in response to IN input.

Outputs OUT+. Transistors Q41 and Q4
z rQ43 and Qa4 are current mirrors, and serve as loads for the differential pairs Qas and Q4b, and Q4t and Qas. The gate voltage of transistors Q4& and Qa7 becomes the reference voltage, and the gate inputs IN and IN of transistors Q41Q41
* H2L for the reference voltage (this is INN, IN)
becomes the output OUT, OUT+. IN, IN of this circuit
N is SAO, SAO% of CM-1, SAI, SA1* of CM-2, SA2 of CM-3 in FIG. SA2%, OUT, OUT* are SAI of CM-1, SA1+, C
M-2 SA2. SA2*, SA3, 5A of CM-3
It is 31.

FIG. 6 shows a specific example of the multiplexer MPX and the RS flip-flop FF. The multiplexer is equipped with analog gates G, ~G4, which are connected in parallel with a P-channel transistor and an n-channel transistor, and outputs the output SA315Aa* of the current mirror CM-3 as the output Rs, Ss, or vice versa, Sn-, It shall be Rs. This switching is done by control signal A.

A+ (A r b in the above example, A + h'k
).

That is, if A=H, A%=L, gate G17G3 is on, A
=L and A=H, gates G t and G4 are on, and the above switching is performed.

Flip-flop FF is a P-channel transistor Q
s I-Q s s and n-channel transistor Q sb
~Q6°. This is a cross-connection of two two-man powered C0M5 inverters, Qs+, Qst and Q,
4 and Qst are one inverter, and Qsa, Qss, Qsq and Q20 are the other inverter. Transistors Qs3 and QSI constitute a C0M5 inverter serving as an output stage.

FIG. 7 shows the ATD (Address Transi
tion Det-ec2) shows a pulse generation circuit. This is a monostable multivibrator, C0M5 inverter 1+~■.

Consists of. The address buffer output ■ is the 7th E (
As shown in a), the output of inverter ■1 is this inversion,
The output of inverter I is also the inverse of that, so it is the same as (2). Inverters L and Is receive these and output ■
produces O. That is, at the beginning (before the rise of ■), since ■ is at H level, inverter I2 is active and immediately responds to the output of It, but since output ■ is initially at L level, inverter ■4 is inactive, and ■ becomes H. Become active for the first time. For this reason, the fall of the output O is delayed. When the output ■ falls, the opposite is true; the fall of ■ is delayed,
The falling edge of (2) occurs immediately. The NAND game (Is) receives these outputs ``O'' and generates an L-level pulse ATD% at the rise/fall of ``2'', that is, at the time of address change. The pulse width of ATD+ is determined so that the word line level is determined (at least in the non-selected state) during this pulse period.

FIG. 8 shows the waveforms of each part. Pulse ATD is H2ATD
When the voltage is low, DB, DB4, etc. are short-circuited and become at the same level as shown in the figure. With the disappearance of the ATD node, a potential difference due to the stored data of the selected cell begins to appear on the data buses DB and DBe, and the current mirrors 0M-1, 2. 3 starts amplification, and by the time there is a very slight potential difference between DB and DB*, the Q output of the flip-flop FF is determined.

In FIG. 8, the data bus DB side is selected and the DB* side is non-selected, and after the ATD pulse disappears, the data bus DB
* settles to the reference level determined by the resistor element, and the data bus DBI settles to the L level shown by the solid line if the cell storage data is 1, and to the H level shown by the dotted line if the stored data is 0.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to realize high-speed nonvolatile memory, and high-speed processing is possible without requiring waiting time when a high-speed processor makes an access.

This operational amplifier can also be used in other systems that require high speed.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of the principle of the present invention, Fig. 2 is an explanatory diagram of a memory according to an embodiment of the invention, Fig. 3 is a sense circuit diagram of the memory of Fig. 2, and Fig. 4 is a bias circuit of Fig. 3. Figure 5 is a circuit diagram of the current mirror in Figure 3, Figure 6 is a circuit diagram of the multiplexer and flip-flop in Figure 3, Figure 7 is a circuit diagram of the ATD pulse generation circuit, and Figure 8 is a circuit diagram of the ATD pulse generation circuit. Second
9 is a circuit diagram of a conventional sense circuit, FIG. 1O is an output waveform diagram of FIG. 9, and FIG. 11 is an output waveform diagram of an improved version of FIG. 9. In Figure 1, CA l+ CAx is a memory cell array, WL
is a word line, BL is a bit line, QclrQct is a column gate, AMP is a differential amplifier, lO is a circuit including a pull-up resistor, Rr and Rt are resistance elements, Qa + rQ a
z is a signal receiving means. Explanation of the principle of the present invention FIG. 2 Memory sense circuit diagram FIG. 3 A, A circuit diagram of the bias circuit in FIG. 3 Circuit diagram of MPX and FF Fig. 6 Circuit diagram of ATD pulse generation circuit Fig. 7

Claims (1)

[Claims] 1. A first input terminal (T_1) and a second input terminal (T_1)
2) and amplifies the difference voltage between a potential applied to a first input terminal and a potential applied to a second input terminal, the differential amplifier being connected to the first and second input terminals, respectively. the pull-up resistors (Q_1_5, Q_1_6) and the first
and a first and second resistive element (R_1, R_2) respectively connected to a second input terminal; and a resistor that receives a control signal and pulls down the first resistive element when the signal is in a first state. and signal receiving means (Q_d_1, Q_d_2) for causing the second resistance element to function as a pull-down resistor when the signal is in a second state. 2. The control signal input to the signal receiving means is given as a set of complementary signals (A, ■), the first state of the signal is one state of the set of complementary signals, and the second state is 2. The differential amplifier according to claim 1, wherein the differential amplifier is in a complementary state to the one state. 3. The first and second resistive elements are connected to the first and second series-connected n-channel transistors (Q
_1_7 and Q_1_3, Q_1_3 and Q_1_4), the drains of the first n-channel transistors (Q_1_7, Q_1_8) of the first and second resistance elements are connected to the first and second input terminals, respectively, and the gate is given a potential higher than the threshold voltage of the transistor and lower than the power supply voltage, the source is connected to the drain of the second n-channel transistor (Q_1_3, Q_1_4), and the gate of the second n-channel transistor is connected to the drain of the second n-channel transistor (Q_1_3, Q_1_4). The input signal receiving means is a third n-channel transistor (Q_d_1, Q_d_2), the drain of which is connected to the source of the second n-channel transistor, and the input signal receiving means is a depletion transistor connected to the source of the second n-channel transistor. One of the sets of complementary signals is input to the set of complementary signals, the source is grounded, and when one signal of the set of complementary signals is at H level and the other is at L level, the first resistor acts as a pull-down resistor, and the second resistor acts as a pull-down resistor. The element does not function as a pull-down resistor, and when the one signal is at L level and the other signal is at H level, the first resistor element does not function as a pull-down resistor, and the second resistor does not function as a pull-down resistor.
3. The differential amplifier circuit according to claim 2, wherein the resistance element functions as a pull-down resistor. 4. A differential amplifier, which includes a first current input terminal (T_1), a second current input terminal (T_2), and a first current input terminal having one end connected to these first and second current input terminals.
and second resistance elements (R_1, R_2), and first and second connection means connected to the other ends of the first and second resistance elements, respectively.
receiving mutually complementary input signals, the other end of the first resistive element is connected to a ground power source when the first input signal is in a first state, and is disconnected from the ground power source when the first input signal is in a second state; 2
connection means (Q_d_1, Q_d_2) for connecting the other end of the second resistive element to the ground power supply when the input signal is in the first state and disconnecting it from the ground power supply when the input signal is in the second state; When the signal is in the first state, the difference current between the current flowing through the first resistance element and the current flowing out from the second current input terminal is converted into a voltage and amplified, and the first input signal is in the second state. What is claimed is: 1. A differential amplifier characterized in that, in the state, a difference current between a current flowing through the second resistance element and a current flowing out from the first current input terminal is converted into a voltage and amplified. 5. A first memory cell array (CA_1) with multiple word lines and multiple bit lines, and a second memory cell array (CA_2) with multiple word lines and multiple bit lines.
), and a first column gate (Q_c_1) for selecting one bit line from the plurality of bit lines of the first memory cell array.
) and a second column gate (
Q_c_2), and a differential amplifier (AMP) in which first and second current input terminals are connected to the output terminals of the first and second column gates, and the differential amplifier includes a first and a second current input terminal. first and second resistance elements (R_1, R_2) having one ends connected to the current input terminals of No. 2, and first and second connection means connected to the other ends of these first and second resistance elements, respectively. each receiving first and second mutually complementary input signals; when the first input signal is in a first state, the other end of the first resistive element is connected to a ground power source; connection means (which disconnects the second resistive element from the ground power supply when the second input signal is in the first state, connects the other end of the second resistive element to the ground power supply when the second input signal is in the first state, and disconnects it from the ground power supply when the second input signal is in the second state); Q_d_1, Q_d_2). 6. A shorting means (Q_2_0) is connected between the first current input terminal and the second current input terminal, and when the address changes, the shorting means is turned on by the clock pulse (ATD) generated by the monostable multivibrator. Became the first, second
Claim 5 characterized in that a short circuit is made between the current input terminals of the
Non-volatile storage device as described.