JPH0314146A - High speed address converting mechanism control system - Google Patents
High speed address converting mechanism control systemInfo
- Publication number
- JPH0314146A JPH0314146A JP1151565A JP15156589A JPH0314146A JP H0314146 A JPH0314146 A JP H0314146A JP 1151565 A JP1151565 A JP 1151565A JP 15156589 A JP15156589 A JP 15156589A JP H0314146 A JPH0314146 A JP H0314146A
- Authority
- JP
- Japan
- Prior art keywords
- speed address
- high speed
- converting mechanism
- address converting
- address translation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000007246 mechanism Effects 0.000 title claims abstract description 43
- 238000000034 method Methods 0.000 claims description 6
- 238000001514 detection method Methods 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
Landscapes
- Memory System Of A Hierarchy Structure (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は高速アドレス変換機構の制御方式に関し、特に
割込み発生時の高速アドレス変換機構制御方式に関する
。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a control method for a high-speed address translation mechanism, and more particularly to a control method for a high-speed address translation mechanism when an interrupt occurs.
従来、高速アドレス変換機構制御方式は単一の高速アド
レス変換機構に対して動作するものがある。Conventionally, some high-speed address translation mechanism control schemes operate on a single high-speed address translation mechanism.
上述した従来の高速アドレス変換機構制御方式では、ア
プリケーションプログラム実行中に割込みか発生ずると
、割込み処理が起動され高速アドレス変換機構の内容を
書き替えていたため、割込み処理からアプリケーション
プロクラム復帰後の高速アドレス変換機構のヒツト率か
低下してしまうという欠点がある。In the conventional high-speed address translation mechanism control method described above, when an interrupt occurs during execution of an application program, the interrupt processing is started and the contents of the high-speed address translation mechanism are rewritten. The disadvantage is that the hit rate of the conversion mechanism decreases.
本発明の高速アドレス変換機構制御方式は、複数の高速
アドレス変換機構と、割込みが発生したかどうかを検出
する割込み発生時のソフトウェアビジブルなレジスタを
退避／復帰するためのレジスタ退避復帰手段と、前記割
込み検出手段によって検出された割込みに対して高速ア
ドレス変換機構の切り替えを制御する高速アドレス変換
機構切り替え手段とを有する。The high-speed address translation mechanism control method of the present invention includes a plurality of high-speed address translation mechanisms, a register saving/restoring means for saving/restoring a software-visible register at the time of an interrupt occurrence, which detects whether or not an interrupt has occurred; and high-speed address translation mechanism switching means for controlling switching of the high-speed address translation mechanism in response to an interrupt detected by the interrupt detection means.
次に本発明について図面を参照して説明チる。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例を示す説明図である。同図に
おいて高速アドレス変換機構制御方式は主記憶部１．オ
ペレーテイングシステム２．アプリケーションプログラ
ム３．高速アドレス変換機構４および５１割込み検出手
段６．高速アドレス変換切り替え手段７．レジスタ退避
復帰手段８、中央処理装置９とから構成されている。FIG. 1 is an explanatory diagram showing one embodiment of the present invention. In the figure, the high-speed address translation mechanism control method is the main memory section 1. Operating system 2. Application program 3. High-speed address translation mechanism 4 and 51 interrupt detection means 6. High-speed address conversion switching means 7. It is composed of a register save/restore means 8 and a central processing unit 9.
主記憶部１上にはオペレーティングシステム２及びアプ
リケーションプログラム３が展開されている。また、高
速アドレス変換機！Ｒ４にはアプリケーションプログラ
ム３のアドレス変換情報が登録されている。An operating system 2 and application programs 3 are developed on the main storage unit 1 . Also a fast address converter! Address conversion information of the application program 3 is registered in R4.
アプリケーションプログラム３を実行中に割込み検出手
段６が割込みを検出し、高速アドレス変換機構切替え手
段７及びレジスタ退避復帰手段８に通知する。While the application program 3 is being executed, the interrupt detection means 6 detects an interrupt and notifies the high-speed address translation mechanism switching means 7 and the register saving and restoring means 8.
レジスタ退避復帰手段８はソフトウェアビジプルなレジ
スタの退避復帰を行うとともに現時点まで使用していた
高速アドレス変換機構４の認識情、り嘘 α １
′、報である旧高速アドレス変換機構情報の退避及び割
込み処理を、どの高速アドレス変換機構を使用すべきか
の認識情報である新高速アドレス変換機構情報に復帰す
る。The register saving and restoring means 8 saves and restores the registers in a software-visible manner, and also saves the old high-speed address translation mechanism information, which is the recognition information, false information α1', and information of the high-speed address translation mechanism 4 that has been used up to the present time. The interrupt processing is returned to the new high-speed address translation mechanism information, which is the recognition information of which high-speed address translation mechanism should be used.
高速アドレス変換機構切り替え手段７はレジスタ退避復
帰手段８によって復帰された新高速アドレス変換機構情
報をもとに、高速アドレス変換機構５に切り替える。The high-speed address translation mechanism switching means 7 switches to the high-speed address translation mechanism 5 based on the new high-speed address translation mechanism information restored by the register saving and restoring means 8.
高速アドレス変換機構５を使用して割込み処理が実行さ
れる。Interrupt processing is executed using the high-speed address translation mechanism 5.
アプリケーションプログラム３へ戻る時はアプリケーシ
ョンプログラム３へ戻る割込みを起こすことによって、
割込み検出手段６が割込みを検出し、上記と同様にして
高速アドレス変換機構４に切替えてアプリケーションプ
ログラム３を実行する。When returning to application program 3, by causing an interrupt to return to application program 3,
The interrupt detection means 6 detects an interrupt, and switches to the high-speed address translation mechanism 4 to execute the application program 3 in the same manner as described above.
以上説明したように本発明は、アプリケーションプログ
ラム実行中に割込みが発生すると高速アドレス変換機構
を切り替えることにより、割込み処理実行時および割込
み処理からのアプリケーションプログラム復帰時の高速
アドレス変換機構のヒツト率が向上し、結果としてシス
テムめ性能を向上させることができる効果がある。As explained above, the present invention switches the high-speed address translation mechanism when an interrupt occurs during execution of an application program, thereby improving the hit rate of the high-speed address translation mechanism when executing interrupt processing and when returning from the application program from interrupt processing. As a result, the system performance can be improved.
第１図は本発明の一実施例を示す構成図である。
１・・・主記憶部、２・・・オペレーティングシステム
、３・・・アプリケーションプログラム、４，５・・高
速アドレス変換機構、６・・・割込み検出手段、７・・
・高速アドレス変換機構切替え手段、８・・・レジスタ
退避復帰手段、９・・・中央処理装置。FIG. 1 is a block diagram showing an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Main memory unit, 2... Operating system, 3... Application program, 4, 5... High-speed address translation mechanism, 6... Interrupt detection means, 7...
- High-speed address conversion mechanism switching means, 8... Register saving and restoring means, 9... Central processing unit.
Claims (1)
うかを検出する割込み発生時のソフトウェアビジブルな
レジスタを退避／復帰するためのレジスタ退避復帰手段
と、前記割込み検出手段によって検出された割込みに対
して高速アドレス変換機構の切り替えを制御する高速ア
ドレス変換機構切り替え手段とを有することを特徴とす
る高速アドレス変換機構制御方式。A plurality of high-speed address translation mechanisms, a register save/restore means for saving/restoring a software-visible register at the time of an interrupt occurrence to detect whether or not an interrupt has occurred, and a register save/restore means for detecting whether or not an interrupt has occurred; 1. A high-speed address translation mechanism control method, comprising: high-speed address translation mechanism switching means for controlling switching of the high-speed address translation mechanism.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1151565A JPH0314146A (en) | 1989-06-13 | 1989-06-13 | High speed address converting mechanism control system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1151565A JPH0314146A (en) | 1989-06-13 | 1989-06-13 | High speed address converting mechanism control system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0314146A true JPH0314146A (en) | 1991-01-22 |
Family
ID=15521312
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1151565A Pending JPH0314146A (en) | 1989-06-13 | 1989-06-13 | High speed address converting mechanism control system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0314146A (en) |
-
1989
- 1989-06-13 JP JP1151565A patent/JPH0314146A/en active Pending
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