JPH0313801B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to an on-board receiver in an automatic train control (abbreviated as ATC) device, in which a selection circuit is constructed by digitizing received ATC signals, and it is possible to downsize the signal selection circuit. While aiming for
The object of the present invention is to provide a device of this kind that reliably selects any one of the mixed signals received near the boundary of an ATC block section.

Figure 1 is a circuit block diagram showing an example of a conventional ATC on-board receiver configuration, where RA is a block diagram of two receiving coils installed vertically above the car, facing a pair of rails laid on the ground. T is a matching transformer, F ₁ and F ₂ are a detection circuit consisting of a filter, an amplifier, a detector, etc., which selectively pass signal carrier waves f ₁ and f ₂ of different frequencies, respectively;
Fl is a signal selection circuit consisting of a filter that selectively passes the low-speed ATC signal fl, a level detector, an amplifier, a rectifier, etc., and drives the reception relay Rl by receiving the ATC signal fl. Similarly, Fm and Fh are selection circuits for a medium-speed ATC signal fm and a high-speed ATC signal fh, respectively, which receive the ATC signal fm or fh and drive the respective receiving relays Rm or Rh. Figure 2 is an example of a lower speed priority circuit configured by combining the contacts of the receiving relays Rl, Rm, and Rh shown in Figure 1. (high speed) speed control is permitted.

As explained with reference to Fig. 1 above, in the past, ATC separated into carrier wave f ₁ and carrier wave f _{2 and} demodulated using band pass filters included in detection circuits F ₁ and F ₂ .
The signals are separated into low-speed (ls), medium-speed (ms), and high-speed (hs) ATC signals by selection circuits Fl, Fm, and Fh, and are selected and output from the lower speed priority circuit shown in Figure 2. . However, the selection circuits Fl, Fm, Fh
etc., the ATC signal usually uses a low frequency of about 10 to 100 (Hz) from the point of view of signal-to-noise ratio (S/N), so the selection filter for these low frequencies is an LC filter or an active CR filter. The disadvantage was that the circuit components were inevitably large in size because they were processed in an analog manner.

Therefore, as a means of downsizing each ATC signal selection circuit, digitization of the circuit has been proposed. Figure 3 shows an example of this.The common circuit on the output side of the detection circuits _F1 and _F2 for carrier waves f1 and _f2 shown in Figure ₁ is a waveform shaping circuit SM using a Schmitt circuit, etc., and Figure 5 shows a digital waveform shaping circuit SM. A period measuring circuit C is an example of an ATC signal selection circuit which shows a specific example of the ATC signal selection circuit.
This is an example of a circuit of an ATC receiver configured with a lower speed priority circuit P, etc. configured with an electronic circuit such as the "priority selection circuit" described in Publication No. 153201. However, the output symbols ls, ms, hs, and Os of the lower speed priority circuit P are low speed, medium speed, high speed, and stop output signals, respectively.

However, there are problems that are difficult to solve by simply digitizing the circuit as shown in FIG. In other words, two types of carrier waves are used to prevent reception of train detection signals flowing in from other sections due to dielectric breakdown of the track circuit.
f ₁ and f ₂ are used alternately in adjacent block sections. Therefore, at the boundary of the ATC block section, two signal waves with different carrier waves are mixed and received, and waveform distortion occurs due to the mutual amplitude relationship of the two waves. Therefore, if the number of signals is selectively measured digitally using a circuit as shown in FIG. 3, an erroneous signal will be output or no signal will be output.

To explain the above state using the time chart in Figure 4, chart a in the figure can be set to any ATC.
The carrier wave f ₁ in the block section is amplitude modulated.
Assuming that chart b represents the ATC signal fm and the chart b represents the ATC signal fl that is amplitude-modulated on the carrier wave f ₂ of the forward block section adjacent to the aforementioned section, the third
Signal detected and demodulated by the detection circuit _F1 shown in the figure
fm is output as a square wave signal as shown in chart c of FIG. 4, and signal fl detected and demodulated by the detection circuit _F2 is output as a square wave signal as shown in chart d. Therefore, when the train in the arbitrary block section advances and the antenna circuit RA of FIG. 1 comes to the boundary between the two sections, the two signal waves fm and fl are mixed and received as described above, The signal wave input to the waveform shaping circuit SM in the figure has a waveform as shown in chart e, which is a mixture of the waveforms in charts c and d in Figure 4, and after the level is determined by the waveform shaping circuit SM, it is input to the period measuring circuit C As shown in chart f in FIG. 4, the resulting waveform is a waveform with an indefinite period that does not match the period of either signal fm or fl, making it impossible for period measuring circuit C to select the ATC signal.

FIG. 5 shows a specific example of the period measuring circuit C shown in FIG. 3, which is shown here as a digital circuit for ATC signal selection, which has been digitized. The figure shows the ATC signal that is detected and demodulated by the detection circuit F ₁ or F ₂ in Figure 3, and then its level is determined by the waveform shaping circuit SM.
Shift register R that shifts the input signal s representing fl, fm, fh, etc. using a clock pulse cp and outputs it.
and AND gates Al, Am, and Ah corresponding to the ATC signals fl, fm, and fh. The input circuits of the group are connected in parallel as shown in the figure, and the inverters (polarity inverting circuits) indicated by the symbols in the multiple input circuits of each AND gate are connected in parallel to each other for each selection period of the input signal. It has been inserted as appropriate.

6 is a time chart showing the operating state of the circuit in FIG. 5. Chart a in FIG. 6 is the signal waveform of the low-speed ATC signal fl input to the shift register R;
Chart b shows the output logic value of shift register R indicating the state in which the signal wave of chart A is digitized into a binary logic value by clock pulse cp, and chart c shows that all inputs to AND gate Al are logic value "1". This shows the output pulse of the gate Al that is generated only under the conditions where , and is generated every cycle Tl of the input signal fl depending on the arrangement of the inverter inserted in the input circuit. Similarly, chart d is medium speed
The signal waveform of ATC signal fm, chart e is the output logical value of shift register R corresponding to the signal wave of chart d, chart f is the output pulse of AND gate Am generated every cycle Tm of signal fm, chart g
is the signal waveform of the high-speed ATC signal fh, chart h is the output logical value of shift register R corresponding to the signal wave of chart g, and chart i is the output pulse of AND gate Ah generated every period Th of signal fh.

The AND gates Al, Am, and Ah in Figure 5 have signals.
The outputs of the shift registers R corresponding to fl, fm, and fh are all input, but as shown in Figure 6, the output pulse for each period is output only for the signal with a period that satisfies the AND condition of each AND gate. Because it occurs,
Periods of output pulses of each AND gate Tl, Tm,
The ATC signals fl, fm, and fh can be selected and separated by Th. However, as mentioned earlier, two signal waves are mixed and received near the boundary of the ATC block section, resulting in a signal wave with an irregular shape and period as shown in charts e and f in Figure 4. is formed and input, and gate Al,
Neither of the AND conditions Am or Ah can be satisfied, and the period measuring circuit C becomes unable to output.

The present invention compares the reception levels of different signals near the boundary of the ATC block section mentioned above, selects a high-level signal, and performs frequency selection.The device can be made smaller by digitizing the signal selection circuit. In addition, the above-mentioned drawbacks such as the inability to output are eliminated.

Next, an embodiment of the present invention will be described with reference to FIGS. 7 and 8. Figure 7 is an example of a circuit in which when different carrier waves and signal waves are received at the same time near the boundary of an ATC block section, one of the ATC signals is reliably selected and its period is measured. . In other words, F ₁ A in the same figure,
F ₂ A is a carrier wave selection circuit consisting of a passband filter and an amplifier for carrier waves f ₁ and f ₂ , respectively;
is a reception level comparison circuit for carrier waves f ₁ and f ₂ , X is a switching circuit that switches the output to the carrier wave with a higher level,
D is a signal detection demodulation circuit, SM is a waveform shaping circuit,
C is a period measuring circuit as shown in FIG. 5 as a means of frequency selection, and P is a lower speed priority circuit similar to that described in FIG. 3.

FIG. 8 is a time chart showing the operating state of the circuit of FIG. 7 near the boundary between adjacent ATC block sections. Carrier wave f ₁ from the train, signal fm
When entering the block section of the carrier wave f ₂ and signal fl from the ATC block section, the output waveform of the selective amplification circuit F ₁ A of the carrier wave f ₁ near the boundary between the two sections is as shown in chart a of FIG. Selective amplification circuit F ₂ A of carrier wave F ₂ whereas its output level is gradually attenuated
As shown in chart b, the output level of the output waveform gradually increases. Therefore, the level comparison circuit
As shown in chart c, the output of the LC changes from the output state showing the receiving level f ₁ > f ₂ to the output state showing f ₁ < f ₂ , and the output wave of the switching circuit
As shown in the figure, the waveform of the carrier wave f ₁ and the signal fm is switched to the waveform of the carrier wave f ₂ and the signal fl. Therefore, the signal fm due to the previous carrier wave _f1 shown in chart e
The output of the signal fl is cut off, and instead, the output of the signal fl whose carrier wave is _f2 , shown in chart f, is input to the detection demodulation circuit D, where it is demodulated and the level is determined by the waveform shaping circuit SM. The frequency is selected by the period measuring means and inputted to the lower speed priority circuit P, and the output based on the speed condition is inputted to the speed checking circuit (not shown) of the ATC onboard device to automatically control the train's brakes. I will do it.

Although the output of the period measuring circuit C is a pulsed AC output using the circuit shown in FIG. 5 as an example, the same applies to a DC output. Furthermore, by providing hysteresis in the comparison characteristics of the level comparison circuit LC shown in FIG. 7, it is possible to prevent unstable operation when the train stops at the same level position of the carrier waves f ₁ and f ₂ . In addition, in the above embodiment, a signal period measuring circuit is used as a frequency selection means in the digital selection circuit of the ATC signal detected and demodulated, but other means, for example, counting the signal waves within a certain period of time, is used as the frequency selection means. There are digital frequency selection means for selection, and are not necessarily limited to period measurement means. Furthermore _, in the explanation of Fig _. 7, the explanation was given by inserting a demodulating circuit on the output side of the switching circuit A similar effect can be obtained by inputting the signal to the switching circuit X.

As explained through the above embodiments, the present invention
The ATC signal selection circuit is digitally configured and miniaturized, and a means is provided for reliably selecting one of the ATC signals mixed and received near the boundary of the ATC block section.
This will have an extremely significant effect on ATC operations.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing an example of a conventional ATC onboard receiver configuration, Figure 2 is an example of a lower speed priority circuit using the reception relay in Figure 1, and Figure 3 is an ATC onboard receiver configuration.
On-vehicle receiver with digitalized signal selection circuit 1
A block diagram showing an example, Fig. 4 is a time chart for explaining the operation of the on-vehicle receiver in Fig. 3, Fig. 5 is an example diagram of a digitized ATC signal period measuring circuit, and Fig. 6 is an operation of the same circuit. FIG. 7 is a circuit block diagram of an ATC on-vehicle receiver configuration showing one embodiment of the present invention, and FIG. 8 is a time chart for explaining the operation of the same circuit. f ₁ , f ₂ : carrier wave, fl, fm, fh : ATC signal,
F ₁ A, F ₂ A: carrier selection circuit, LC: level comparison circuit, X: switching circuit, D: detection demodulation circuit, C: period measurement circuit, P: lower speed priority circuit.

Claims (1)

[Claims] 1. In an automatic train control onboard receiver that receives train control signals transmitted by carrier waves with different frequencies in adjacent block sections onboard the train, and separates the received signals by carrier wave, A level comparison circuit for a train control signal, and a switching circuit that selects and outputs a received carrier wave with a high level based on the output of this comparison circuit are provided.The output signal of this switching circuit is detected and demodulated and digitized by a frequency selection circuit. An automatic train control on-board receiver characterized by performing selection.