JPH0313710Y2 - - Google Patents

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a synchronous rectification circuit for synchronously rectifying an unbalance detection signal to extract an unbalanced force component in a balance testing machine.

<Prior art> In general, a balance tester using a synchronous rectification system is equipped with two sets of synchronous rectification circuits as shown in Fig. 4, and detects centrifugal force and vibration detection signals obtained by rotating the test object. , are introduced into these two sets of synchronous rectifier circuits, and each circuit is operated in synchronization with the rotation period of the test object and with a phase difference of 90 degrees, and the test object is detected from the above detection signal. 2 corresponding to the 90° component of the unbalance signal synchronized with the rotation period of
Obtain two DC signals.

By the way, in the synchronous rectifier circuit as shown in FIG. 4, the switch 1 is opened and closed every half cycle in synchronization with the input signal cycle, and conventionally, a switching transistor such as a FET switch is generally used.

Further, the input signal of this synchronous rectifier circuit, that is, the unbalance signal which is a detection signal of centrifugal force or vibration caused by the rotation of the test object, becomes a signal close to a sine wave whose positive/negative sign changes periodically.

<Problem to be solved by the invention> Here, the switching transistor is usually
ON resistance is approximately 200~400Ω, OFF resistance is approximately 2~5M
Ω, making it an ideal switch (ON resistance 0
Ω, OFF resistance ∞Ω), but there are some differences. Furthermore, the ON resistance differs depending on the sign of the input signal.

From the above, in a synchronous rectifier circuit as shown in Figure 4, if a positive signal is inputted to an operational amplifier by passing 100% of the current, for example, if a negative signal is input to an operational amplifier (100 - Δ)%
only the signal is input to the operational amplifier.

Therefore, the rectification result by such a synchronous rectifier circuit is determined by the phase difference of the chopping with respect to the unbalanced signal, that is, the position of the unbalance with respect to the reference position of the test object, as shown by the broken line in FIG. The value is smaller in the negative region compared to the actual rectification result. This means that when the unbalance vector is determined using this rectification result, even if the unbalance amount is the same, the indicated value of the unbalance amount will differ depending on the unbalance angle of the test object.

In order to solve the above problems, it is necessary to use a special switching transistor whose ON resistance does not depend on polarity, but this is extremely expensive.

The purpose of the present invention is to eliminate phase distortion as shown in Figure 5, even if an inexpensive and easily available unipolar IC switch is used, for example, without using the above-mentioned special switching transistor. An object of the present invention is to provide a synchronous rectifier circuit for an unbalance tester in which no problem occurs.

<Means for Solving the Problems> The configuration for achieving the above object will be explained with reference to FIG. 3 corresponding to the embodiment. and a capacitor 26),
equal to its feedback resistance and feedback capacitance, respectively,
It is connected to an operational amplifier 23 comprising a ground resistance and a ground capacitance (resistor 27 and capacitor 28) in parallel with each other, and one differential input terminal of the operational amplifier 23, and is synchronized with the rotation period of the test object. The first switching transistor 22 is connected to the other differential input terminal of the operational amplifier 23, and the first switching transistor 22 is opened and closed every half cycle. The second switching transistor 24 is configured to introduce the unbalanced signal to both differential input terminals of the operational amplifier 23 via the first and second switching transistors 22 and 24, respectively. characterized by.

<Operation> First and second switching transistors 2
2 and 24 are opened and closed every half cycle of the rotation of the test object, and they are opened and closed with a phase difference of 180 degrees, so that the full wave of the unbalanced signal is input to the operational amplifier 23. Even if there is a polarity dependence of the ON resistance of the first and second switching transistors 22 and 24, the rectification error caused by this is averaged out and the distortion due to the phase is improved. .

<Example> An example of the present invention will be described below based on the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention.

The input signal, which is an unbalanced signal, is passed through a resistor 21 to the first and second switching transistors 2.
2 and 24, respectively. The output side terminal of the first switching transistor 22 is connected to the negative side of the differential input terminals of the operational amplifier 23, and the output side terminal of the first switching transistor 22 is connected to the negative side of the differential input terminals of the operational amplifier 23.
The output side terminals of are similarly connected to the + side differential input terminals of the operational amplifier 23, respectively.

first and second switching transistors 2
2 and 24 are opened and closed at the timings whose time charts are shown in FIGS. 2a and 2b, respectively. That is, the first switching transistor 22 is opened and closed in synchronization with the rotation period of the test object, for example, with a phase difference of 0 degrees with respect to the rotation phase, and every half period of the rotation period, and the second switching transistor 22 is The switching transistor 24 is opened and closed in a phase opposite to that of the switching transistor 24.

The operational amplifier 23 has a feedback loop in which a resistor 25 and a capacitor 26 are connected in parallel between the − side differential input terminal and the output terminal, and the + side differential input terminal has a feedback loop with the same resistance value as the resistor 25. A resistor 27 and a capacitor 28 having the same capacity as the capacitor 26 are connected in parallel and connected to the ground.

According to the above-described embodiment of the present invention, the unbalance signal is synchronized with the rotation period of the test object and is alternately guided to the negative and positive input terminals of the operational amplifier 23 every half period, and the unbalance signal is fed at the same rate. will be amplified. Therefore, the unbalanced signal is full-wave rectified, and even if the ON resistances of the first and second switching transistors 22 and 24 have polarity dependence, the rectification errors caused by this are averaged out, and the rectification results do not depend on the phase. No distortion occurs. In other words, even if only (100-Δ%) of the negative signal is passed as described above, it is full-wave rectified, so the distortion based on the phase of the chopping is superimposed and averaged.
Compared to the ideal rectification result shown by the solid line in FIG. 5, the size is smaller overall by Δ% in the negative region, but it becomes approximately circular.

Note that even if unipolar IC switches are used as the first and second switching transistors 22 and 24, the second or first switching transistor remains OFF while the first or second switching transistor 22 or 24 is OFF. 24 or 22
is always turned on, and the unbalance signal is always guided to one of the input terminals of the operational amplifier 23, which is the virtual zero point, so the switch transistor 22 or 2
No reverse bias is applied at the OFF timing in step 4, allowing smooth ON/OFF.

FIG. 3 is a circuit diagram of another embodiment of the present invention. In this embodiment, an amplifier 33 and a resistor 34 are provided between the resistor 21 and the switch group to produce a signal that is -1 times the input signal U, and the signal and the input signal U are respectively switching transistors 22 and 24, third and fourth switching transistors 29 and 30;
Reference numeral 9 is connected to a negative differential input terminal of the operational amplifier 23, and second and fourth switching transistors 24 and 30 are similarly connected to a positive differential input terminal.

With this configuration, the distortion due to the phase is eliminated as in the previous embodiment, and at the same time, the unbalanced signal and its inverted signal are always input to the differential input terminal of the operational amplifier 23, so the rectification efficiency is improved. This is twice that of the previous example. In this embodiment, the resistors 21 and 34, the resistors 31 and 32, and the resistors 25 and 27 have the same resistance value, and the capacitors 26 and 28 have the same resistance value.
must have the same capacity.

<Effects of the invention> As explained above, according to the invention, the device opens and closes in synchronization with the rotation period of the test object in half its period.
By chopping the unbalanced signal using two switching transistors with a phase difference of 180 degrees,
Since I configured it so that the inputs are input alternately to the differential input terminals of the operational amplifier and amplified at the same rate, the ON
Even if a switching transistor that is dependent on the polarity of the input signal is used as a resistor, the rectification errors caused by this are averaged out, and a rectification result that is free from distortion due to the phase of the unbalanced signal can be obtained as a whole. As a result, it becomes possible to accurately measure unbalance without using a special, extremely expensive transistor whose ON resistance is polarity-independent, as in the past, and it is possible to reduce the cost of the device.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram of an embodiment of the present invention, FIG. 2 is a timing chart showing the opening and closing operations of the first and second switching transistors 22 and 24, and FIG. 3 is a diagram of another embodiment of the present invention. Circuit configuration diagram, Figure 4 is a configuration diagram of a conventional synchronous rectifier circuit, Figure 5
The figure is an explanatory diagram of distortion of the rectification result with respect to the phase of the unbalanced signal. 22...first switching transistor, 2
3... Operational amplifier, 24... Second switching transistor, 25, 27... Resistor, 26, 28
...Capacitor.

Claims (1)

[Claims for Utility Model Registration] A circuit that rectifies an unbalanced signal generated by rotating a test object by chopping it in synchronization with the rotation period of the test object, the circuit having mutually parallel feedback. A ground resistance that is equivalent to the feedback resistance and feedback capacitance and parallel to each other is connected to a differential input terminal that is different from the differential input terminal to which the feedback resistance and feedback capacitance are connected. and an operational amplifier connected to a ground capacitance, and a first switching transistor connected to one differential input terminal of the operational amplifier and opened and closed every half period in synchronization with the rotation period of the test object. and a second switching transistor connected to the other differential input terminal of the operational amplifier and opened and closed with a phase difference of 180° from the first switching transistor, and transmitting the unbalanced signal to the first switching transistor and the second switching transistor connected to the other differential input terminal of the operational amplifier. A synchronous rectifier circuit for a balance tester, characterized in that the circuit is configured to be introduced into both differential input terminals of the operational amplifier via first and second switching transistors.