JPH03136241A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To make possible a high-precision flattening of a polycrystalline silicon layer without being affected by a loading effect by a method wherein a silicon- containing resist layer is left in a recessed part in the silicon layer and an etchback of the silicon layer is performed with the mixed gas of chlorine gas and oxygen gas using the resist layer as a mask. CONSTITUTION:An opening part 3 is formed in an insulating film 2 on a semiconductor substrate 1 and a polycrystalline silicon layer 4 made to follow the surface step of the film 2 is formed in such a way as to cover at least the above opening part 3. Then, a silicon-containing resist layer 5 is selectively formed only in a recessed part 4b generated in the layer 4 facing the opening part 3 to flatten the surface of the substrate and after the layer 4 is etched back with the mixed gas of chlorine gas and oxygen gas using the layer 5 as a mask, the layer 5 is removed. Thereby, as O2 gas reacts with the silicon in the silicon-containing resist layer 5 and a silicon oxide film is formed in the surface layer part of the layer 5, an etching does never excessively proceed in the upper part of the opening part 3 and a good flattening is realized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for planarizing a polycrystalline silicon layer.

[Summary of the invention]

The present invention provides a method for manufacturing a semiconductor device in which a polycrystalline silicon layer formed on a substrate having a step is planarized using an etch bank, in which a silicon-containing resist layer is selectively left in the recessed portions of the polycrystalline silicon layer, and chlorine chloride is removed. By etching back the polycrystalline silicon layer while changing the surface layer of the silicon-containing resist layer to silicon oxide, which is difficult to etch, using a mixed gas of system gas and oxygen gas, accuracy can be improved without being affected by the loading effect. This makes it possible to flatten a high polycrystalline silicon layer.

[Prior art] In recent years, in the field of semiconductor devices such as VLSI and ULSI, not only two-dimensional miniaturization but also three-dimensional integration has been progressing with the aim of achieving higher integration and higher performance. technology is becoming increasingly important. The material layer targeted for this planarization is limited to the insulating film, contact hole, and peer hole 5.
This also applies to polycrystalline silicon layers for embedding trench capacitors, trench isolation, etc.

Conventionally, the methods shown in FIGS. 4(A) and 4(B) have generally been used to planarize a polycrystalline silicon layer.

That is, as shown in FIG. 4(A), an insulating film (12) having an opening (13) formed on a semiconductor substrate (11) is prepared in advance.
) is formed, and a polycrystalline silicon layer (14) is further formed covering at least the opening (13), and the base body is flattened by a flattening film (15) made of a resist material or the like.

Next, etchback is performed under conditions such that the selectivity ratio between the planarization film (15) and the polycrystalline silicon layer (14) is l:1, and the surface of the substrate is planarized as shown in FIG. 4(B). do.

However, unlike the planarization of an insulating film made of silicon oxide, etc., the planarization of the polycrystalline silicon layer (14) as described above is easily affected by the loading effect, and in fact, as shown in FIG. 4(B). Achieving such an ideal situation is difficult. That is, when the surface of the polycrystalline silicon layer (14) is exposed during the etch-back process, the etch rate of the polycrystalline silicon layer (14) is relatively lowered, and the flattened silicon layer (15) remaining in the recessed portion is better. Insulation II! When the surface of (12) is exposed, the etching progresses to the inside of the opening (13) (over-etching), and as a result, the surface of the substrate is not flattened as shown in FIG. In an even more extreme case, the polycrystalline silicon layer (
14) may be removed, which may be a serious defect.

As a technique for solving such problems, for example, Japanese Patent Application Laid-open No. 139321/1983 describes a method of ion-implanting impurities such as phosphorus at a high concentration into the surface layer of the polycrystalline silicon layer formed to cover the opening. Alternatively, the reactivity of the polycrystalline silicon layer near the surface layer with respect to the etching gas (mixed gas of CF4 and 0□) is relatively increased by tungsten silicide, and reactive ion etching is performed using the mixed gas. Techniques for planarizing the surface of a substrate are disclosed.

[Problem to be solved by the invention]

However, even if the technique disclosed in JP-A-62-139321 is applied, it is considered difficult to achieve complete planarization for the following reasons. First of all, when ion implantation of phosphorus is performed as a means of modifying the properties of the surface layer of a polycrystalline silicon layer, activation by heat treatment is required, but as a result, the impurities introduced at a high concentration are There is a possibility that it will spread to the inside of the opening. Second, since heat treatment is also performed when tungsten silicide is formed, there is a possibility that the region to be silicided will expand into the inside of the opening. Therefore, these methods cannot be called practical.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that solves the problems of the prior art and enables highly accurate planarization of a polycrystalline silicon layer.

[Means to solve the problem]

In order to achieve the above-mentioned object, the present inventor conducted a study and found that when a silicon-containing resist conventionally applied in a multilayer resist method is exposed to oxygen plasma, the surface layer easily changes to silicon oxide ( By paying attention to the change in the thickness of the etching surface (Sin, ) and using it selectively as a mask in areas where overetching is likely to occur, we found that highly accurate planarization is possible without being affected by the loading effect. , which led to the completion of the present invention.

That is, the method for manufacturing a semiconductor device according to the present invention includes the steps of forming an opening in an insulating film on a semiconductor substrate, and forming a polycrystalline silicon layer that covers at least the opening and follows the surface steps of the insulating film. a step of selectively forming a silicon-containing resist layer only in the recesses formed in the polycrystalline silicon layer facing the opening to planarize the surface of the substrate; The method is characterized by comprising a step of etching back the polycrystalline silicon layer with a mixed gas using the silicon-containing resist layer as a mask, and a step of removing the silicon-containing resist layer.

[Function] In the present invention, instead of flattening the polycrystalline silicon layer by setting the selectivity of different materials to 1; A silicon-containing resist layer is selectively formed, and the polycrystalline silicon layer is etched while changing the surface layer of the silicon-containing resist layer into a material that is difficult to etch using an etching gas used in the next step.

Here, the method of selectively forming a silicon-containing resist layer only in the concave portions of the polycrystalline silicon layer is to form the silicon-containing resist layer on the entire surface and then etching until the flat portion of the polycrystalline silicon layer is exposed. How to bank, ■
Select a positive type material for the silicon-containing resist layer, expose it to light in the recesses weakly enough to prevent photochemical reactions from proceeding, and then remove the exposed areas by development, or ■ form openings in the insulating film. A possible method is to expose a positive type silicon-containing resist using an inverted mask, develop and remove the exposed area, and then etch back.

In the conventional general etch-back process, the exposed area of the polycrystalline silicon layer increases rapidly once the silicon-containing resist is left only in the recesses of the polycrystalline silicon layer. The etching speed of the silicon layer was relatively reduced, and the influence of the loading effect became significant.

However, in the present invention, etchback is performed using a mixed gas of chlorine-based gas and oxygen gas in the subsequent step. In this step, the silicon-containing resist layer remaining in the recesses comes into contact with oxygen plasma, so that its surface layer changes to silicon oxide. This effect is only exhibited when the resist layer contains silicon. Moreover, the selectivity ratio between polycrystalline silicon and silicon oxide by the mixed gas is as large as 10 or more. As a result, a process equivalent to etching a polycrystalline silicon layer using the silicon oxide film as a mask proceeds in the upper part of the opening. Therefore, it is possible to perform flattening with high precision without being affected by the loading effect as in the prior art.

[Embodiments] Hereinafter, preferred embodiments of the present invention will be explained with reference to FIGS. 1(A) to 1(E).

First, as shown in FIG. 1(A), a semiconductor substrate (1) made of, for example, silicon oxide is placed on a semiconductor substrate (1) made of silicon or the like. !
Edges 119 (2) are formed and buttering is performed to form openings (3). Next, a polycrystalline silicon layer (4) is deposited over the entire surface by CVD, which has excellent coverage. At this time, the polycrystalline silicon layer (4) reflects the step difference in the underlying layer, and in addition to the flat part (4a), a concave part (4b) is formed on the surface facing the opening part (3).

Next, as shown in FIG. 1B, a silicon-containing resist layer (5) is coated on the entire surface to planarize the surface of the substrate. Here, a mixture of a siloxane-based novolak resin and a quinonediazide compound was used as the material for the silicon-containing resist layer (5). The silicon content of the above materials is usually around 3% or less. However, the material is not limited to this, as long as the material can be easily oxidized from the surface by oxygen plasma. Thereafter, baking is performed at a temperature of about 80° C. to evaporate and remove the solvent.

Next, as shown in FIG. 1(C), the silicon-containing resist layer (5) is etched back, and the process ends when the surface of the flat part (4a) of the polycrystalline silicon layer (4) is exposed. . Here, as the etching gas for performing the above etching, C/l! ,,NF3゜SFi,CCI
Fx, NH3, etc. are used.

Next, cI! Endepacking of polycrystalline silicon N(4) is performed using a mixed gas of z gas and 0□ gas.

The conditions for the above etchback are, for example, a C11 gas flow it 20 SCCM using an ECR etching apparatus.

0□Gas flow 130 SCCM, vacuum level 10 mTorr
,? Microwave power 850 W, high frequency bias 20
It is assumed to be 0W. In this step, the C1 gas reacts with the polycrystalline silicon and removes the silicon in the form of highly volatile chlorides, while the C1 gas reacts with the silicon-containing resist layer (5).
Reacts with the silicon inside and forms silicon oxide on the surface layer.
form n. Although this silicon oxide (Sin) is etched to some extent by the mixed gas, the etching rate is less than 1/10 of the etching rate of the polycrystalline silicon layer (4).

Therefore, the silicon-containing resist layer (5) functions as an etching mask, and since it is successively oxidized from the surface as etching progresses, it continues to function as a mask.

As a result, as shown in FIG. 1(D), even when the polycrystalline silicon N (4) is etched until the surface of the insulating film (2) is exposed, the upper part of the opening (3) Good planarization is achieved without excessive etching progressing.

Note that the chlorine-based gas used for the etchback is not limited to the above-mentioned Cf2, but may include BCl2. .

HCI! , , C (14, etc.) can also be selected.

Finally, as shown in FIG. 1E, the silicon-containing resist N (5) remaining above the opening (3) is removed using buffered hydrofluoric acid or the like.

In the above example, the planarization of the polycrystalline silicon layer (4) by etch-back ended when the surface of the insulating film (2) was exposed, but the layer thickness and coverage of the polycrystalline silicon layer (4) Depending on the situation, planarization may be achieved before the insulating film (2) is exposed, as shown in FIG. In such a case, a silicon-containing resist layer (5
) may be removed first and then etched back again until the insulating film (2) is exposed.

By the way, in the above method, the entire silicon-containing resist layer (5) is left only in the recesses (4b) of the polycrystalline silicon layer (4) by etching back the entire surface, but a method that does not involve etchback is also possible. be. For example, a positive type material is selected as the silicon-containing resist and applied to form a silicon-containing resist layer (5), as shown in FIG.
The substrate is flattened in the same manner as in the state shown in B). Subsequently, a photodecomposition reaction occurs only in the upper part of the flat part (4a),
In addition, when controlled exposure is performed at an intensity that does not cause a photodecomposition reaction in the recesses (4b), and then development is performed, only the recesses (4b) are filled with the silicon-containing resist layer (5).

Furthermore, the following method may be considered, which combines selective exposure and etching. This is shown in Figure 3 (A).
This will be explained with reference to FIG. 3(B). First, the third
As shown in Figure (A), an inverted mask (6) with respect to the mask for forming the opening (3) in the insulating film (2) is used, and the same condition as that shown in Figure 1 (B) is used. Perform selective exposure of the substrate. Next, as shown in FIG. 3B, the exposed portion of the silicon-containing resist layer (5) is removed by development, leaving only the unexposed portion facing the opening (3). Thereafter, etchback is performed to flatten the surface of the substrate as in the state shown in FIG. 1(C). According to this method, since the area of the silicon-containing resist layer (5) to be etched is small, the time required for etching is significantly shortened.

〔Effect of the invention〕

As is clear from the above description, when the present invention is applied, when flattening the polycrystalline silicon layer formed covering the opening, etchback is performed while the upper part of the opening is protected by a mask. .

Therefore, in the present invention, over-etching within the opening, which is often seen in the conventional general etch bank process, does not occur, and it is possible to manufacture a semiconductor device with high integration, high reliability, and high performance.

[Brief explanation of the drawing]

FIGS. 1(A) to 1(E) are schematic cross-sectional views for explaining an example of the method for manufacturing a semiconductor device of the present invention according to the process order, and FIG. 1(A) shows an insulating film, an opening, Step of forming a polycrystalline silicon layer, FIG. 1(B) is a step of forming a silicon-containing resist layer, and step 11ffl (C) is a step of forming a silicon-containing resist layer only in the concave portions of the polycrystalline silicon layer by etch-back or controlled exposure. Process, 1st I2
] (D) shows the etch-back process of the polycrystalline silicon layer using a mixed gas of chlorine gas and oxygen gas, and FIG. 1 (E) shows the process of removing the silicon-containing resist layer. FIG. 2 is a schematic cross-sectional view showing another state in the etch-back process of the polycrystalline silicon layer. 3(A) and 3(B) are schematic cross-sectional views illustrating another method of forming a silicon-containing resist layer only in the recessed portions of a polycrystalline silicon layer by selective IR exposure. A) shows a selective exposure process using a reversal mask, and FIG. 3(B) shows a development process. 4(A) and 4(B) are schematic cross-sectional views sequentially illustrating a conventional general planarization process of a polycrystalline silicon layer, and FIG. 4(A) shows an insulating film. Forming process of opening, polycrystalline silicon layer, and planarization film, fourth
Figure (B) shows the state i after the etchback has been completed. FIG. 5 is a schematic cross-sectional view showing an overetching state in a conventional planarization process of a polycrystalline silicon layer. Semiconductor substrate insulating film opening polycrystalline silicon layer recess silicon-containing resist layer

Claims (1)

[Scope of Claims] A step of forming an opening in an insulating film on a semiconductor substrate, a step of forming a polycrystalline silicon layer that covers at least the opening and follows the surface steps of the insulating film, and the opening a step of planarizing the surface of the substrate by selectively forming a silicon-containing resist layer only in the recesses formed in the polycrystalline silicon layer; A method for manufacturing a semiconductor device, comprising: etching back the polycrystalline silicon layer using the polycrystalline silicon layer as a mask; and removing the silicon-containing resist layer.