JPH03136235A - Formation of p-n junction - Google Patents
Formation of p-n junctionInfo
- Publication number
- JPH03136235A JPH03136235A JP27428089A JP27428089A JPH03136235A JP H03136235 A JPH03136235 A JP H03136235A JP 27428089 A JP27428089 A JP 27428089A JP 27428089 A JP27428089 A JP 27428089A JP H03136235 A JPH03136235 A JP H03136235A
- Authority
- JP
- Japan
- Prior art keywords
- type semiconductor
- deposition
- thin film
- type
- ion implantation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000015572 biosynthetic process Effects 0.000 title claims description 3
- 239000004065 semiconductor Substances 0.000 claims abstract description 23
- 238000000034 method Methods 0.000 claims abstract description 22
- 238000005468 ion implantation Methods 0.000 claims abstract description 16
- 238000001771 vacuum deposition Methods 0.000 claims abstract description 4
- 150000002500 ions Chemical class 0.000 abstract description 23
- 239000000758 substrate Substances 0.000 abstract description 14
- 239000010409 thin film Substances 0.000 abstract description 12
- 239000010408 film Substances 0.000 abstract description 7
- 239000013078 crystal Substances 0.000 abstract description 6
- 238000000151 deposition Methods 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 abstract description 4
- 239000000126 substance Substances 0.000 abstract description 2
- 238000004506 ultrasonic cleaning Methods 0.000 abstract description 2
- 230000008021 deposition Effects 0.000 abstract 4
- 239000010410 layer Substances 0.000 description 13
- 125000004429 atom Chemical group 0.000 description 9
- 238000007740 vapor deposition Methods 0.000 description 6
- 239000002344 surface layer Substances 0.000 description 5
- 238000010894 electron beam technology Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000004949 mass spectrometry Methods 0.000 description 2
- 229910052787 antimony Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 229910052793 cadmium Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 229910000765 intermetallic Inorganic materials 0.000 description 1
- 229910052745 lead Inorganic materials 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 125000004433 nitrogen atom Chemical group N* 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 230000005676 thermoelectric effect Effects 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】 ［産業上の利用分野］ 本発明はＰＮ接合形成法に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a method for forming a PN junction.
［従来の技術］
従来、特定の元素をＳｉウェーハなどの表面に打ち込む
ことによってドーピングを行なう方法として、イオン注
入法が知られている。即ち、基板であるＳｉウェーハに
Ｂ、Ｐ、Ａｓなどの元素をイオン注入することにより、
所定の半導体接合素子を形成するのである。[Prior Art] Ion implantation is conventionally known as a method for doping by implanting a specific element into the surface of a Si wafer or the like. That is, by ion-implanting elements such as B, P, and As into the Si wafer that is the substrate,
A predetermined semiconductor junction element is formed.
［発明が解決しようとする課題］
しかしながら、従来のイオン注入法では、注入されたイ
オンが基板表面の一定の深さのところに偏って集るとい
う問題があり、必ずしも電気的特性の点で満足すべきも
のとはならなかった。そこで、注入されたイオンを均一
拡散させる処理がさらに必要となる。しかし、注入層の
みを確実に均一拡散する処理は必ずしも容易ではなく、
十分なものとはなり難かった。[Problem to be solved by the invention] However, in the conventional ion implantation method, there is a problem in that the implanted ions concentrate unevenly at a certain depth on the substrate surface, and the electrical characteristics are not always satisfactory. It wasn't what it should have been. Therefore, further processing is required to uniformly diffuse the implanted ions. However, it is not always easy to ensure uniform diffusion of only the injection layer.
It was hardly enough.
上記従来技術の課題に鑑み、本発明の目的は、Ｐ型半導
体、たとえばＳｉウェーハなどの表面に均一なミキシン
グ層を形成し、電気的に安定で優れた薄膜状のＮ型半導
体を作成することによりＰＮ接合を形成する方法を提供
することにある。In view of the problems of the prior art described above, an object of the present invention is to form a uniform mixing layer on the surface of a P-type semiconductor, such as a Si wafer, and to create an electrically stable and excellent thin film N-type semiconductor. An object of the present invention is to provide a method for forming a PN junction.
［課題を解決するための手段］
上記目的を達成するため、本発明にかかるＰＮ接合形成
法の特徴構成は、Ｐ型半導体表面上にイオンの注入と真
空蒸着を同時に行なうことにより薄膜状のＮ型半導体層
を形成する点にある。[Means for Solving the Problems] In order to achieve the above object, the characteristic configuration of the PN junction forming method according to the present invention is to form a thin N film by simultaneously performing ion implantation and vacuum deposition on the surface of a P-type semiconductor. The point is that a type semiconductor layer is formed.
このうち、Ｐ型半導体表面上に形成される薄膜状のＮ型
半導体層がＡＩＮからなるとともに、Ｎ／Ａｌが２．０
〜１５．０の比率であると、とくに好ましい
［作用・効果］
つぎに、本発明にがかるＰＮ接合形成法の作用効果を説
明する。Among these, the thin N-type semiconductor layer formed on the P-type semiconductor surface is made of AIN, and N/Al is 2.0.
A ratio of 15.0 to 15.0 is particularly preferable [Function/Effect] Next, the function and effect of the PN junction forming method according to the present invention will be explained.
本発明にがかるＰＮ接合形成法は、Ｐ型半導体表面上に
イオンの注入と真空蒸着を同時に行なうことによる。こ
のような方法として、いわゆるダイナミックミキシング
法あるいはＩ Ｖ Ｄ （Ｊｏｎ ａｎｄＶａｐｏｒ
Ｄｅｐｏｓｉｔｉｏｎ）法と称されるもの（Ｍ、 ５ａ
ｔｏｕ。The PN junction forming method according to the present invention involves simultaneously performing ion implantation and vacuum deposition on the surface of a P-type semiconductor. As such a method, the so-called dynamic mixing method or IVD (Jon and Vapor
What is called the Deposition method (M, 5a
tou.
Ｋ、Ｆｕｋｕｉ ａｎｄ Ｆ、Ｆｕｊｉｍｏｔｏ、Ｐｒ
ｏｃ、、５ｔｈ Ｓｙｍｐ、 ｌ５ＩＡＴ。K, Fukui and F, Fujimoto, Pr.
oc,, 5th Symp, l5IAT.
３４９頁）がある、この方法であると、注入イオンが特
定の深さのところで偏って集ることがない。With this method, the implanted ions do not gather unevenly at a specific depth.
即ち、この方法では、真空蒸着とイオン注入とが同時に
行なわれるので、薄膜形成の過程で蒸着原子と注入イオ
ンとが均一に混合されながら所定の厚みの薄膜が形成、
成長するのである（第２図）。That is, in this method, vacuum evaporation and ion implantation are performed simultaneously, so that a thin film of a predetermined thickness is formed while the evaporated atoms and implanted ions are uniformly mixed during the thin film formation process.
It grows (Figure 2).
同図で、１は基板を形成する原子、２は注入イオン、３
は蒸着原子である。したがって、蒸着原子と注入イオン
の混合比も一定の関係が維持されることとなる。In the figure, 1 is an atom forming the substrate, 2 is an implanted ion, and 3 is an atom forming the substrate.
is the evaporated atom. Therefore, the mixing ratio of vapor deposited atoms and implanted ions also maintains a constant relationship.
さらに、基板の表層は、蒸着原子と注入イオン及び基板
原子とが十分にミキシングされ混合層を形成するので、
基板と薄膜との密着性が極めて強固なものとなっている
。Furthermore, in the surface layer of the substrate, vapor deposited atoms, implanted ions, and substrate atoms are sufficiently mixed to form a mixed layer.
The adhesion between the substrate and the thin film is extremely strong.
蒸着原子と注入イオンの混合比は、イオン注入の条件あ
るいは蒸着条件を制御することにより、精度よく容易に
調整することができる。The mixing ratio of vapor deposited atoms and implanted ions can be easily adjusted with high accuracy by controlling the ion implantation conditions or the vapor deposition conditions.
本発明が、注入する元素の選択が容易であり、目的に応
じて各種の表層を形成することができるのみならず表層
形成元素の一部がイオン状態であることから極めて活性
であるという、イオン注入技術を利用しているので、ミ
キシングされた基板との一体性が良く、２種以上のイオ
ンをミキシングしても基板に確実に所望の金属間化合物
層を形成させることができるのである。The present invention not only allows easy selection of the element to be implanted and forms various surface layers depending on the purpose, but also has the advantage of being extremely active because some of the elements forming the surface layer are in an ionic state. Since it uses implantation technology, it has good integrity with the mixed substrate, and even when two or more types of ions are mixed, it is possible to reliably form a desired intermetallic compound layer on the substrate.
本発明による方法によれば、ＣＶＤ法によるＰＮ接合形
成法のような加熱の必要がないので、必要な熱処理を行
った後に薄膜形成処理を行うことができる。According to the method according to the present invention, there is no need for heating as in the PN junction forming method using the CVD method, so that the thin film forming process can be performed after performing the necessary heat treatment.
Ｐ型半導体表面上に形成される薄膜状のＮ型半導体層が
ＡＩＮからなるとともに、Ｎ／Ａｌが２゜０〜１５．０
の比率であると、好ましい整流特性が得られる。The thin N-type semiconductor layer formed on the P-type semiconductor surface is made of AIN, and N/Al is 2°0 to 15.0.
When the ratio is , favorable rectification characteristics can be obtained.
［実施例］
以下に、本発明にかかるＰＮ接合形成法の一実施例を、
図面を参照して詳細に説明する。[Example] An example of the PN junction forming method according to the present invention will be described below.
This will be explained in detail with reference to the drawings.
基板としては、面方位が（１００）であるＰ型Ｓｔウェ
ーハ単結晶を用い、この表面に窒化アルミニウム薄膜層
を形成する方法を例にとった。As an example, a method of forming a thin aluminum nitride film layer on the surface of a P-type St wafer single crystal with a (100) plane orientation was used as the substrate.
まず、本発明に用いたイオン注入装置について説明する
。First, the ion implantation device used in the present invention will be explained.
第１図に、本発明に用いたイオン注入装置の概略構成を
示す、この装置は、イオン源（５）として冷陰極型イオ
ン源を用い、このイオン源（５）から出たイオンは質量
分析系（６）によって注入したいイオンのみを取り出し
て試料台（１７）に載置された試料（７）に注入するよ
うになっている。したがって、予定していない不純物元
素は質量分析系（６）によってふるい分けられ、試料（
７）には不純物元素が混入しないのである。さらに、選
択したイオンの電流密度を制御することによって、試料
表層で形成される化合物薄膜の組成比を制御できるよう
になっている。FIG. 1 shows the schematic configuration of the ion implantation device used in the present invention. This device uses a cold cathode ion source as the ion source (5), and the ions emitted from this ion source (5) are analyzed by mass spectroscopy. Only the ions desired to be implanted are taken out by the system (6) and implanted into the sample (7) placed on the sample stage (17). Therefore, unplanned impurity elements are screened out by the mass spectrometry system (6) and the sample (
7) does not contain any impurity elements. Furthermore, by controlling the current density of selected ions, it is possible to control the composition ratio of the compound thin film formed on the surface layer of the sample.
図中（１４）はバルブであり、（８）は試料（７）に照
射されるイオン電流を正確に知るための追い返し電極で
、これに試料（７）における電流密度および均質な照射
領域を得るためのレンズ作用を持たせたものである０図
中（９）は、試料（７）に照射されるイオン電流を測定
するための電流積算計である。In the figure, (14) is a valve, and (8) is a repulsion electrode to accurately determine the ion current irradiated to the sample (7), and to obtain the current density and homogeneous irradiation area in the sample (7). (9) in the figure is a current integrator for measuring the ion current irradiated onto the sample (7).
他方、イオン源（５）からのイオンとともに、試料（７
）の表層に別イオンをミキシングさせるため、チャンバ
ー（ｌＯ）内に電子ビーム蒸着装置（１１）を設置しで
ある。電子ビーム蒸着装置（１１）を用いれば、蒸着速
度を電子ビーム電流の調整により容易に制御できて都合
がよい、チャンバー（１０）内には、電子ビーム蒸着装
置（１１）による試料表層の蒸着量を測定するため、石
英板を備えた水晶振動型膜厚計（１２）も設置されてい
る。これは水晶振動子の振動数変化によって蒸着膜厚を
正確に測定できるのである０図中（１３）は、チャンバ
ー（１０）内を排気するための細流分子ポンプ（図示せ
ず）に接続する排気口で・ある、もっとも、別イオンを
混合させるための蒸着装置は、上記したように電子ビー
ム蒸着装置に限られず、通常の蒸着装置であってもよい
。On the other hand, along with the ions from the ion source (5), the sample (7
) An electron beam evaporator (11) is installed in the chamber (10) in order to mix other ions into the surface layer of the sample. If the electron beam evaporator (11) is used, it is convenient because the evaporation rate can be easily controlled by adjusting the electron beam current. A crystal vibrating film thickness meter (12) equipped with a quartz plate is also installed to measure the thickness. This allows the thickness of the deposited film to be accurately measured by changing the frequency of the crystal oscillator. In the figure, (13) is an exhaust gas connected to a trickle molecular pump (not shown) for exhausting the inside of the chamber (10). However, the vapor deposition device for mixing different ions is not limited to the electron beam vapor deposition device as described above, but may be a normal vapor deposition device.
次に、上記イオン注入装置を用いて、Ｐ型半導体表面上
に薄膜状のＮ型半導体層を形成する方法を説明する。Next, a method of forming a thin film-like N-type semiconductor layer on the surface of a P-type semiconductor using the above-mentioned ion implantation apparatus will be explained.
超音波洗浄が施されたＰ型Ｓｔウェーハ単結晶をイオン
注入方向に向けて試料台に設置する。装置内を密封した
後、ターボ分子ポンプによって５Ｘ １０ ＝Ｔｏｒｒ
程度になるまで排気した。ついで、蒸着物質であるＡ１
に吸蔵されている気体分子を除去するため、基板にシャ
ッターをしたま５蒸着装置に載置されたＡＩを予備加熱
した。しかる後、Ａ１蒸着量は膜厚計で、またＮイオン
量は電流積算計で夫々調整しながらシャッターを開放し
てミキシング処理を実施した。A P-type St wafer single crystal that has been subjected to ultrasonic cleaning is placed on a sample stage facing the ion implantation direction. After sealing the inside of the device, the turbo molecular pump pumps 5X 10 = Torr.
It was evacuated until it reached a certain level. Next, A1 which is a vapor deposition substance
In order to remove the gas molecules occluded in the substrate, the AI placed on the vapor deposition apparatus was preheated while the substrate was shuttered. Thereafter, the shutter was opened and a mixing process was performed while adjusting the amount of A1 vapor deposited using a film thickness meter and the amount of N ions using a current integrator.
Ｐ型Ｓｉウェーハ上に作成したＡ Ｉ Ｎｌ膜の各種作
成条件を第１表に示す。Table 1 shows various conditions for forming the A I Nl film formed on the P-type Si wafer.
上記条件でＰ型Ｓｉウェーハ上に形成したＡＩＮ薄膜に
ついて、−１９６，２０，１００℃の各温度にて電気的
特性（電圧−電流特性）を測定した。その結果を第３図
〜第７図に示す。Electrical characteristics (voltage-current characteristics) of the AIN thin film formed on a P-type Si wafer under the above conditions were measured at temperatures of -196, 20, and 100°C. The results are shown in FIGS. 3 to 7.
いずれの試料も−１９６，２０℃の各温度においては、
顕著な整流特性を示すことがわかる。At each temperature of -196 and 20℃ for both samples,
It can be seen that it exhibits remarkable rectification characteristics.
尚、Ｐ型Ｓｉウェーハ上に形成されたＡＩＮ薄膜がＮ型
であることは、熱電効果によって確認された。It was confirmed by the thermoelectric effect that the AIN thin film formed on the P-type Si wafer was N-type.
本発明を実施するＳＬウェー八への結晶方位が、（１０
０）に限られるものでないことは言うまでもない。The crystal orientation of the SL wafer in which the present invention is implemented is (10
Needless to say, this is not limited to 0).
更に、Ｐ型半導体としてはＰ型Ｓｉウェーハに限られず
、Ｎ型半導体層としてはＡＩＮからなるものに限られる
ものではない、Ｎ型半導体層として、例えばＭｇ、Ｉ
ｎ、Ｐｂ、Ｓｎ、Ｃｄ、Ｓｂ。Furthermore, the P-type semiconductor is not limited to a P-type Si wafer, and the N-type semiconductor layer is not limited to AIN.
n, Pb, Sn, Cd, Sb.
Ａｇ、Ｃｕ、Ｎｉなどの金属原子とＮ原子とのミキシン
グ層が形成されたものからなるものであってもよい。It may be made of a layer in which a mixing layer of metal atoms such as Ag, Cu, Ni, etc. and N atoms is formed.
第１図は本発明の実施に用いたイオン注入装置の概略構
成図、
第２図は第１図の装置により基板にミキシング層が形成
される状態を示す模式図、
第３図は試料Ａの電圧−電流曲線を表す図、第４図は試
料Ｂの電圧−を流面線を表す図、第５図は試料Ｃの電圧
−電流曲線を表す図、第６図は試料りの電圧−電流曲線
を表す図、第７図は試料Ｅの電圧−を流面線を表す因で
ある。FIG. 1 is a schematic diagram of the ion implantation apparatus used to carry out the present invention, FIG. 2 is a schematic diagram showing the state in which a mixing layer is formed on a substrate by the apparatus of FIG. 1, and FIG. Figure 4 shows the voltage-current curve of sample B. Figure 5 shows the voltage-current curve of sample C. Figure 6 shows the voltage-current curve of sample B. A diagram showing a curve, FIG. 7, shows the voltage of sample E as a flow surface line.
Claims (2)
に行なうことにより薄膜状のＮ型半導体層を形成するＰ
Ｎ接合形成法。1. A thin N-type semiconductor layer is formed on the surface of a P-type semiconductor by simultaneously performing ion implantation and vacuum deposition.
N-junction formation method.
層がＡＩＮからなるとともに、Ｎ／Ａｌが２．０〜１５
．０の比率である請求項１記載のＰＮ接合形成法。2. The thin N-type semiconductor layer formed on the P-type semiconductor surface is made of AIN, and N/Al is 2.0 to 15.
．． 2. The method for forming a PN junction according to claim 1, wherein the ratio is 0.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1274280A JP2522560B2 (en) | 1989-10-21 | 1989-10-21 | PN junction formation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1274280A JP2522560B2 (en) | 1989-10-21 | 1989-10-21 | PN junction formation method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03136235A true JPH03136235A (en) | 1991-06-11 |
| JP2522560B2 JP2522560B2 (en) | 1996-08-07 |
Family
ID=17539457
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1274280A Expired - Lifetime JP2522560B2 (en) | 1989-10-21 | 1989-10-21 | PN junction formation method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2522560B2 (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS582022A (en) * | 1981-06-27 | 1983-01-07 | Agency Of Ind Science & Technol | Thin film formation |
| JPS60223113A (en) * | 1985-03-30 | 1985-11-07 | Agency Of Ind Science & Technol | Forming method of thin-film |
| JPS6212655A (en) * | 1985-07-08 | 1987-01-21 | 川崎炉材株式会社 | Carbon-containing refractory brick |
| JPH02105408A (en) * | 1988-10-13 | 1990-04-18 | Nissin Electric Co Ltd | Semiconductor device and its manufacture |
-
1989
- 1989-10-21 JP JP1274280A patent/JP2522560B2/en not_active Expired - Lifetime
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS582022A (en) * | 1981-06-27 | 1983-01-07 | Agency Of Ind Science & Technol | Thin film formation |
| JPS60223113A (en) * | 1985-03-30 | 1985-11-07 | Agency Of Ind Science & Technol | Forming method of thin-film |
| JPS6212655A (en) * | 1985-07-08 | 1987-01-21 | 川崎炉材株式会社 | Carbon-containing refractory brick |
| JPH02105408A (en) * | 1988-10-13 | 1990-04-18 | Nissin Electric Co Ltd | Semiconductor device and its manufacture |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2522560B2 (en) | 1996-08-07 |
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