JPH03135041A - Manufacture of bonding fine wire for semiconductor use - Google Patents

Manufacture of bonding fine wire for semiconductor use

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Publication number
JPH03135041A
JPH03135041A JP1273520A JP27352089A JPH03135041A JP H03135041 A JPH03135041 A JP H03135041A JP 1273520 A JP1273520 A JP 1273520A JP 27352089 A JP27352089 A JP 27352089A JP H03135041 A JPH03135041 A JP H03135041A
Authority
JP
Japan
Prior art keywords
wire
alloy
conductor
purity
alloy element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1273520A
Other languages
Japanese (ja)
Other versions
JP2708574B2 (en
Inventor
Kohei Tatsumi
宏平 巽
Takahide Ono
恭秀 大野
Tomohiro Uno
智裕 宇野
Shunpei Miyajima
俊平 宮嶋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Steel Corp
Original Assignee
Nippon Steel Corp
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Filing date
Publication date
Application filed by Nippon Steel Corp filed Critical Nippon Steel Corp
Priority to JP1273520A priority Critical patent/JP2708574B2/en
Publication of JPH03135041A publication Critical patent/JPH03135041A/en
Application granted granted Critical
Publication of JP2708574B2 publication Critical patent/JP2708574B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/741—Apparatus for manufacturing means for bonding, e.g. connectors
    • H01L24/745—Apparatus for manufacturing wire connectors
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/43—Manufacturing methods
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/43—Manufacturing methods
    • H01L2224/438—Post-treatment of the connector
    • H01L2224/43848—Thermal treatments, e.g. annealing, controlled cooling
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45015—Cross-sectional shape being circular
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554—Coating
    • H01L2224/45565—Single coating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554—Coating
    • H01L2224/45599—Material
    • H01L2224/456—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/741—Apparatus for manufacturing means for bonding, e.g. connectors
    • H01L2224/745—Apparatus for manufacturing wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
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    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
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    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]

Abstract

PURPOSE:To prevent an inclusion from being mixed and to eliminate segregation of an alloy element by a method wherein, after the surface of a conductor has been coated with the alloy element or with a high-concentration alloy, a diffusion heat treatment of the conductor is executed, the conductor is alloyed and, after that, a wire is stretched. CONSTITUTION:An ingot of a high-purity metal composed of Au, Cu, Al or the like is rolled and a wire is stretched to form an intermediate blank. The high-purity intermediate blank is passed continuously through a vapor-deposition region or inside a plating tank; and the surface of the wire is coated with an alloy element or a master alloy containing the alloy element in a high concen tration. After that, a diffusion heat treatment is executed; the coating alloy is uniformly diffused up to the central part of the wire. The wire is stretched to form a thin wire of a desired diameter. It is desirable to clean the surface of a conductor by a sputtering operation before the alloy element is vapor- deposited. Thereby, a desired characteristic of the high-purity alloy fine wire is obtained stably; and the wire can be produced with high efficiency.

Description

【発明の詳細な説明】 （産業上の利用分野） 本発明は半導体チップとリードを結ぶ半導体ボンディン
グ細線の製造法に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor bonding thin wire that connects a semiconductor chip and leads.

（従来の技術） 半導体用のボンディング細線は、従来高純度のＡｕ、Ａ
ｌ　、Ｃｕが使用されているが、最近半導体の多ピン化
に伴いボンディング線も次第に細線（２０ｔｌｎ以下）
化されるようになり、それなりの強度、伸び等の機械的
特性や接合性、ボール成形性等のボンディング特性が要
求される。これらの要求は例えば特公昭５７−３５５７
７号公報にみられるように、通常特殊な合金元素を添加
することでこれを満足するように製造される。(Prior art) Bonding thin wires for semiconductors have conventionally been made of high-purity Au, A
l, Cu is used, but recently with the increase in the number of pins in semiconductors, bonding wires are gradually becoming thinner (less than 20 tln).
As a result, mechanical properties such as strength and elongation, and bonding properties such as bondability and ball formability are required. These requirements are, for example,
As seen in Japanese Patent No. 7, it is usually manufactured to satisfy this requirement by adding special alloying elements.

細線の合金化は通常高純度素材を真空中で高周波誘導加
熱等の方法により溶解し、合金化元素あるいは合金化元
素を高濃度に含有する母合金を添加することにより行な
う。Alloying of fine wires is usually carried out by melting a high-purity material in a vacuum using a method such as high-frequency induction heating, and adding an alloying element or a master alloy containing a high concentration of the alloying element.

この方法は高純度素材を溶解するためにルツボあるいは
雰囲気からの不純物介在物の混入があり、ワイヤーの特
性を劣化させるおそれがあること、又ＡＩＩ　２０　ｉ
　＊　　Ｓ　ｔ　０２等の介在物が混入することにより
伸線中に断線することがあり、歩留りを低下させる。又
、凝固中に偏析が生じるため、ワイヤーの各部の濃度が
多少変化するため、特性、特に強度、伸びが長平方向で
バラツキを生じている。それらの改善のため、インゴッ
トを再加熱（又は溶解）し均一化する処理を行なってい
る（ゾーンレベリング）が、それでも十分とはいえない
。Since this method melts high-purity materials, impurity inclusions may be introduced from the crucible or the atmosphere, which may deteriorate the characteristics of the wire, and AII 20 i
* If inclusions such as S t 02 are mixed in, the wire may break during wire drawing, reducing the yield. Furthermore, since segregation occurs during solidification, the concentration in each part of the wire changes somewhat, resulting in variations in properties, particularly strength and elongation, in the longitudinal direction. In order to improve these problems, the ingot is reheated (or melted) and homogenized (zone leveling), but this is still not sufficient.

（発明が解決しようとする課題） 本発明は、前記した従来法の問題点を改善するものであ
り、高純度素材の純度を劣化させずに合金を添加するも
のであって、すなわち介在物の混入は全くなく、合金元
素の偏析がみられない細線への合金添加法を提供するも
のである。(Problems to be Solved by the Invention) The present invention improves the problems of the conventional method described above, and adds an alloy without deteriorating the purity of a high-purity material, that is, eliminates inclusions. The present invention provides a method of adding alloys to fine wires in which there is no contamination and no segregation of alloying elements is observed.

（課題を解決するための手段） 前記目的を達成するための本発明の要旨は次の通りであ
る。(Means for Solving the Problems) The gist of the present invention for achieving the above object is as follows.

■導体表面に合金元素あるいは高濃度合金を被覆した後
、該導体に拡散熱処理を施すことにより合金化を行ない
、その後、細線することを特徴とする半導体用ボンディ
ング細線の製造方法。(2) A method for producing a thin bonding wire for semiconductors, which comprises coating the surface of a conductor with an alloying element or a high-concentration alloy, then subjecting the conductor to alloying by subjecting it to diffusion heat treatment, and then forming the wire into a thin wire.

■導体表面を合金元素あるいは高濃度合金で被覆する前
に、スパッタリングによりクリーニングすることを特徴
とする前記■記載の半導体用ボンディングｍ線の製造方
法。(2) The method for producing a bonding m-wire for semiconductors as described in (2) above, wherein the conductor surface is cleaned by sputtering before being coated with the alloy element or the high concentration alloy.

以下本発明の詳細な説明する。The present invention will be explained in detail below.

本発明の導体は、Ａｕ、Ｃυ、ＡΩ等からなる高純度金
属であり該金属のインゴットを圧延し、伸線して０．１
〜５ｍｍの径の線（中間素材）にする。The conductor of the present invention is a high-purity metal made of Au, Cυ, AΩ, etc., and is made by rolling an ingot of the metal and drawing it into a wire.
Make a wire (intermediate material) with a diameter of ~5 mm.

この高純度中間素材（線）を蒸着領域あるいはメッキ槽
内を連続的に通過させ線の表面に合金元素あるいは合金
元素を高濃度に含有する母合金を被覆する。This high-purity intermediate material (wire) is continuously passed through a vapor deposition region or a plating bath, and the surface of the wire is coated with an alloying element or a master alloy containing a high concentration of the alloying element.

蒸着方法には、スパッタリング、イオンブレーティング
、真空蒸着に代表される物理蒸着方法、プラズマＣＶＤ
に代表される化学蒸着方法を用い、メッキは通常行なわ
れている浸漬、電解方法を採用する。被覆厚は得ようと
する合金濃度をＣ（重量パーセント）とし、高純度線の
径をｄ　（ｍｍ）、蒸着あるいはメッキする合金化元素
の被覆厚みをΔｄ　（ｍｕ）　、又、合金化元素の密度
をρ。、高純度線の密度をρ９とすると、 の関係となる合金化の濃度は高濃度になりすぎるとボー
ル硬化の要因となり、好ましくないので、０．１％以下
にするのが通常であり、すなわちｄ）Δｄであるから めの条件は として目的とする濃度Ｃが保たれるよう厚みΔｄを決定
すればよい。Vapor deposition methods include sputtering, ion blating, physical vapor deposition methods such as vacuum evaporation, and plasma CVD.
The chemical vapor deposition method typified by is used for plating, and the commonly used immersion and electrolytic methods are used for plating. The coating thickness is determined by taking the alloy concentration to be obtained as C (weight percent), the diameter of the high-purity wire as d (mm), the coating thickness of the alloying element to be vapor-deposited or plated as Δd (mu), and the thickness of the alloying element. Let the density be ρ. If the density of the high-purity wire is ρ9, then the alloying concentration has the following relationship: If the concentration is too high, it will cause ball hardening, which is not preferable, so it is usually kept at 0.1% or less, that is, d) The thickness Δd may be determined so that the desired concentration C can be maintained as the condition of Δd.

すなわち合金濃度は通常０．０００１％〜０．１％の範
囲であるのでΔｄは２．５Ｘ　ｄ　Ｘρ２×ρ、　Ｘｌ
０−’〜２．５Ｘ　ｄ　ＸρＭ／ρ。×同一４の範囲と
なる。That is, since the alloy concentration is usually in the range of 0.0001% to 0.1%, Δd is 2.5X d Xρ2×ρ, Xl
0-'~2.5XdXρM/ρ. × Same range of 4.

合金化元素が高濃度母合金として供給される場合は、合
金化元素の含有する割合に応じて被覆厚みを変化させる
必要がある。その濃度がα（％）とすると となる。When the alloying element is supplied as a high-concentration master alloy, it is necessary to change the coating thickness depending on the proportion of the alloying element contained. Let the concentration be α (%).

上式により、必要な厚さを被覆した後は拡散熱処理を行
なう。拡散熱処理により、被覆合金を線の中心部まで均
一に拡散させる。均一拡散するたＤは拡散係数であり、
ＤｏとＱが与えられれば、各温度に対して求められる。According to the above formula, after the required thickness is coated, diffusion heat treatment is performed. Diffusion heat treatment uniformly spreads the coating alloy to the center of the wire. For uniform diffusion, D is the diffusion coefficient,
If Do and Q are given, they can be found for each temperature.

ＤｏとＱは各元素特有の定数で、例えば、日本金属学会
編金属データブックあるいはＣＲＣＰｒｅｓｓ発行のＣ
ＲＣｌ１ａｎｄｂｏｏｋｏｆ’　ｃｈｅｍｉｓｔｒｙ　
ａｎｄ　ｐｈｙｓｉｃｓ等に掲載されている。Do and Q are constants specific to each element, for example, the metal data book edited by the Japan Institute of Metals or C
RCl1andbookof'chemistry
and physics, etc.

なおＲは気体係数である。ここでＫはほぼ１〜１０の間
の値の定数である。Note that R is a gas coefficient. Here, K is a constant with a value approximately between 1 and 10.

本発明において、被覆、拡散による合金化は、必要とす
る細線の線径の３〜２００倍の太いところで行ない、そ
の後仲線をして所望の径の細線とすることが好ましい。In the present invention, it is preferable that the alloying by coating and diffusion be carried out at a point 3 to 200 times thicker than the required diameter of the thin wire, and then a wire is formed to form a thin wire of the desired diameter.

最も好ましくは細線の５〜１００倍である。すなわち本
発明においては、例えば径３０−φの細線を得ようとす
る場合には、径０．１５〜３ｍ＋ａφの中間材に合金を
彼覆し、拡散処理を施してから細線することが最も好ま
しい。このようにすることによって、生産性か極めて大
となリ、細線化した後に蒸着−拡散処理をした場合に起
こる粒の粗大化を防ぐことができる。また通常は、伸線
の中間工程で中間焼鈍を行なってひずみとりをするので
あるが、中間焼鈍をすべき線径で、蒸着、拡散−熱処理
を行なうことにより、中間焼鈍を省略することができる
。Most preferably it is 5 to 100 times that of a thin wire. That is, in the present invention, when trying to obtain a thin wire with a diameter of 30-φ, for example, it is most preferable to coat an intermediate material with a diameter of 0.15 to 3 m+aφ, apply a diffusion treatment, and then form the thin wire. By doing so, it is possible to prevent the grains from becoming coarser, which would occur if the vapor deposition-diffusion treatment is performed after thinning, which greatly increases the productivity. In addition, normally, intermediate annealing is performed in the intermediate process of wire drawing to relieve strain, but intermediate annealing can be omitted by performing vapor deposition and diffusion heat treatment at the wire diameter that requires intermediate annealing. .

（実　施　例） 以下本発明を実施例に基づいて説明する。(Example) The present invention will be explained below based on examples.

第１図は本発明のクリーニング及び蒸着を行なう装置の
一例を示すもので、真空容器１中に、線２を回巻し、こ
れを繰り出すリール３と線２を巻取る巻取りリール４を
設置する。これらのリールは線２を回転しながら移送す
る機能を備えている。FIG. 1 shows an example of the cleaning and vapor deposition apparatus of the present invention, in which a reel 3 for winding and feeding out the wire 2 and a take-up reel 4 for winding the wire 2 are installed in a vacuum container 1. do. These reels have the function of transporting the wire 2 while rotating.

線２の移行領域には、繰り出し側に電極５．６を配した
クリーニングゾーンと、巻取り側にターゲット７及び電
極８を設けたスパッタリングゾーンを設けている。９は
Ａ「ガス供給管であり、１口は排気管である。In the transition area of the line 2 there is provided a cleaning zone with an electrode 5.6 on the unwinding side and a sputtering zone with a target 7 and an electrode 8 on the winding side. 9 is A's gas supply pipe, and one port is an exhaust pipe.

直径１１１１！１φの金線（純度９９．９９９％）を第
１図に示す装置を用いて連続的に回転させながら移行さ
せ、移行線２に連続的にグロー放電スパッタリングを行
なって表面を清浄にした後、大気中に出すことなくスパ
ッタリング蒸着をした。A gold wire (purity 99.999%) with a diameter of 1111!1φ was transferred while being continuously rotated using the apparatus shown in Fig. 1, and the transition line 2 was continuously subjected to glow discharge sputtering to clean the surface. After that, sputtering deposition was performed without exposing it to the atmosphere.

ターゲットには、銅＋２％ベリリウムを用い、線表面へ
の蒸着厚みが約１１００人になるように調整した。Copper + 2% beryllium was used as the target, and the thickness of the vapor deposition on the wire surface was adjusted to about 1100 mm.

スパッタリングに用いた雰囲気ガスはＡｒであり、グロ
ー放電は何れも３００〜１００ＯＶの直流電源により行
なった。The atmospheric gas used for sputtering was Ar, and all glow discharges were performed using a DC power source of 300 to 100 OV.

拡散処理は、９５０℃で４時間行なった。拡散処理後、
線の断面を研磨し、Ｘ線分析、イオンマイクロアナライ
ザーにより分析した結果、銅、ベリリウム共はぼ均一に
拡散していることが確かめられた。化学分析した結果、
銅は２１０ｐｐＩｌｌ、ベリリウムは４ｐｐｍ含有して
いることがわかった。このことは上記した式の関係が成
り立っていることを示している。この金合金線を２０−
まで伸線した後、仕上げ熱処理を行ない、この細線を用
いて半導体チップとリードとのボンディングを実施した
。The diffusion treatment was carried out at 950° C. for 4 hours. After the diffusion process,
As a result of polishing the cross section of the wire and analyzing it using X-ray analysis and an ion microanalyzer, it was confirmed that both copper and beryllium were diffused almost uniformly. As a result of chemical analysis,
It was found that 210 ppIll of copper and 4 ppm of beryllium were contained. This shows that the relationship in the above equation holds true. This gold alloy wire is 20-
After the wire was drawn to the point where the wire was drawn, a final heat treatment was performed, and the semiconductor chip and the leads were bonded using this fine wire.

ボール形成性、強度延性バランスは安定してバラツキが
なく伸線時の断線もなかった。The ball formability and strength-ductility balance were stable and uniform, and there was no wire breakage during wire drawing.

第１表に、上記組成よりなる本発明線と、同一組成の細
線を溶解法で作成し、それぞれの製造時における断線口
数と長手方向での伸びのバラツキのデーターを示す。Table 1 shows data on the number of wire breaks and the variation in elongation in the longitudinal direction when the wire of the present invention having the above composition and the thin wire with the same composition were produced by the melting method.

第１表Table 1

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の蒸着（スパッタリング）処理をする装
置の一例を示す説明図である。FIG. 1 is an explanatory diagram showing an example of an apparatus for performing vapor deposition (sputtering) processing according to the present invention.

Claims (2)

【特許請求の範囲】[Claims] （１）導体の表面に、合金元素あるいは高濃度合金を蒸
着、メッキにより被覆した後、拡散熱処理を施すことに
より合金化を行ない、その後仲線することを特徴とする
半導体用ボンディング細線の製造方法。(1) A method for producing a thin bonding wire for semiconductors, which comprises coating the surface of a conductor with an alloying element or a high-concentration alloy by vapor deposition or plating, then performing alloying by performing diffusion heat treatment, and then forming a wire. . （２）導体表面を合金元素の蒸着前にスパッタリングに
よりクリーニングすることを特徴とする請求項（１）記
載の半導体用ボンディング細線の製造方法。(2) The method for manufacturing a thin bonding wire for a semiconductor according to claim (1), characterized in that the conductor surface is cleaned by sputtering before the alloying element is deposited.
JP1273520A 1989-10-20 1989-10-20 Manufacturing method of bonding wire for semiconductor Expired - Fee Related JP2708574B2 (en)

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JP1273520A JP2708574B2 (en) 1989-10-20 1989-10-20 Manufacturing method of bonding wire for semiconductor

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US8552465B2 (en) 2011-11-09 2013-10-08 Toshiba Techno Center Inc. Method for reducing stress in epitaxial growth
US8558247B2 (en) 2011-09-06 2013-10-15 Toshiba Techno Center Inc. GaN LEDs with improved area and method for making the same
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US9159869B2 (en) 2011-08-03 2015-10-13 Kabushiki Kaisha Toshiba LED on silicon substrate using zinc-sulfide as buffer layer
US9070833B2 (en) 2011-08-04 2015-06-30 Kabushiki Kaisha Toshiba Distributed current blocking structures for light emitting diodes
US8564010B2 (en) 2011-08-04 2013-10-22 Toshiba Techno Center Inc. Distributed current blocking structures for light emitting diodes
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