JPH03132264A - Waveform distortion eliminating device - Google Patents

Abstract

PURPOSE:To eliminate ghost quickly by providing a required number of memory means capable of independent data write and read corresponding to a field period of a reference signal line for ghost detection included in a video signal. CONSTITUTION:A waveform fetch circuit 30 has line memories 32-46 being FIFO memories and the line memories 32-46 store by one horizontal line of a video signal. That is, the line memories 32-46 store reference signal line data of fields F1-F8 respectively. Thus, the line memories 32-46 capable of data write and read independently are provided corresponding to the signal period of the reference signal line and the reference signal by one period is stored respectively to the line memories 32-46. The reference signals by a prescribed field difference are read from the line memories 32-46 at any time to apply a prescribed operation, then the result is obtained quickly. Then ghost is quickly eliminated.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to video equipment such as televisions, and particularly relates to a waveform distortion removal device for removing waveform distortion such as ghosts in such equipment. It is. [Prior Art] For example, in a television video signal of the NTSC system, a reference signal for a ghost canceller is inserted into a predetermined line during, for example, a vertical retrace period. This reference signal is
As shown in Figures 3 (^) to (H), two signals, an OCR signal and a pedestal signal, are inserted into the video signal in four phases separated by four fields in field units, and the repetition period is 8 fields. It is. In the figure, (A),
fc), fE), IG) are even fields, +
8) , (DJ, '(Fl, (Old is odd field.) Here, the bar waveform that becomes the reference signal for the ghost canceller is the GCR signal Sl.
The pedestal signal S4 is an auxiliary signal for extracting the GCR signal 51 by canceling and removing the GCR signal 51 and the burst signal S3 by subtraction processing. The GCR signal signal S (indicated by rGCRJ in the diagram) is the 1st. Third,
6th. 8th fee JL, FF l', F3°F6
．． F8 respectively, and the pedestal signal S4 (indicated by rOJ in the figure) is inserted into the second.F8. 4th, 5th. 7th field F2. F4°F5. They are each inserted in F7. The burst signal S3 is also inserted into the field, and its polarity is indicated by r+J and r-J in the figure. Note that it is also added to the right of the symbols rGCRJ and rOJ. These GCR signals and pedestal signals are repeated at an 8-field period, as shown in FIG. First, for even fields, as shown in the same figure (^), the first field F1rOCR"J - the third field F
3rOCR-J-5th field F5 "0°"-7th field F7 ro-J-1st field F1 r
It is repeated in the order of OCR"J. For odd fields, 2nd field F2 rQ-J-4th field F4 "0°" 6th field F6 rGCR-"-
It is repeated in the order of 8th field F8 rGCR" J - 2nd field F2rO-1. In order to cancel the horizontal synchronization signal S2 and burst signal S3 by subtraction, the polarity of the burst signal S3 must match. Therefore, as is clear from FIG. 4, if the difference is taken between the signals separated by four fields, the horizontal synchronizing signals S2 and The bar waveforms rGcRJ and r-GCRJ in which the burst signal S3 is well canceled are extracted.Next, in order to use the bar waveforms extracted in the above manner as a reference signal for a ghost canceller, a third Figure (1
) or (J) is subjected to differential or differential processing. As a result, pulses are generated as shown in FIG. Among these, the waveform from which the leading edge of the bar waveform is also extracted becomes the reference pulse S5 for ghost cancellation. This reference pulse S5 sufficiently contains energy components up to 4 MHz. For such a reference pulse S5, for example, an in-phase ghost S6 appears as shown in ILI in the figure. here,
By subtracting the reference waveform S7 & of Ml in the figure (Ml) from the signal in (L) in the figure, the error signal sequence ε shown in the figure (N) is obtained.Ghost removal uses this error signal sequence ε, to remove the ghost. This is done by determining the delay time, amplitude value, etc., and setting the tap coefficient value of the transversal filter based on these values. Fig. 5 shows a conventional example of a ghost removal device based on this principle. In the terminal 10, a video signal from a television or the like to be subjected to ghost removal is input.The terminal 10 is connected to the input side of the filter part 12, and the output side of the filter part 12 is connected to the input side of the filter part 12. , one side is the video signal output after ghost removal, and the other side is connected to the input side of the waveform acquisition circuit 14.Next, the output side of the waveform acquisition circuit 14 is connected to the edge detection circuit 1.
6. They are each connected to the input side of the synchronous addition circuit 18. The output side of the edge detection circuit 16 is connected to a synchronous addition circuit 18. They are respectively connected to the other input side of the coefficient setting circuit 26. Furthermore, the output side of the synchronous addition circuit 18 is connected to the input side of the waveform conversion circuit 20. Next, the output side of this waveform conversion circuit 20 is connected to the input end of a subtracter 24 as well as the output side of the reference waveform output circuit 22. The output side of this subtracter 24 is connected to the input side of a coefficient setting circuit 26, and the output side of the coefficient setting circuit 26 is connected to the other input side of the filter part 12. Note that the timing generator 28 connected to the terminal IO
This will be discussed later. How to remove ghost signals included in video signals. This is done by filter part 12. The coefficient setting of this filter portion 12 is performed by a coefficient setting circuit 26. Among the above-mentioned parts, first, the filter part 12 is composed of a cyclic or acyclic transversal filter. Next, the waveform capture circuit 14 captures a reference signal portion for ghost detection present in the video signal, for example, the sixth
It is configured as shown in the figure. In the figure, a terminal 14A on the side of the filter part 12 is connected on one side to the negative input side of a subtracter 14B, and on the other side, a terminal 14A on the side of the filter part 12 is connected to a subtracter 14B via a delay circuit 14c that generates a time delay equivalent to 4 fields. is connected to the positive input side of the The output side of the subtracter 14B is a memory 1 that can store 1942 minutes of signal data.
Multiplexer 1 for signal switching connected to 4D
This multiplexer is connected to the input side of 4H.
The output side of 14H is connected to the input side of the edge detection circuit 16 or the synchronous addition circuit 18, respectively. Next, the edge detection circuit 16, for example,
or (Jl), which detects the timing of the leading edge of the GCR signal, and is configured to detect, for example, the midpoint of the front part from the maximum amplitude value position by differential processing.Next, the synchronous addition circuit Reference numeral 18 is used to time-align the signals (I or IJ) in FIG. 3 that are periodically input for each field at the timing detected by the edge detection circuit 16, and to average the signals. , thereby improving the signal-to-noise ratio of the signal. In addition, GC
If the R signal is in the same figure (Jl), the polarity is inverted and synchronous addition is performed.Next, the waveform conversion circuit 20 converts the GCR signal shown in FIG. , the reference pulse S5 as shown in the same figure (Kl) is obtained by performing differentiation or difference.This reference pulse contains information on the transmission characteristics from the transmitting side to the receiving side.Next The reference waveform output circuit 22 generates a reference waveform S7 (see the cap in the figure) in synchronization with the reference pulse S5. The error signal sequence ε1 is self-evident by subtracting the reference waveform S7 which is the output of
Based on this, the edge information detected by the edge detection circuit 16 is used to set the tap coefficient value of the transversal filter of the filter part 12. Edge information is used as a reference position. This process is often performed in a sequentially iterative manner using, for example, the following equation (1). (,l,lK+r+=ωnlx)−α
(1ε IXI...-11) However, ω1''''1 is the coefficient value updated based on the detected error signal sequence ε7, ω
1111 represents the coefficient values set before the update, and α is a constant smaller than rlJ,
It can also be changed depending on K. Next, the operation of the above conventional example will be explained. Note that the signals handled are digitized signals, but in order to make the content easier to understand, the operation will be explained in an analog manner.The sampling frequency for digitization is 1, for example, the commonly used color subcarrier frequency fsc. (approximately 3.58MHz
) is used for 4fsc. A video signal input from the outside is input to the filter part 12, and a video signal output from the filter part 12 is further input to the waveform acquisition circuit 14. That is, the signals of each field shown in FIG. 3 (Al-(Hl) are sequentially input to the waveform acquisition circuit 14. As shown in FIG. Subtraction processing is performed between the signal given a 4-field delay at 14G, and the result is shown in Figure 3 (I).
, The OCR signal shown in (J) is extracted. Since the multiplexer 14E outputs the input signal to the memory 14D only during the period when the reference signal for the ghost canceller exists, the GCR signal is written to the memory 140. When this period ends, the memory 140 becomes ready for reading, the multiplexer 14E is also switched, and the contents of the memory 14D are read out and output to the next stage. Next, the signal captured by the waveform capture circuit 14 is averaged with the output of the edge detection circuit 16 in the synchronous addition circuit 18 to improve the S/N ratio, and then input to the waveform conversion circuit 20. Ru. Then, the signal is differentiated to generate the reference pulse S5 shown in FIG. 3 IKI,
It is output to the subtracter 24. This subtracter 24 is connected to the reference waveform output circuit 22 (see FIG.
A reference waveform S7 as shown in Ml is input, and this is subtracted from the input signals of the waveform conversion circuit 20 to obtain an error signal sequence ε. In the example shown in FIG. 3, the error signal sequence ε has a waveform in which only the ghost S6 remains, as shown in FIG. 3(N), and this is input to the coefficient setting circuit 26. Next, in the coefficient setting circuit 26, the calculation of equation (1) is performed using the edge information and the values of the error signal sequence f, , and the tap coefficients of the filter part 12 are set or updated. As a result, the ghost S6 is sequentially removed. [Problems to be Solved by the Invention] However, the above conventional techniques have the following disadvantages. In other words, in the waveform acquisition method shown in Figure 6, it is necessary to provide a very long delay time of 4 fields, and the circuit capacity of the delay circuit that creates such a delay time is large, resulting in an extremely long delay time. becomes expensive. In addition, since the memory only has a storage capacity for one line of video signals, the readout time is 1 field, that is, 1 line.
/60 seconds (416,7 m5), and rapid signal acquisition is not possible. The present invention has been made in view of these points, and provides a cost-effective waveform distortion removal device that can substantially shorten signal acquisition time and quickly perform ghost removal in a short time. This is its purpose. [Means for Solving the Problems] The present invention utilizes a signal of a reference signal line for ghost removal with a predetermined field period included in a video signal,
A waveform distortion removing device for setting tap coefficients of a filter section is characterized in that a plurality of memory means capable of independently writing and reading data are provided corresponding to the field period. C Effect] According to the present invention, data is written independently. A plurality of readable memory means are provided corresponding to the signal period of the reference signal line. For example, one cycle of the reference signal is stored in each of these memory means. The reference signals can be quickly obtained by reading signals with a predetermined field difference from the memory means and performing predetermined calculations. [Embodiment 1] Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings. Note that the same reference numerals are used for the same components as in the conventional example described above. <Outline of Embodiment> First, an outline of this embodiment will be described. In this embodiment, eight line memories are used to store each of the eight field cycles shown in FIG. These memories include FIFO (First In Ftrat)
0ut) type, which allows writing and reading to be performed at independent timings. These memories contain eight repeated fields F
Since the l-F8 signal is always stored, the GCR signal can be quickly retrieved by reading out the four-field difference signal at a desired timing and performing subtraction. Even if eight FIFO memories are used, they are more cost-effective than delay circuits equivalent to four fields. <Configuration of Example> Next, the configuration of one example will be described. In Figure 1,
The configuration of the waveform acquisition circuit 30 in this embodiment is shown. In the same figure, the waveform acquisition circuit 30 is the FIFO
Each of the line memories 32 to 46 includes a memory. These line memories 32 to 46 are each capable of storing 1942 horizontal portions of data of the video signal. That is, the line memories 32 to 46 contain the reference signal line data (third
The control signals for writing data into these line memories 32 to 46 include a write clock signal WCK, a write reset signal WR3T, and a write enable signal W. E
n (n·0 to 7) is used, respectively. In addition, as control signals for data reading, read clock signal RCK, read reset signal RR3T,
Output enable signal OE. (n·0 to 7) is used. Next, each field's reference signal line data S1. (n
= 0 to 7) is, for example, 8 bits and line memory 32 to 4.
6 data input terminals DI are commonly input manually. On the other hand, the reference signal line data of each line memory 32 to 46 is output from the data output terminal DO. Then, among the reference signal line data, line memory 3
The output data of 2, 34, 36, and 38 are collectively input to the plus side of the subtracter 48. Also, among the reference signal line data, line memory 40.42.44.46
The output data of are collectively input to the minus side of the subtracter 48. As a result, the signal of any one of the first to fourth fields is subtracted from the signal of any one of the fifth to eighth fields having a four-field time difference therefrom. Which of the line memories 32 to 46 data is written to is determined by the write enable signal WE, and which line memory to read data from is determined by the output enable signal OE. Next, the write enable signal WE mentioned above. is generated by the decoder circuit 50. This decoder circuit 50 includes a
), the field information signals FSO, FS1 . F.S.
2, and a reference instruction signal GPX as shown in FIG. 101, which is at the "L" level on the line where the reference signal is inserted in each field, is manually input. The decoder circuit 50 uses these signals to perform the following (
2) The logical operation of the expression is performed, and...
+21 Write enable signals WE shown in FIG. FSl, FS2, and reference instruction signal GPX are also input to a decoder/latch circuit 52 with a latch on the output side.In this decoder/latch circuit 52, field information signals FSO, FSI, and FS2 are decoded. At the same time, it is taken into the latch on the output side at the rising timing of the reference instruction signal GPX, and the read timing signal GP
It is designed to be output as n-thickness 0 to 7). When these readout timing signals GPS are illustrated, they have waveforms as shown in FIG. 2 IP-11 to (F-8).
The period when So (see (F-1) in the same figure) is at the logical "L" level is a period corresponding to one field from time t0 when writing of the reference signal of the first field Fl to the line memory 32 is completed. ”-t+. The same applies hereafter, and the read timing signals GPS, (
The period of rLJ level of the logic value (see figure (F-8)) represents the period ty~t@ corresponding to the l field from the time ti when writing of the reference signal of the eighth field F8 to the line memory 46 is completed. ing. Next, the read timing signal GPS obtained as described above is transferred to the timing generator 28 or the control microcomputer shown in FIG.
The output enable signal 0E11 shown in -11~(G-81 or (H-11~(H-81) is generated. By the way, the FIFO memory used as the line memories 32-46 is As mentioned above, in principle, writing and reading can be performed independently, so data can be read as needed.However, it should be taken into consideration that the write signal waveform may include some jitter. Therefore, it is preferable not to read during the write operation.Therefore, in this embodiment, the following (3) is used for the normal read operation in which the read signals have a difference of 4 fields.
The output enable signal 0E11 is determined as shown in the equation and is input to the line memories 32 to 46, respectively (see FIG. 2 (G-1) to (G-8)). (3) Furthermore, as mentioned above, the FIFO memory has the function of reading at any time, so the tap coefficients of the filter part 12 can be set in a short time when necessary. If you want to quickly remove ghosts using
8), the output enable signal OE is determined. The above-mentioned data writing and reading signals are generated by a timing generator 28 (see FIG. 5) and supplied to each section. When the control section is configured with a CPU or the like, the read timing signal GPS is transferred to the control section, and the read clock signal RCK for reading is generated based on this signal. <Operation of the Embodiment> Next, the operation of the embodiment configured as above will be described. a9 Waveform capture using normal time First, the operation when waveform capture is performed using normal time will be described. As explained in FIG. 5, the video signal output from the filter part 12 is transferred to the waveform acquisition circuit 30 shown in FIG.
is input. In the line memories 32 to 46, as shown in FIG.
At the timing when the write enable signal WEn shown at -81 is at the rLJ level, the reference signal lines included in each of the first to eighth fields are written in 8 bits. That is, the write enable signal WE is rLJ
Write reset pulse signal W at the timing when it reaches the level
R3T is applied to each of the line memories 32-46, and the write counter of each memory is reset. As a result, the memory address in the line memories 32-46 is set to the first address. Therefore, the 8-bit data is sequentially written to the line memories 32 to 46 at the timing of the write clock signal WCK. In this way, the reference signals for one period shown in FIGS. Next, the reference signal data stored in the line memories 32 to 46 as described above are stored in the line memories 32 to 46 as shown in FIG.
The output enable signals OE and OE shown in FIG. 1 are rL.
Each of the signals is read out at the timing when the signal reaches the J level, and is input to the subtracter 48. That is, at the falling timing of the output enable signal OEn, the read reset pulse signal RR3T is applied to the line memories 32 to 46, and the read counters in the memories are reset. As a result, the memory address in the line memories 32-46 is set to the first address. Therefore, the stored 8-bit data is sequentially read out from the line memories 32 to 46 at the timing of the read clock signal RCK. The read data of a set of reference signal lines having a time difference of four fields is input to a subtracter 48, respectively. The subtracter 48 performs subtraction to cancel the horizontal synchronization signal and the burst signal explained in FIG.
I) or (GCR signal 5O0 (n・θ~7) shown in Jl
will be taken out. Although the overall length of these OCR signals 5O1l changes with the period of the read crotter signal RCK, basically a bar waveform similar to that shown in FIG. 3 is extracted. The GCR signal SOn extracted in the above manner is processed in the same manner as in the conventional device shown in FIG.
. is determined, and furthermore, the tap coefficients of the filter part 12 are set based on this. These operations are the same as conventional ones. b. Short-time waveform capture This capture operation is performed when necessary by using the FIFO memory's read-out function at any time. In this case, the output enable signal 0Ell is set as shown in FIG. The data read processing performed is performed during one field period from time t0 to time tl. The data write operation to the line memories 32 to 46 described above is repeatedly performed in accordance with the input of the video signal. Therefore, the line memories 32 to 46 always store the data of the reference signal lines included in the first to eighth fields shown in FIGS. 3(A) to TH). Therefore, even if data is read out in a short time at the timings shown in FIG.
R signal detection can be performed. In particular, when a CPU is used in the control system and this is used to calculate the coefficient settings of the transversal filter in the filter part 12, the shorter the time required to capture the waveform, the better. For example, the time equivalent to three shortened fields can be used for calculation time by CPLI. Therefore, in the case of sequential processing as shown in Equation 11, the time required for ghost removal is significantly reduced. <Effects of Example> As described above, this example In addition to using 8 FIFO memories that can be read at any time, the reference signal for ghost removal inserted into the video signal at the cycle of fields Fl to F8 (see Figure 3) is transmitted to each of the 8 FIFOs.
It was decided to obtain the GCR signal by storing each in the FO memory and further reading and subtracting data on reference signal lines separated by four fields at any time. Therefore, the effective waveform acquisition time is substantially shortened, and the time required for ghost removal is significantly improved. In addition, the subsequent processing by the several stages of circuits is carried out by a CPU or DSP suitable for the arithmetic processing function using the ghost removal algorithm.
It will be possible to have Uke in processors such as. This embodiment is particularly suitable for a sequential type ghost removal apparatus that captures data of a reference signal line multiple times and performs ghost removal little by little. <Other Embodiments> The present invention is not limited to the above-mentioned embodiments. For example, in the above-mentioned embodiments, the case where ghosts are mainly removed has been explained, but similar waveform distortion can also be solved in this invention. The invention is valid. Furthermore, the circuit configuration can be modified in various ways so as to achieve the same effect, and these modifications are also included in the present invention. [Effects of the Invention] As explained above, according to the present invention, a memory means capable of independently writing and reading data is adapted to correspond to the field period of a reference signal line for ghost detection included in a video signal. Since the number of these five elements is provided, it is advantageous in terms of cost, and the signal acquisition time can be substantially shortened, so that ghost removal can be quickly performed in a short period of time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a time chart showing the operation of the main parts in the embodiment, and FIG. 3 is a time chart showing a reference signal included in a video signal and its detection process. Chart, FIG. 4 is an explanatory diagram showing the characteristics of the reference signal, FIG. 5 is a circuit diagram showing a general ghost removal device,
FIG. 6 is a circuit diagram showing an example of the configuration of a conventional waveform acquisition circuit. 12--Part of filter, 14.30- Waveform acquisition circuit, 16- Edge detection circuit, 18-- Synchronous addition circuit, 20- Waveform conversion circuit, 22- Reference waveform output Circuit, 24... Subtractor, 26-... Coefficient setting circuit, 4
0...2 B-...timing generator, 32-46.
... line memory, 48 - subtracter, 50 - decoder circuit, 52 - decoder/latch circuit. Figure 1

Claims (1)

[Claims] In a waveform distortion removal device that sets tap coefficients of a filter section using a reference signal line signal for ghost removal with a predetermined field period included in a video signal, A waveform distortion removing device characterized in that a plurality of memory means capable of writing and reading are provided corresponding to the field period.