JPH03131930A - Information processor - Google Patents

Abstract

PURPOSE:To attain processing without increasing the time required for a stage by providing the information processor with a next instruction suppressing FF for suppressing the execution of an instruction in an address next to that of a branch instruction and a branched instruction suppressing FF for suppressing the execution of a branched instruction. CONSTITUTION:On the instruction execution stage of a branch instruction N, whether processing is to be branched by a branch instruction N or not is detected. Namely, a tag specified by the branch instruction N is transferred from a general purpose register group 13 to a control circuit 9 and a tag to be compared with the contents of the register group 13 from an instruction post register 6. The discrepancy of both tags is checked by a control circuit 9, and when no branch is detected, the address (N+2) of the instruction (N+2) is successively loaded from an instruction address forming circuit 8 to an instruc tion address register 1. The next instruction suppressing FF 10 and the branched instruction suppressing FF 11 are set up by the circuit 9 and the processing of the next instruction (N+1) and the processing of the instruction decoding stage of the branched instruction are suppressed by the succeeding cycle, so that the processing can be executed without increasing the stage time.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to control of an information processing device.

[Conventional technology]

In conventional information processing devices, (1) the next instruction is executed even if the branch is not taken, or (2) the next instruction is inhibited from being executed in the case where the branch is not taken, in a stage where tag matching is detected. This method suppressed the execution of the next instruction.

[Problem to be solved by the invention]

In case (1), when the conventional information processing device described above does not branch and does not want to execute the next instruction,
The next instruction must be a NOP instruction, and (2)
In the case of (
Both 1) and (2) had the problem of reduced performance.

An object of the present invention is to provide an information processing device that can perform processing without increasing stage time.

[Means to solve the problem]

The information processing device of the present invention extracts a branch destination instruction next to the next instruction, and determines whether or not the tag in the register specified by the instruction word matches the tag written in the instruction word. In an information processing device that performs execution/non-execution and branching operations, when a match of tags is detected at the tag match detection stage, the next instruction is executed as is, and then the branch destination instruction is executed. On the other hand, when a tag mismatch is detected, the next instruction inhibit flip-flop and the branch target instruction inhibit flip-flop are set, the next instruction inhibit flip-flop inhibits execution of the next instruction, and the branch target instruction inhibit The clip 70 is configured to inhibit execution of the branch destination instruction, and to take out instructions one after another and execute them starting from the instruction one after another.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

The information processing device shown in FIG. 1 has an instruction address register 1 that holds the address of an instruction in the instruction fetch stage, an instruction address register 2 that holds the address of the instruction in the instruction decode stage, and an instruction address register 2 that holds the address of the instruction in the instruction execution stage. an instruction address register 3, an instruction address register 4 that holds the address of the instruction in the instruction execution result write stage, an instruction word register 5 that holds the instruction word in the instruction decode stage, an instruction word register 6 that holds the instruction word in the instruction execution stage, An address instruction register 7 that holds the instruction word in the instruction execution result writing stage, an instruction address generation circuit 8 that generates an instruction address to be loaded into the instruction address register 1, and a control circuit 9 that controls the information processing device.
, a next instruction inhibit flip-flop (hereinafter referred to as F/F) 10 for inhibiting execution of the instruction at the next address of the branch instruction, and a branch target instruction execution F for inhibiting execution of the branch target instruction. It is composed of a memory circuit 12 into which /Fll-instruction words are written, and a general-purpose register group 13 that stores tagged data.

Next, the operation will be explained.

FIG. 2 is a timing diagram showing the operation of the information processing apparatus shown in FIG.

In Figure 2, N is a branch instruction, N+1 is an instruction placed at the address next to the branch instruction, N+2 is an instruction placed at the address next to N+1, and M is when branching occurs due to execution of branch instruction N. This is the branch destination instruction. Each instruction sequentially transitions to an instruction fetching stage, an instruction decoding stage, an instruction execution stage, and an instruction execution result writing stage.

In FIG. 2, in cycle T1, branch instruction N is in the instruction fetch stage, and address <N> pointing to branch instruction N is held in instruction address register 1. When this is transferred to the memory circuit 12, the memory circuit i12 transfers the instruction word of the branch instruction N to the instruction word register 5. The instruction word of branch instruction N is taken into the instruction word register 5 at the end of the instruction fetch stage. The branch instruction N then moves to the instruction decode stage. Also, instruction address register 1
The instruction address generation circuit 8 inputs the instruction address <N+
1> is loaded.

In the next cycle T2, the branch instruction N is loaded into the instruction decode stage, and the next instruction N+1 is loaded from the instruction fetch address generation circuit 8 into the instruction address register 1.

In the next cycle T3, the branch instruction N is in the instruction execution stage, the next instruction N+1 is in the instruction decode stage, and the branch destination instruction M is in the instruction fetch stage. At this point, it is detected whether or not to branch based on the branch instruction N. The tag specified by the branch instruction N is transferred from the general-purpose register group 13 to the control circuit 9, and the tag to be compared with the general-purpose register is transferred from the instruction word register 6. When the control circuit 9 checks for mismatch between both tags and detects that there is no branch, the instruction generation circuit 8 sequentially issues instructions N+
2 address <N+2> is loaded into instruction address register 1. The control circuit 9 also controls the next instruction inhibit F/F.
10, and branch destination instruction inhibition F/Fi1. is set.

In the next cycle T4, the branch instruction N is in the instruction execution result write stage, the next instruction N+1 is in the instruction execution stage, the branch destination instruction M is in the instruction decode stage, and the next instruction N+2 is in the instruction fetch stage. At this point, the next instruction inhibition F/F10 and branch destination instruction inhibition F/Fil are set, so the processing in the instruction execution stage of the next instruction N+1 and the processing in the instruction decode stage of the branch destination instruction are inhibited. Then, at the end of this cycle, the next instruction inhibition F/F 10 and the branch destination instruction inhibition F/Fil are reset. Further, instruction words of instruction N+2 are loaded into the instruction word register 5 from the memory circuit 12 one after another.

In the next cycle T5, the next instruction N+1 and the branch destination instruction M do not exist because they were inhibited in the previous cycle T4. One after another, instructions N+2 go to the instruction decode stage,
Furthermore, the next instruction N+3 becomes the instruction fetch stage.

Similarly below, cycle 6. In cycle T7 as well, instructions are sequentially executed.

In addition, when it is detected that the tags match and a branch is executed in the instruction execution stage of the branch instruction N, the next instruction suppression F/F,
Branch destination instruction inhibition F/F is not set, execution is N, N+
1, M, M+1.

〔Effect of the invention〕

As explained above, the present invention is advantageous in processing a branch instruction in which, when branching, the next instruction is executed and then branching, and when not branching, the branching instruction is executed one after another without executing the next instruction. When it is detected that no branch will occur at the instruction execution stage, the next instruction inhibition F/F and branch destination instruction inhibition F/F are set, and the execution of the next instruction and branch destination instruction is inhibited from those F/Fs in the next cycle. This has the effect that processing can be performed without increasing the stage time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
FIG. 3 is a timing chart showing the operation of the information processing device shown in the figure. 1 to 4...Instruction address register, 5 to 7...
...Instruction word register, 8...Instruction address generation circuit, 9...Control circuit, 10...Next instruction inhibit flip-flop (F/F), 11... ...
Branch destination instruction inhibit flip-flop (F/F), 12...
...Memory circuit, 13...General-purpose register group, N
...Branch instruction, N+1...Next instruction, M
...Branch destination instruction, N+2 to N+5...
Instructions after one instruction after another.

Claims (1)

[Claims] The branch destination instruction is taken out after the next instruction, and the execution/non-execution of the next instruction is performed depending on whether the tag in the register specified by the instruction word matches the tag written in the instruction word.
In an information processing device that executes a branch operation, when a tag match is detected at the tag match detection stage, the next instruction is executed as is, and then the branch destination instruction is executed, and conversely, the tag mismatch is executed. is detected, a next instruction inhibit flip-flop and a branch target instruction inhibit flip-flop are set, the next instruction inhibit flip-flop inhibits execution of the next instruction, and the branch target instruction inhibit flip-flop inhibits execution of the branch target. An information processing device characterized by inhibiting execution of instructions, extracting instructions one after another, and executing the instructions one after another.