JPH03131784A - Transmitter-receiver - Google Patents

Abstract

PURPOSE:To enhance high-speed pulse driving performance without increasing power consumption by connecting the gate of a transistor on a high voltage side to the potential point of a 2nd potential which is lower than a 1st potential by a specified value through a diode having the excellent characteristic of reverse recovery time. CONSTITUTION:A pulse current is supplied by the transistor 8, and consequentially the p-ch transistor 3 connected to the high voltage HV side is driven. At such a time, when the value of the pulse current is high enough, the charge of the gate capacity of the p-ch transistor is performed at a high speed and high-speed turn-on characteristic is obtained. Before the charge of the gate capacity of the transistor 3 by the pulse current exceeds the breakdown strength of the gate, the potential is clamped to the 2nd one through the diode connected to the gate. At such a time, and excess part of the pulse current is bypassed to a 2nd potential circuit through a clamp diode 7 and the high-speed driving which does not exceed the breakdown strength is accomplished in the gate of the p-ch transistor.

Description

[Detailed description of the invention]

(Industrial Application Field) The present invention relates to a transmitting/receiving circuit in an ultrasonic diagnostic apparatus or the like, and particularly to a transmitting/receiving circuit suitable for integrating a large number of circuits.

[Prior art 1] FIG. 2 shows a conventional example of a pulse driver that supplies high voltage pulses to a load 5. Here, the output stage is p-channel (p-
ah) 3 and n-channel (n-ch) 4 high withstand voltage M
Connect the OS/FETs in a complementary manner, and connect 100 to the power line 10.
A voltage of ~100 volts is applied. The input pulse signal is applied to the terminal 400, and a predriver 41 provides a driving pulse to the output stage element 3.4. Here, the N-ch element 4 is turned on when the gate has a positive potential equal to or higher than a certain threshold value with respect to the source, while the P-ch element 3 is turned on when the gate has a negative potential equal to or higher than a certain threshold value with respect to the source. At this time, since each of the above elements has an input capacitance between the gate and source, in order to perform on/off operations at high speed, it is necessary to charge and discharge the capacitance at high speed. Here, the pulse amplitude of the input terminal 400 is a normal logic circuit output, and is, for example, about 5 square meters. On the other hand, the load driving element 3
．． The above potential applied to the gate of No. 4 is required to be, for example, 8 to 15V. Further, it is necessary to apply a pulse whose potential is 8 to 15 V lower than the potential of the power source t@io to the gate of the p-ah element 3. A predriver 41 is used for this purpose. An output 410 of the predriver 41 is connected to the gate 300 of the p-ah element 3 through a capacitor 71. If the input 400 of the pre-driver 41 is now at the II L" level, the output 410 is at the II H" level. If this is V and Vth is the above-mentioned threshold value, then V>Vth, the n-ch element 4 is turned on. At this time, capacitor 71 is charged through resistor 61. Assuming that the voltage of the power supply line 10 is VH, the potential of the point 300 at the time of the above charging is VH, and the voltage of the capacitor 71 is VH-V. Therefore, the voltage between the gate 1 and the source of 3 is turned off at Ov. Next, when a pulse of width T"H" is applied to the input of 400, the output 410 becomes @T II L". Therefore, n-c
The h-element 4 is turned off for a period T. If the time constant of the circuit consisting of the capacitor 71 and the resistor 61 is sufficiently larger than the pulse width T, the potential at the point 300 drops to VH-V. Therefore, the p-ch element 3 is turned on for a period T, and a pulse having a width T and an amplitude substantially equal to the power supply voltage is supplied to the load 5. As mentioned above, the capacitor 71 does not depend on the value of the power supply VH,
A gate drive pulse of a predetermined amplitude (■ in the above example) can be applied. However, as is clear from the above description of the operation, the capacitor 71 requires a withstand voltage higher than VH, and its capacitance has a considerably large value compared to T in order to obtain a sufficiently long time constant. For example, about 10,000 pF is required for T=500 ns, and when implementing the circuit including the driver shown in FIG. 2 into an IC, there is a problem in that it is difficult to integrate the above-mentioned high-withstand-voltage, large-capacity capacitor. In particular, when the above driver is used as a driver for an array of several -10 to several 100 transducers, such as in an ultrasonic diagnostic device, the circuit shown in FIG.
Since 0 to several 100 are required, the above point becomes a big problem. On the other hand, as a front driver circuit that does not require a high-voltage, large-capacity capacitor, the configuration shown in FIG. 3 can be considered. That is, in FIG. 3, a p-ch element 62 is used in place of the resistor 61 in FIG.
A pulse current synchronized with the input pulse to 0 is applied. However, it is difficult to reliably maintain this current value within a predetermined range, considering the characteristics of the element and its fluctuations. Therefore, it is necessary to reduce the potential at point 300 to below the gate breakdown voltage of elements 3 and 62 under the worst case condition of the above conditions. Guaranteed under standard conditions will result in insufficient operating capacity, speed, and delay time. There is a problem in that performance such as drive ability cannot be fully demonstrated. There is also a circuit in which a Zena diode is connected in parallel between the gate and source for the purpose of protection from overvoltage. In order to use a Zena diode for the above purpose, an element with a large current capacity is required because all the remaining current after supplying the charge necessary to turn on the target transistor flows through the Zena diode. Furthermore, when integrating the driver circuit in multiple channels, a Zener diode for protection is required for each target transistor of each channel, resulting in a large scale circuit. In addition, as a prior art related to the present invention, "IEICE Technical Research Report ED83-7 (1983), 5
There are reports such as "pages 1-58". (Problem to be solved by the invention) The above conventional technology guarantees the gate active capacity (gate-source capacitance charge/discharge current) and gate breakdown voltage conditions of the transistor, and facilitates high-speed, multi-channel integration with a high power supply voltage. Therefore, it is an object of the present invention to provide a high-speed pulse drive characteristic, that is, a sufficiently fast rise and
The object of the present invention is to provide a circuit means that supplies a drive current having falling characteristics while guaranteeing conditions such as gate breakdown voltage, consumes less power, and is suitable for multi-channel integration. It is especially suitable for driver circuits called complementary type or totem pole type, and when these are integrated into multiple channels,
The object of the present invention is to obtain an optimal circuit means when there are few channels operating simultaneously. A second object of the present invention is to supply the above-mentioned pulses to a load device as disclosed in Japanese Patent Application No. 6O-2236O9, Japanese Patent Application No. 61-164827, etc., and at the same time generate a signal from the load side, such as a continuous or intermittent analog signal. The object of the present invention is to obtain a circuit means that includes a reception port and a path means as a part of the driver. Furthermore, a third object of the present invention is to apply it to, for example, an ultrasonic diagnostic device, a flaw detection device, or another device having a phased array transducer, and to supply high voltage and high speed pulses to the multi-channel transducer. The object of the present invention is to obtain a wave transmitting/receiving device having means for receiving signals from the transducer. [Means for Solving the Problems] In order to achieve the above object, the present invention connects the gate of the high voltage side transistor to the high voltage (first potential)
It is connected to a point at a second potential that is lower by a predetermined value. The potential difference between these first and second potentials is set to be equal to or lower than the gate breakdown voltage of the transistor. As a means for obtaining the second potential, it is optimal to use a Zena diode or the like. That is, one end of the Zena diode is connected to the high voltage HV, the other end is set as a second potential point, and one of the diodes of each driver circuit is connected. Each driver circuit has a pulse current supply means sufficient for high-speed charging and discharging. This may be a pulse current supply circuit similar to the transistor 8 in the conventional circuit shown in FIG. 3, but its current value should be large enough for high-speed charging and discharging. As mentioned above, the means for obtaining the second potential in the present invention is as follows:
- for multiple driver circuits. [Operation] The operation of the driver circuit according to the present invention is almost the same as that of the conventional example shown in FIG. A pulse current is supplied by the transistor 8, so that the p
-ch transistor 3 is driven. At this time, if the pulse current value is sufficiently large, the gate capacitance of the P-ch transistor is charged at high speed, and high-speed turn-on characteristics can be obtained. Here, before the gate capacitance of the transistor is charged by the pulse current and exceeds its gate breakdown voltage, it is clamped to the second potential by a diode connected to the gate. At this time, the excess portion of the pulse current is bypassed to the second potential circuit through the clamp diode 7, so that the gate of the P-ch transistor can operate at high speed without exceeding the withstand voltage. Furthermore, since the bypass current flowing through the clamp diode flows only during pulse drive, no extra power is consumed during non-drive.

【Example】

Embodiments of the present invention will be described below with reference to FIG. In FIG. 1, reference numeral 100 denotes a pulse driver circuit, which is connected in parallel to a first potential power line 1o connected to a power source 1, and supplies a pulse voltage to each load 5. The load 5 is, for example, a transducer for transmitting and receiving ultrasonic waves, and transmits ultrasonic waves by driving with the above pulses. transistor 3,
4 are complementary connected pen channel transistors (MOS-FETs), and a transistor 8 and a resistor 6 constitute a predistortion circuit for driving the p-ah transistor 3. The gate of the p-ch transistor 3 of each driver circuit is connected through a diode 7 to a power supply line 20 at a second potential. The second potential is obtained by the Zena diode 2 in this embodiment. This Zener voltage is lower than the gate breakdown voltage of the P-ch transistor. Further, a capacitor 200 or a resistor 201 may be connected to the second power supply line 20. The operation shown in FIG. 1 will be explained in detail with reference to FIG. 4. From time to to tl
A case is shown in which pulses are supplied to the load 5 for the period up to . Transistors 4 and 8 are shown in Fig. 4vg (4) respectively.
, Vg(8) is applied. That is, until 1<10, transistor 4 is on, transistor 8 is off, therefore transistor 3 is also off, and the potential of load 5 is O. When the Vg (4), Vg (8) (7) drive pulses are applied at time to, transistor 4 turns on and off, while transistor 8 turns on during off. As a result, the drain current Id(8) of the transistor 8 gradually increases as shown in FIG. 4, and reaches a saturation current determined by Vg(8) and the characteristics of the transistor 8, or a current value determined by the load conditions of the resistor 6, etc. . According to this, transistor 3
The gate potential Vg(3) of is equal to the first potential Vg(3) when 1<10.
It gradually decreases from H due to the voltage drop across the resistor I6 due to the above current, but when the value of this voltage drop reaches the zener voltage Vz of the zener diode 2, any further current flows through the zener diode side through the diode 7 and Vg (3) is the second
It is clamped to the potential of VH-Vz. The gate-source voltage of transistor 3 is Vgs.
(3) does not exceed Vz, and by selecting Vz below the gate withstand voltage, the transistor 3 will not be destroyed by excessive gate voltage regardless of the values of Id (8) and the resistor 6. 1(7) in Fig. 4 is the current flowing through the diode 7, which is rd(
The current corresponds to the hatched part in 8). As a result of the above operation, the gate potential Vgs(3) of the transistor 3 becomes as shown in FIG.
Figure 4 V. A pulse with a voltage of <VH is supplied as shown in FIG. As is clear from the above description, in order to speed up the turn-on of the I-transistor 3, it is necessary to shorten the time for Vgs (3) to reach the threshold value. However, in the conventional circuit, Id(8
Even if an attempt is made to achieve this condition by increasing the value of ), the final value of Id(8) must be within a range where Vgs(3) does not exceed the gate breakdown voltage, and sufficient speed-up cannot be achieved. In the present invention, since the excess current of Id(8)- flows through the Zena diode side, the above-mentioned withstand voltage condition and high speed condition of Vgs(3) can be selected independently. In other words, even if the value of Id(8) is increased to increase speed, Vg
s (3) will not lose its withstand pressure. However, since the current Id(8) is applied only during the period of the output pulse width, for example, when the duty ratio of the output pulse is very small, such as in a transducer for an ultrasonic diagnostic device (for example, 1/1
000 or less), driver circuit 1 by increasing Id(8)
The increase in power consumption at 00 can be made sufficiently small. Furthermore, even when a large number of pulse drivers 100 are connected as shown in FIG. 1, the part that obtains the second potential, such as the Zena diode 2, may be -. Here, when a plurality of drivers simultaneously supply pulses to the load 5, the current flowing through the Zener diode 2 becomes the sum of the currents shown in FIG. 4 (7) in each driver circuit 100. Therefore, if there is no or little overlap in the operation timings of the drivers 100, it is particularly effective to integrate a large number of driver circuits without increasing the elements or power consumption. FIG. 5 shows a second embodiment in which the second power source is taken out from a point in the middle of the first power source. Other parts and operations are similar to those in FIG. 1. FIG. 6 shows a third embodiment in which the circuit section of the transistor 8 is changed from FIGS. 1 and 5. In FIG. Here, transistors 82 and 83 are connected in series, a bias power supply 80 is applied to the gate of 83, and a pulse similar to that in FIG. 5 is applied to the gate of 82. In this embodiment, the transistor 83 to which a constant bias is applied does not switch, and only the series-connected transistor 82 switches in accordance with the input pulse. The drain-source breakdown voltage of the transistor 8 shown in FIGS. 1 and 5 must be higher than at least the first power supply VH. - Although the transistor 83 in FIG. 6 requires the same breakdown voltage as above, the transistor 82 may have a low breakdown voltage. Further, the value of Id(8) in FIG. 1 is determined by either transistor 82 or 83. For example, the bias power supply 80 can be controlled to an optimal value based on the electric g voltage, allowable current value, temperature conditions, and the like. Further, the bias power supply 80 can be shared by a plurality of similar drivers. FIG. 7 shows a fourth embodiment in which the present invention is applied to a different type of front drive circuit. Furthermore, FIG. 8 shows a fifth embodiment in which the transistor 4 in FIG. 1 is applied to a driver circuit 101 that is shared by a plurality of circuits. Here, multiple times, l@1
The transistor 4 is common to 01, but a diode 40 is added to each. FIG. 9 shows a sixth embodiment in which the present invention is applied to a circuit called a totem pole type. Here, p-c in FIG.
In place of the hi-transistor 3, a p-ah transistor 30 and an n-ch transistor 33 are combined, and a diode 34 is added. In the embodiment of FIG. 9, the input pulse to the transistor 8 does not necessarily need to be applied for the same period as the output pulse width, as shown in the explanatory diagram of FIG. That is, even if the i-transistor 30 is turned off before time t1 of the trailing edge of the output pulse, the transistor 33 remains on as long as the gate-source voltage does not fall below the threshold. Particularly when the load 5 has strong capacitive properties such as an ultrasonic transducer, this effect makes it possible to further reduce the power consumption due to the short on period of the transistor 8<LId (8). For this purpose, V in Fig.
This can be easily achieved by setting the drive pulse shown in g (8) to Vpol 1 at to, but setting it to 0 volts before Ll (shown by the broken line in Figure 4 Vg (8), at this time Id
(8) and i (7) are also indicated by the broken lines in the figure). The present invention is particularly effective when applied to a device in which a large number of drivers are integrated, such as a transmission driver for a transducer array in an ultrasonic device. For example, patent application No. 60-223609. It can be applied to Japanese Patent Application No. 61-164827, Japanese Patent Application No. 62-273048, etc. to obtain remarkable effects. FIG. 10 shows such an embodiment. [Effects of the Invention] According to the present invention, the high-speed pulse drive performance can be further enhanced without increasing power consumption by applying it to various circuits having driver functions in complementary type or Totenball type circuit formats. . Furthermore, since the above function can be obtained by adding common circuit means to a plurality of the above driver circuits, it is particularly effective when a large number of drivers are integrated. This effect can be remarkable in a device that uses a large number of wave transmitting/receiving circuits and has a small pulse drive duty ratio, such as a wave transmitting/receiving device of an array transducer in an ultrasonic diagnostic apparatus.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the main parts in an embodiment of the present invention, FIGS. 2 and 3 are circuit diagrams of the conventional system, FIG. 4 is a pulse timing diagram showing the operation of the circuit of the present invention, and FIG. FIG. 6, FIG. 7, FIG. 8, FIG. 9, and FIG. 10 are circuit diagrams showing other embodiments of the present invention. Explanation of symbols 1... High voltage power supply 2... Zena diode 3.4... Output stage transistor 5... Load 7... Diode 8... Front drive stage 10... First potential 20...Second potential 100.101,102...Driver circuit 4tEa Fig. 2 Fig. 3 Fig. 4θθ 1 Fig. 4 Fig. S Fig. C Fig. 1 Fig. 10

Claims (1)

[Claims] 1. The source of the P-channel MOS/FET is connected to a first potential, a resistance or an element having a resistive function is connected between the source and the gate, a load is connected to the drain, and a pulse is applied to the gate. In a switch circuit connected to a current supply means, a diode is connected to the gate at a second potential with a polarity such that the gate side becomes a cathode, and the potential is connected to the FET.
A transmitting/receiving device characterized in that the voltage is set lower than the source-to-gate breakdown voltage of the transmitter/receiver. 2. The source of the n-channel MOS/FET is connected to a reference potential, the drain is connected to the drain of the p-channel FET according to claim 1, and the related control signal is connected to the gate from the pulse current supply means according to claim 1. 2. The transmitting/receiving device according to claim 1, wherein the p-channel and n-channel FETs provide a complementary output configuration and operation. 3. A constant voltage diode having a Zener voltage lower than the source-gate breakdown voltage of the p-channel FET is used as the means for obtaining the potential difference between the first and second potentials. transmitting and receiving equipment. 4. The transmitting/receiving device according to any one of claims 1, 2, and 3, wherein means for obtaining the first and second potentials is commonly used for a plurality of transmitting/receiving circuits. 5. n to the p-channel FET in the output stage of the above transmitter/receiver circuit.
5. The transmitting/receiving device according to claim 1, wherein the transmitting/receiving device has a totem pole type circuit configuration by adding a channel FET and a diode. 6. Claim 4, characterized in that the pulse width of the pulse current supply means is shorter than the pulse width supplied to the load.
Transmitting/receiving device as described in section. 7. An ultrasonic diagnostic apparatus characterized in that a transmitting/receiving circuit according to any one of claims 1 to 6 is provided for each element of a transducer array for transmitting and receiving ultrasonic waves. 8. The ultrasonic diagnostic apparatus according to claim 7, wherein a plurality of reception outputs are commonly connected and extracted for reception signals corresponding to the plurality of transducers.