JPH03129909A - Output buffer amplifier - Google Patents

Abstract

PURPOSE:To output a voltage of a low impedance at the time of output, and also, to realize an analog input/output combined terminal for exerting no influence on an internal circuit such as a buffer, etc., by connecting a switch between a gate terminal of a MOS transistor for constituting an output stage of an output buffer amplifier and a power supply voltage terminal. CONSTITUTION:A switch S1 consisting of a MOSFET, and a switch S2 are connected between a transistor M1 for constituting an output stage 2 and a power supply voltage terminal VCC, and between a transistor M2 and a power supply voltage terminal VSS, respectively. When an input/output switching control signal C is fixed to a low level, the switch S2 is turned off, and the switch S1 is turned on. Accordingly, a buffer amplifier outputs a voltage corresponding to an internal reference voltage Vref of a low impedance. When the control signal C is varied to a high level, the switch S2 is turned on, and the switch S1 is turned off. Accordingly, an output buffer is not influenced at all.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is applicable to semiconductor integrated circuit technology and analog MO8
Regarding technology that is particularly effective when applied to LSI input/output circuits,
For example, the present invention relates to a technique that is effective when one terminal is used for both input and output in an LSI having a built-in A/D and D/A converter, such as an LSI for audio communication.

[Prior art] In I and SI devices with built-in filters, such as voice communication LSIs, the filter section is constructed from a digital circuit such as a DSP (digital signal processor), and A/D conversion is performed on the input and output sides. A device is provided in which a circuit and a D/A conversion circuit are provided and these are integrated into one chip.

[Problems to be Solved by the Invention] For example, a telephone exchange is configured by combining the above LSI with another LSI having functions such as connection and disconnection of lines. In this way, when configuring a system by combining an LSI and other LSIs, there are cases where it is desired to use the reference voltage (analog GND) generated inside the voice communication LSI in other LSIs, and such LSIs have An analog output terminal that outputs a specific voltage may be required.

An analog input terminal may be required to apply a predetermined voltage from the outside during power, aging, or debugging. However, if new terminals are provided only for such tests, the package becomes larger than necessary.

Therefore, the inventors thought of using one terminal for both analog output and input, and created an output buffer B as shown in Figure 2.
We considered a method in which a switch S made of a MOSFET or the like is connected between A and an external terminal T, and the switch is turned on when used as an output terminal, and turned off when used as an input terminal.

However, in the input/output switching method using the above switch, a MOS F is connected between the buffer BA and the terminal T.
It has been found that since the on-resistance of the ET is involved, there are problems in that the output voltage level changes depending on the output current and the analog characteristics of the internal circuit deteriorate.

An object of the present invention is to provide a semiconductor integrated circuit technology that can output a low impedance voltage when outputting, and can realize an analog input/output terminal that does not affect internal circuits such as buffers when inputting. It is in.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

That is, instead of inserting a switch between the output buffer amplifier and the external terminal, a MOS transistor M constituting the output stage of the output buffer amplifier BA as shown in FIG.
l, M2 gate terminal and power supply voltage terminal Vc, c, Vss
switch 31 in between. When S2 is connected and used as an input terminal, the switches Sl and S2 are turned on, and when used as an output terminal, the switches Sl and S2 are turned on.

[Operation] According to the above-described means, since there is no resistance between the output buffer amplifier and the external terminal, it is possible to output a low impedance voltage, and the gate terminals of the output transistors Ml and M2 and the power supply voltage By turning on the switches Sl and S2 between the terminals, the output transistor M
1 and M2 are cut off, the output node n of the output buffer amplifier is placed in an output high impedance state, and voltage can be supplied from the outside to the input/output terminal.

[Embodiment] Fig. 3 shows an example in which the present invention is applied to an LSI for voice communication in which a reference voltage Vre f generated by an internal reference voltage generation circuit and supplied to an A/D converter and a D/A converter is supplied to the outside of the LSI. One embodiment is shown when applied to an output buffer amplifier.

In FIG. 3, l is a MOS transistor M11 to M1.
5, Ml l and Ml2 are input differential transistors whose source terminals are commonly connected to each other,
Ml3. M14 is an active load transistor connected between the drain terminals of transistors M11 and M12 and power supply voltage Vce, and transistors M13 and M14 are connected in a current mirror.

Ml5 is an input differential transistor Ml1. This is a constant current transistor connected between the common source terminal of Ml 2 and the power supply voltage terminal Vss. A constant voltage VGG can be applied to the gate terminal of the transistor M15 via the switch MO3.

The output node of this differential amplifier stage 1, that is, the connection node n between the input differential transistor M12 and the load transistor M14
, are connected to the gate terminal of the output transistor M1 constituting the output stage 2.

A constant voltage VGG, which is the same as the gate voltage of the constant current transistor M15, can be applied to the gate terminal of the transistor M2 via the switch 3.

In the buffer amplifier of this embodiment, a reference voltage Vref such as 2.1V generated by an internal reference voltage generation circuit 4 is applied to the gate terminal of the input differential transistor M12.
The voltage at the output node n of the output stage 2 is fed back to the gate terminal of the other input differential transistor M11, thereby functioning as a voltage follower that performs impedance conversion.

In this embodiment, the transistor Ml constituting the output stage 2
A switch Sl consisting of a MOSFET is connected between the transistor M2 and the power supply voltage terminal Vss.
A switch S2 is connected between them. This switch S2
is turned on and off by the input/output switching control signal C, and the switch S between the switch S1 and the bias circuit 3
3 is controlled on/off by a signal obtained by inverting the control signal C by an inverter INV. and,
An input buffer 5 can be connected to an external terminal T connected to an output node n of the output stage 2.

In the output buffer amplifier configured as described above, when the input/output switching control signal C is fixed at a low level, the switches Sl and S2 are turned off and the switch S3 is turned on. Therefore, the constant voltage VGG generated in the bias circuit 3 is supplied to the gate terminals of the transistors M15 and M2, causing them to act as constant current sources. Therefore, the buffer amplifier outputs a voltage corresponding to the internal reference voltage Vref with low impedance.

On the other hand, when the control signal C is changed to a high level, the switches Sl and S2 are turned on, and the switch S3 is turned off. Therefore, the gate-source voltage of the MOS transistors M1 and M2 constituting the output stage 2 becomes zero and is turned off, and the output node n becomes in a high impedance state. Therefore, even if an external reference voltage vR is applied to the terminal T from the outside at this time, the output buffer amplifier BA is not affected at all. The input voltage VR is supplied to the internal A/D converter etc. via the input buffer 5. Note that, although not particularly limited, even when the external terminal T is used as an output terminal, the internal reference voltage Vref is supplied to a desired internal portion via the input buffer 5.

In the above embodiment, the buffer amplifier is activated by providing the switch S3 between the gate terminals of the constant current transistor M15 and the output transistor M2 and the bias circuit 3 to supply or cut off the bias voltage VGG. However, the control signal C may be directly supplied to the bias circuit 3 and controlled so that the bias voltage VGG itself is not output when it is input.

In this way, switch S3 can be omitted.

Further, the input/output switching control signal in the above embodiment may be generated by an internal test mode control circuit or the like, or may be provided from the outside. If a control signal is given externally, a terminal is required for that purpose, so it may not be possible to reduce the number of pins, but LSIs with multiple input/output terminals as described above Since the control signals can be shared, the total number of bins can be reduced.

As explained above, in the above embodiment, instead of inserting a switch between the output buffer amplifier and the external terminal, the output transistor Ml constituting the output stage as shown in FIG.
Switches SL and S2 are connected between the gate terminal of M2 and the power supply voltage terminals Vcc and Vss. When using it as an input terminal, turn on the switches SL and S2, and when using it as an output terminal, turn on the switches SL and S2. Since it is turned on, there is no resistance between the output buffer amplifier and the external terminal, so it is possible to output a voltage with low impedance, and the output transistor M
l, switch Sl between the gate terminal of M2 and the power supply voltage terminal
, S2 is turned on, the output transistors Ml and M2 are cut off, the output node n of the amplifier is put into an output high impedance state, and a voltage can be supplied from the outside to the input/output terminal. be.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the buffer amplifier of the above embodiment, the Vss side transistor M2 of the output stage is driven with the same voltage as the voltage supplied from the bias circuit 3 to the constant current transistor M15, but the output voltage of the differential amplifier stage is Alternatively, it is also possible to drive it with a level-shifted voltage.

In the above explanation, the invention made by the present inventor was mainly applied to an LSI configured with a 0M08 circuit, which is the background field of application, but the present invention is not limited thereto. It can be used not only for LSIs made up of circuits, but also for LSIs with built-in analog circuits.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

That is, it is possible to realize an analog input/output terminal that can output a low impedance voltage when outputting and does not affect internal circuits such as buffers when inputting.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing the basic concept of the present invention, Figure 2 is a circuit diagram showing an example of the configuration of a conventional input/output terminal, and Figure 3 is a diagram of a buffer amplifier to which the present invention is applied and its output terminal. FIG. 2 is a circuit diagram showing an example. l...differential amplification stage, 2...output stage, 3...
Bias circuit, Ml...first output transistor,
M2... Second output transistor, 7... External terminal (input/output terminal), S1-S3... Switch first
Illustration.

Claims (1)

[Claims] 1. A differential amplifier stage and its bias circuit, and two MO
An output buffer amplifier comprising an output stage in which S transistors are connected in series between power supply voltage terminals and driven by the output voltage of the differential amplification stage, and an output terminal of the output stage is connected to an external terminal. 1st MO of output stage
Switch elements are connected between the gate terminal of the S transistor and the first power supply voltage terminal of the circuit, and between the gate terminal of the second MOS transistor of the output stage and the second power supply voltage terminal of the circuit, and these switch elements An output buffer amplifier characterized in that the circuit is activated when the circuit is turned off, and the output terminal is placed in a high impedance state when the circuit is turned on. 2. A third switching element is provided between the bias circuit and the differential amplifier stage, and the third switching element is controlled to be turned on and off in a complementary manner to the first and second switching elements. 2. The output buffer amplifier according to claim 1, wherein the output buffer amplifier is configured as follows. 3. The output buffer amplifier according to claim 1 or 2, wherein the second MOS transistor constituting the output stage is configured to be biased by a constant voltage supplied from the bias circuit.