JPH03129544A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To make it unnecessary to prepare a circuit or the like for inhibiting access to a memory part in an electronic apparatus by constituting the semiconductor storage device to access the memory part only when an address specified by the electronic apparatus is the one set up as a using address. CONSTITUTION:When there is an overlapped part between the addresses of the memory part 6 and the addresses of a memory 6 built in the electronic apparatus 1, unoverlapped addresses are set up using addresses so as to inhibit the overlapped addresses in the memory part 2 from being accessed. Namely when the electronic apparatus 1 specifies one of the overlapped addresses, the memory 6 built in the electronic apparatus 1 is accessed. Thereby, it is unnecessary to prepare a circuit or the like for inhibiting access to the memory part 2 in the electronic apparatus 1.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Field of Application Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems...Fig. 1 Functional Embodiment First Embodiment...Fig. 2 Structure of the first embodiment Operation of the first embodiment Effects of the first embodiment Second embodiment...Figure 3 Third embodiment...Figure 4 Other effects of the invention [Summary] Electronic devices such as IC memory cards, etc. Regarding a semiconductor memory device used as an external storage device, the addresses of the memory section are divided into used addresses and unused addresses, and unused addresses are made inaccessible and addresses are changed as necessary. The purpose is to enable wide use in various electronic devices that have built-in memory, and to set the memory section used by the electronic device and the address to be used for the memory section, and to display the address to be used. a used address setting/used address display code output unit for outputting a used address display code to output a used address display code; and a specified address/used address display for comparing part or all of the address specified by the electronic device with the used address display code. A code comparison section is provided so that the memory section can be accessed only when the address designated by the electronic device is the address set as the address to be used! R command.

[Industrial Field of Application] The present invention relates to a semiconductor storage device used as an external storage device for electronic equipment, such as an IC memory card.

For example, when using an IC memory card, it is necessary to ensure that the address of the IC memory card does not overlap with the address of the built-in memory of the electronic device that uses the IC memory card. . In other words, if there is an overlap between the address provided by the IC memory card and the address provided by the memory built into the electronic device, erroneous writing or reading may occur unless only one of the addresses is accessed. This may lead to system malfunction.

[Prior Art] Conventionally, an IC memory card has been proposed in which usable addresses are written as data in its memory section.

When this IC memory card is used, the above-mentioned data is read out by the central processing unit (hereinafter referred to as CPU) built into the electronic device, and the address of the IC memory card and the memory built into the electronic device are read out. If there is an overlap between the addresses provided in the electronic device, an attempt is made to make it impossible to access either the memory section of the IC memory card or the internal memory of the electronic device using the circuitry (hardware) of the electronic device. It is something to do.

[Problems to be Solved by the Invention] In such conventional IC memory cards, the memory is wasted by writing usable addresses as data, and the electronic equipment that uses them has no capacity to read them. requires a circuit and program to make it impossible to access the program and the memory section of the IC memory card or the internal memory of the electronic device,
The problem was that it was not universal.

In view of the above, the present invention provides an external storage device such as an IC memory card, in which addresses in a memory section are divided into used addresses and unused addresses, and unused addresses are accessed. It is an object of the present invention to provide a semiconductor memory device which can be widely used in various electronic devices incorporating memories with different addresses.

[Manual punch for solving the problem] As shown in FIG. 1, the semiconductor memory device of the present invention is a semiconductor memory device used as an external memory device of an electronic device 1, and is a semiconductor memory device used as an external memory device of an electronic device 1. A memory section 2 used by the device 1, and a use address setting/use address display code output section 3 for setting a use address for this memory section 2 and outputting a use address display code for displaying the use address. and a specified address/used address display code comparing section 4 that compares part or all of the address specified by the electronic device 1 with the used address display code, so that the address specified by the electronic device 1 is set as the used address. The memory section 2 can be accessed only when the address is a valid address.

In addition, as a method to enable access to the memory section 2, a so-called chip enable (C
E) Various methods can be considered, such as issuing a signal. In addition, in the figure, 5 is the CPU built in the electronic device 1, and 6 is the CPU built in the electronic device 1.
is a built-in memory, 7 is an address bus, and 8 is a data bus.

[Operation] In the present invention, if there is an overlap between the address of the memory unit 2 and the address of the memory 6 built into the electronic device 1, by setting a non-overlapping address as the address to be used, Access to addresses in the memory unit 2 is prohibited for duplicate addresses. In other words, when the electronic device 1 specifies a duplicate address, the electronic device built-in memory 6 is accessed. Therefore, there is no need to provide the electronic device 1 with a circuit or the like that makes the memory section 2 inaccessible.

[Embodiments] Various embodiments of the present invention will be described below with reference to FIGS. 2 to 4. It should be noted that these Examples do not explain the present invention.
Although this embodiment is applied to a C memory card, the present invention is not limited to these embodiments.

First, the first embodiment will be explained in terms of configuration, operation, and effects.

(1) Configuration of the first embodiment FIG. 2 is a circuit diagram showing the first embodiment of the present invention.
Chip enable signal input terminal 14, read/write control signal input terminal 15, address buffer 16.17.1
8.19, chip enable buffer 20, memory section 2
, a chip selector 21, a used address setting/used address display code output section 3, a designated address/used address display code comparison section 4, an I10 port 22, and data input/output terminals 23, 24, . . . 30. . Note that address signals Ao, A1, A2, and A3 are input to the address signal input terminals 10, 11, 12, and 13, respectively, and a chip enable signal CE is input to the chip enable signal input terminal 14, so that writing/reading can be performed. A write/read signal R/W is input to the signal input terminal 15.

In this first embodiment, the memory section 2 is a static RAM (hereinafter referred to as SRAM).
has been established. These SRAM31.32 are both 8×
It is an 8-bit structured SRAM, and the address is O to 1.
No. 11 has been set up. Furthermore, as described later, these SRAMs 31 and 32 are connected in parallel, and the SRAM 31 is
~111 address is in charge, SRAM32 is in charge of 1000~11
All 11 addresses are set to be 111. In addition, SRAM
31 and 32 are their chip select signals (CS
) is selected by supplying a logic "1" to the input terminal.

Moreover, the chip selector 21 is connected to the inverter 33.34.3.
5. It is configured by providing OR circuits 36 and 37.

Further, the use address setting/use address display code output section 3 is configured by providing EPROM cells 38, 39, 40, 41, and these EPROM cells 38, 39, 4.
The address to be used is set by setting the logic state of 0.41 as shown in Table 1, which will be described later. Used address display codes CIO, C1l, C1 according to the logic state of .39.40.41
□, output C13. That is, when the EPROM cell 38 is at logic "O", the logic rQ, , EPRO
If the M cell 38 is a logic "1", the CIO
" is output. EPROM cells 39.4o, 41 and C1
The same holds true for the relationships with l, C1□, and CtS. In addition, these address display codes C10, C11, C
12 and C1B are supplied to the specified address/used address display code comparison section 4.

In addition, the designated address/used address display code comparison section 4
is constructed by providing NAND circuits 46, 47, 48, 49, 50. As will be described later, when the output of the specified address/used address display code comparison section 4, that is, the output of the NAND circuit 50 (hereinafter referred to as comparison output SC) is logic "0", either of the SRAMs 31 and 32 becomes selectable.

In addition, the I10 boat 22 has input/output gates 51, 52...
58, an inverter 59, and OR circuits 60 and 61. Here, input/output gates 51, 52...
- 58 have the same configuration, for example, the input/output gate 51 is connected to the buffer 62 and the three-stit buffer 63.
The input gate has an input gate connected in series, and an output gate formed by connecting a buffer 64 and a three-stitch buffer 65. Also, this I10 boat 22
is provided with an I10 control control terminal 22A and a write/read control signal input terminal 22B, and the I10 control control terminal 22A is connected to one input terminal of the OR circuit 60, 61 to perform write/read control. Signal input terminal 22
B is connected to the other input terminal of the OR circuit 61 and also connected to one input terminal of the OR circuit 60 via the inverter 59 . The output terminal of the OR circuit 60 is the three-stit buffer 63.67.71.75.7.
The output terminal of the OR circuit 61 is connected to the control terminal of 9.83.87.91, and the output terminal of the OR circuit 61 is
．． It is connected to the control terminal of 73.77.81.85.89.93.

As a result, the I10 control hole power terminal 22A has logic "0".
, the logic “1” is applied to the write/read control signal input terminal 22B.
is supplied, the three-sty-one power is 63.67
．． 71.75.79.83.87.91 are made conductive, and threesty 1 to buffer 65.69.73.77
．． 81.85.89.93 are placed in a floating state. Therefore, in this case, writing is possible.

In addition, logic "O" is applied to the I10 control control hole input terminal 22A, and logic "0" is also applied to the write/read control signal input terminal 22B.
” is supplied, the three-stit buffer 63.67
．． 71.75.79.83.87.91 is set to floating state, and three-stit buffer 65.69.7
3.77.81.85.89.93 are made conductive. Therefore, in this case, reading is not possible.

Note that when logic "1" is supplied to the I10 control hole power terminal 22A, the three-stit buffer 63, 67, 71
．． 75.79.83.87.91 and three-stit buffer 65.69.73.77.81.85.89.9
3 are both placed in a floating state, making writing and reading impossible.

Here, address signal input terminals 10, 11, and 12 are connected to SRA via address buffers 16, 17, and 18, respectively.
It is connected to the address signal input terminal of M31.32. Further, the address signal input terminal 13 is connected to the first input terminal of the OR circuit 36 via the address buffer 19 and the first input terminal of the OR circuit 37 via the inverter 33.
is connected to the input terminal of Further, the chip enable signal input terminal 14 is connected to the second input terminal of the OR circuit 2836.37 via the chip enable buffer 20. Furthermore, the output terminal of the OR circuit 36 is connected to the inverter 3
4 to the chip select signal input terminal of the SRAM 31. Further, the output terminal of the OR circuit 1!837 is connected to the chip select signal input terminal of the SRAM 32 via the inverter 35. Further, the write/read control signal input terminal 15 is connected to the write/read control signal input terminals of the SRAMs 31 and 32 and the write/read control signal input terminal 22B of the I10 boat 22.

In addition, the output terminals of address buffers 16, 17, 18, and 19 are AND-circuited l\! 49.48.47.46
is connected to one input terminal of EPROM cell 3.
8.39.40.41 output terminal 42.43.44.4
5 are connected to the other input terminals of the NAND circuits 46, 47, 48, and 49, respectively. Further, the output terminals of these NAND circuits 46, 47, 48, 49 are connected to the first, second, third, and fourth input terminals of a NAND circuit 50, respectively, and the output terminal of this NAND circuit 50 is connected to the OR circuit 36. .37
and the I10 control hole power terminal 22A of the I10 boat 22.

In addition, the data input/output terminals of the SRAM 31 and 32 are connected to the input/output gates 51, 52, .
8 to the data input/output terminal 2 of this IC memory card.
3. Connected to 24...30.

(2> Operation of the first embodiment In the first embodiment, the SRAMs 31 and 32 are connected in parallel, so the addresses are 0 to 11.
This means that it has address 11.

Here, the chip selector 21 receives the chip enable signal C.
Only when E is logic rQ and comparison output sc is logic r□, the output of inverter 34 or 35 is logic "1".
”, so only in this case, SRAM31 or 3
2 can be selected. That is, address signal A3 is logic "0", chip enable signal CE is logic "O",
When the comparison output Sc is logic "0", the output of the inverter 34 is logic "1", and the output of the inverter 35 is logic "0".
Therefore, logic "1" is supplied to the chip select signal input terminal of the SRAM 31, so in this case, the SRAM
31 can be selected.

On the other hand, when address signal A3 is logic "1", chip enable signal σr is logic "0", and comparison output SC is logic "0", the output of inverter 34 is logic "O", and the output of inverter 35 is logic "0". 1" and the logic "1" is supplied to the chip select signal input terminal of the SRAM 32, so in this case, the SRAM 32 is selected.

Further, for example, the EI7ROM cell 38 is set to logic "0" and EP
When ROM cells 39, 40, and 41 are set to logic "1", the used address display codes CIO, CIl, C12, C
10 has the logic "0", "1", "1", and "1", respectively, so the other input terminal of the NAND circuit 46 has the logic "0", "1", "1", and "1".
0'' is input, and the logic r1. is input. As a result, address signal AO=“OJ, Al-“O”, A2-“O”,
If A3=“o” or Ao=“1”, Al
- only in the case of "o", Aa = 'OJ, As = ro', the comparison output SC becomes logic "0". That is, in this case, addresses 0 to 111 held by the memory section 2
Only addresses 0 and 1 of 1 address (0 and 1 of SRAM31)
(only the address) can be accessed. Table 1 shows the relationship between the logical states of EPROM cells 38, 39, 4o and 41 and the addresses that can be used.
become that way.

Table 1 (3) Effects of the first embodiment In the first embodiment, as shown in Table 1, in addition to setting to use all addresses 0 to 1111, addresses 0 to 1, It is also possible to use either addresses O to 11 or addresses O to 111. Therefore, there is no need to provide a circuit or the like for making the memory section 2 inaccessible to the electronic device using the IC memory card of the first embodiment. Therefore, the IC of this first embodiment
Memory cards can be widely used in various electronic devices containing memories with different addresses.

Suyu”01 ship FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

This second embodiment differs from the first embodiment in circuit configuration with respect to the used address setting/used address display code output section 3 and the specified address/used address display code comparison section 4.

That is, in this second embodiment, the address settings and
The used address display code output section 3 is an EPROM cell 94
．． 95, inverter 96.97, AND circuit 98.99
．． 100, OR circuits 101 and 102 are provided, and the specified address/used address display code comparison section 4
is configured by providing NAND circuits 103, 104, 105, and 106.

Here, the output terminal of the EPROM cell 94 is connected to the AND circuit 9.
8 and is connected to one input terminal of the inverter 96.
is connected to one input terminal of the AND circuit 99.100. Further, the output terminal of the EPROM cell 95 is connected to the other input terminal of an AND circuit 99, and is also connected via an inverter 97 to the other input terminal of an AND circuit 98.100.

Further, the output terminal of the AND circuit 98 is connected to one input terminal of the OR circuit 101, and this OR circuit 1i'8101
The output terminal of is connected to the other input terminal of the NAND circuit 103. Note that one input terminal of this NAND circuit 103 is connected to the output terminal of the address buffer 19.

Further, the output terminal of the AND circuit 99 is connected to one input terminal of an OR circuit 102, and the output terminal of this OR circuit 102 is connected to the other input terminal of the OR circuit 101 and the other input terminal of the NAND circuit 104. ing. Note that one input terminal of this NAND circuit 104 is connected to the output terminal of the address buffer 18.

Further, the output terminal of the AND circuit 100 is connected to the other input terminal of the OR circuit 102 and the other input terminal of the NAND circuit 105. Note that one input terminal of this NAND circuit 105 is connected to the output terminal of the address buffer 17.

The output terminals of the NAND circuits 103, 104, and 105 are connected to the first, second, and third input terminals of the NAND circuit 106, respectively, and the output terminal of the NAND circuit 106 is connected to the third input terminal of the OR circuit 36.37. input terminal and I10 boat 2
It is connected to the I10 control hole power terminal 22A of No. 2.

The rest of the structure is the same as that of the first embodiment (the example in FIG. 2).

In the second embodiment, the used address setting/used address display code output section 3 outputs the used address display codes C20, C21, and C22.
The relationship between C21 and C22 and the logic states of EPR and OM cells 94 and 95 is shown in Table 2.

Table 2 Therefore, the relationship between the logical states of the EPROM cells 94 and 95 and the address used is as shown in Table 3.

Table 3 Therefore, like the IC memory card of the first embodiment, the IC memory card of the second embodiment can be widely used in various electronic devices that incorporate memories with different addresses.

``Sakuyu'' Umuhiki FIG. 4 is a circuit diagram showing a third embodiment of the present invention.

Similar to the second embodiment, the third embodiment differs from the first embodiment in the circuit configuration of the used address setting/used address display code output section 3 and the comparison section 4.

That is, in this third embodiment, the use address setting/
The used address display code output section 3 is an EPROM cell 10
7.108, inverter 109.110, AND circuit 1
11, 112, and 113, and the designated address/used address display code comparison section 4 includes NAND circuits 114, 115, 116, 117, and AND circuits 118.
, and an OR circuit 119.

Here, the output terminal of the EPROM cell 107 is connected to one input terminal of an AND circuit 111 and also connected to one input terminal of AND circuits 112 and 113 via an inverter 109. Further, the output terminal of the EPROM cell 108 is connected to the other input terminal of the AND circuit 112 and connected to the AND circuit 111 via the inverter 110.
, 113. Further, the output terminals of the AND circuits 111, 112, and 113 are connected to the other input terminals of the NAND circuits 114, 115, and 116, respectively.

Further, in this third embodiment, the address buffer 1
The output terminal of address buffer 1 is connected to the other input terminal of AND circuit 118 and OR circuit 119.
The output terminals of 9 are an AND circuit 118, a NAND circuit 115,
It is connected to one input terminal of the OR circuit 119.

Further, the output terminals of the NAND circuits 114, 115, and 116 are connected to the first, second, and third input terminals of the NAND circuit 117, respectively, and the output terminal of the NAND circuit 117 is connected to the third input terminal of the OR circuit 36.37. input terminal and I10 boat 2
It is connected to the I10 control hole power terminal 22A of No. 2.

The rest of the structure is the same as that of the first embodiment.

In the third embodiment, the used address setting/used address display code output unit 3 outputs the used address display codes C30, cst, and C32, but these C9°,
The relationship between C31, C32 and the logical states of EPROM cells 107 and 108 is as shown in Table 4.

Table 4 Therefore, the relationship between the logical states of the EPROM cells 107 and 108 and the address used is as shown in Table 5.

Table 5 In the third embodiment, the address range used is
Although this embodiment is different from the first embodiment, it is possible to obtain the same effect as the first embodiment in that it can be used in various electronic devices having built-in memories with different addresses.

Living! 04 In the above embodiment, the case where the address signal input from the CPU is 4 bits has been described, but the present invention can also be applied to cases where address signals of various bit numbers are input, such as 8 bits, 16 bits, etc. It can also be applied to

Furthermore, in the above embodiment, the memory section is divided into two SRs.
Although the case has been described in which the AM is configured, the present invention also includes one or more SRAMs, or one or more DRAMs.
The present invention can also be applied to a configuration using RAM, EEPROM, mask ROM, etc.

Furthermore, in the above-described embodiment, the use address setting/use address display code output section 3 is configured with an EPROM cell, but instead of this, a mask ROM may be used.
It is also possible to use a cell, an SRAM cell with backup, a deep switch, or the like.

[Effects of the Invention] As described above, according to the present invention, a use address is set, and only when the address specified by the electronic device using the present invention is the address set as the use address, the memory unit is Allows access to t! Therefore, there is no need to provide a circuit or the like on the electronic device side to make the memory section inaccessible. Therefore, the present invention has versatility and can be widely used in various electronic devices incorporating memories with different addresses.

[Brief explanation of the drawing]

Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is a circuit diagram showing a first embodiment of the invention, Fig. 3 is a circuit diagram showing a second embodiment of the invention, and Fig. 4 is a circuit diagram showing a second embodiment of the invention. Third
FIG. 2 is a circuit diagram showing an example. 1...Electronic device 2...Memory unit 3...Used address setting/Used address display code output section 4...Specified address/Used address display code comparison section 5...CPU 6...Electronic device Built-in memory 7...Address bus 8...Data path

Claims (1)

[Claims] A semiconductor storage device used as an external storage device of an electronic device (1), comprising: a memory section (2) used by the electronic device (1).
and a use address setting/use address display code output unit (3) for setting a use address for the memory unit (2) and outputting a use address display code for displaying the use address, and the electronic device. A specified address/used address display code comparison unit (4) is provided to compare part or all of the address specified by (1) with the used address display code, and the address specified by the electronic device (1) is used. A semiconductor memory device characterized in that the memory section (2) can be accessed only when the address is set as an address.