JPH03129538A - Program evaluation system - Google Patents

Abstract

PURPOSE:To make it possible to reflect the result of response processing to communication to program evaluation by detecting a communication instruction issued by a program to be evaluated and automatically executing the response processing to the communication in accordance with the contents of a communication instruction. CONSTITUTION:An instruction extracting means 5 extracts a CPU instruction to be executed from the program 2 to be evaluated stored in a main storage device 1, and when there is a CPU instruction to be executed, starts an instruction analyzing/executing means 6. When the supplied CPU instruction requests communication issue to a processor 14, the means 6 starts an external processor simulator starting means 7. The means 7 starts an instruction string output means 11. When a CPU instruction string corresponding to the informed communication instruction is defined in response information stored in a response information storing means 9, the means 11 starts an instruction supplying means 12. Consequently the result of response processing to communication is reflected to the program evaluation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an evaluation system for programs at the development stage.

[Conventional technology]

The development of a software program is often carried out simultaneously with the development of the hardware such as a micro combinator to which the program is applied, so when evaluating the effectiveness of a program that is currently under development, it is important to An evaluation system using a simulator that replaces the department has been adopted.

Conventionally, this type of evaluation system consists of a CPU simulator that replaces some of the functions of the CPU of a microcomputer, and a main storage device that stores the program to be evaluated. The program was evaluated by running the program and testing whether the predetermined operations were performed correctly.

[Problem to be solved by the invention]

The conventional program evaluation system described above, when evaluating a program applied to a microcomputer that performs communication processing with a processor different from the CPU to be simulated, processes responses to communications issued by the CPU to be simulated. Therefore, the evaluation of communication requests issued by the program to be evaluated is
It was practically impossible to do.

[Means to solve the problem]

The configuration of the program evaluation system of the present invention is a system for evaluating a program at the development stage, and replaces some functions of a CPU in an information processing device to which the program to be evaluated is applied. a CPU simulator that analyzes and executes CPU instructions of a program; and a CPU simulator that is connected to the CPU simulator and replaces some functions of a processor different from the CPU in the information processing device, and that performs communication issued by the CPU simulator. an external processor simulator that responds to the evaluation target program, and a main storage device for storing the evaluation target program; CPU that should be executed from the evaluation target program
An instruction fetching means for fetching instructions and a supplied CPU
an instruction analysis/execution unit that analyzes and executes an instruction; and when the instruction analysis/execution unit detects a communication instruction requesting the issuance of communication to a processor in the information processing device different from the CPU; an external processor simulator activation means for activating the external processor simulator based on a communication command; and a response for creating response information that associates a communication command with a CPU instruction string based on correspondence input from outside the CPU simulator. The external processor simulator has an information creation means and a response information storage means for storing response information, and the external processor simulator refers to the response information and executes a CPU command corresponding to the communication command notified by the external processor simulator activation means. An instruction sequence output means for searching and outputting a sequence, and a CPU instruction sequence outputted by the instruction sequence output means,
The present invention is characterized by comprising an instruction supply means for supplying one instruction to the execution means one by one.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing the configuration of an embodiment of the program evaluation system of the present invention, FIG. 2 is a diagram showing the bottom of the information processing device to which the program to be evaluated is actually applied, and FIG. 3 is the diagram shown in FIG. 1. FIG. 4 is a flowchart showing the operating procedure of this embodiment.

The program evaluation system of this embodiment uses the CPU shown in FIG.
CPU simulator 3 that replaces some of the functions of 13;
It consists of an external processor simulator 1° that replaces part of the functions of the processor 14 shown in FIG. 2, and a main storage device 1 that stores a program 2 to be evaluated. C.P.
The U simulator 3 includes a CPU simulator starting means 4 that starts the CPU simulator in response to a starting command, an instruction extracting means 5 that extracts a CPU instruction from the evaluation target program 2, and an instruction analyzer that analyzes and executes the supplied CPU instruction. /When the execution means 6 and the instruction analysis/execution means 6 detect that the supplied CPU instruction is a communication instruction for the processor 14, the detected communication instruction is notified to the external processor simulator 10, and the external processor simulator 10 is activated. External processor simulator starting means 7, response information creation means 8 for creating response information for associating communication commands and CPU instruction sequences based on correspondence input from the outside, and response information for storing response information. It is composed of storage means 9. The external processor simulator 10 includes an instruction sequence output means 11 that searches response information for a CPU instruction sequence corresponding to a communication command notified by the external processor simulator activation means 7 and outputs the CPU instruction sequence, and a CPU instruction outputted by the instruction sequence output means 11. It is comprised of an instruction supply means 12 that sequentially extracts CPU instructions from the sequence, supplies them one instruction at a time to the instruction analysis/execution means 6, and activates the instructions.

Next, the operation of this embodiment will be explained.

When a startup command is input from the outside, the CPU simulator startup means 4 starts the CPU simulator 3 (step 16), and then starts the response information creation means 8 (step 17). Based on the input correspondence information, response information is created and stored in the response information storage means 9 (step 18).Next, the CPU
Simulation.

The controller starting means 4 starts the instruction retrieval means 5 (step 19), and the instruction retrieval means 5 retrieves the CPU instruction to be executed from the evaluation target program 2 in the main memory 1 (step 20), and first executes it. It is determined whether there is a CPU instruction or not (Step 21), and if there is a CPU instruction to be executed, it is supplied to the instruction analysis/execution means 6 and the instruction analysis/execution means 6 is activated (Step 22).
.

When there are no CPU instructions to process, the process ends.

The instruction analysis/execution means 6 determines whether the supplied CPU instruction requests the processor 14 to issue a communication (Step 24), and if it is a communication instruction, starts the external processor simulator activation means 7. (
Step 25>0 If there is no communication request, step 1
Returning to step 9, the next CPU instruction on the evaluation target program 2 is processed.

The external processor simulator starting means 7 notifies the instruction string output means 11 of the content of the detected communication command and starts the instruction string output means 11 (step 26). It is determined whether the CPU command sequence corresponding to the communication command is defined in the response information in the response information storage means 9 (step 27), and if the CPU command sequence corresponding to the communication command is defined in the response information,
Notify the corresponding CPU instruction sequence to the instruction supply means 12 and start it (step 28) C corresponding to the 0 communication instruction
If the PU instruction sequence is not defined in the response information, the process returns to step 19 to process the next CPU instruction. The instruction supply means 12 determines whether all CPU instructions on the notified CPU instruction sequence have been executed (Step 29), and if there is a CPU instruction to be executed, the
The CPU instruction to be executed next is extracted from the PU instruction sequence, and the extracted CPLI instruction is supplied to the instruction analysis/execution means 6, and it is activated (step 30).

The instruction analysis/execution means 6 analyzes/executes (simulates) the supplied CPU instruction (step 31), returns to step 29, and processes the next CPU instruction on the CPU instruction sequence. When all the CPU instructions on the column have been executed, the process returns to step 19 and processes the next CPU instruction on the evaluation target program 2, and the CPU to process
Processing ends when there are no more instructions.

〔Effect of the invention〕

As explained above, the present invention detects a communication command issued by a program to be evaluated, and automatically performs a response process to this communication according to the content of the communication command, thereby reflecting the result of the response process to the communication in program evaluation. can do.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of an embodiment of the program evaluation system of the present invention, FIG. 2 is a diagram showing the nIj precepts of an information processing device to which the evaluation target program is actually applied, and FIG. Response information 15 stored in response information storage means 9
FIG. 4 is a flowchart showing the operating procedure of this embodiment. 1... Main storage device, 2... Program to be evaluated, 3
...CPU simulator, 4.CPU simulator starting means, 5.Instruction fetching means, 6.Instruction analysis/execution means, 7.External processor simulator starting means, 8.Reply information creation means, 9...response information storage means, 10...external processor simulator;
11... Instruction sequence output means, 12... Instruction supply means,
13...CPU, 14...Processor, 15...
Response information, steps 16-31.

Claims (1)

[Claims] A system for evaluating a program at the development stage, which is a CPU that replaces some of the functions of a CPU in an information processing device to which the evaluation target program is applied, and analyzes and executes CPU instructions of the evaluation target program. a simulator; an external processor simulator connected to the CPU simulator, which replaces some functions of a processor different from the CPU in the information processing device and responds to communications issued by the CPU simulator; The CPU simulator includes a main storage device for storing a program to be evaluated, and the CPU simulator includes a CPU simulator startup means for starting the CPU simulator in response to a startup command, and a CPU instruction to be executed from the program to be evaluated. an instruction retrieval unit for retrieving an instruction; an instruction analysis/execution unit for analyzing and executing a supplied CPU instruction; and a request for issuing a communication to a processor in the information processing device different from the CPU by the instruction analysis/execution unit. External processor simulator activation means for activating the external processor simulator based on the communication instruction when a communication instruction is detected, and based on association information input from the outside of the CPU simulator,
The external processor simulator includes a response information creation means for creating response information that associates a communication command with a CPU command sequence, and a response information storage means for storing the response information, and the external processor simulator includes:
With reference to the response information, the CP corresponding to the communication command notified by the external processor simulator starting means
It is characterized by comprising an instruction sequence output means for searching and outputting a U instruction sequence, and an instruction supply means for supplying the CPU instruction sequence outputted by the instruction sequence output means to the instruction analysis/execution means one instruction at a time. program evaluation system.