JPH03125981A - Hazard detection circuit - Google Patents

Abstract

PURPOSE:To enable detection of location of a test pattern simply by performing a timing simulation once only by connecting a hazard circuit in parallel to an input terminal of each combination block (AND, OR etc.) to be verified. CONSTITUTION:An input A indicates a rising at timings (T) 21 and 31 from a level '1' and a falling at a T 30 and an input C indicates a waveform held at a logic value 1 and an input B should rise at the timing T 21 from a level '1' and rise again at the timing T 31 but deviated in the T affected by a hazard given by an AND gate output Y. Now, for example, when inputs A, B and C of the AND gate 1 change at the T 21 with respect to a rising 20 of CLK to be provided from an inverter 16, outputs 2-Q and 3-Q of FF circuits 2 and 3 latched at a falling 22 of CLK vary as shown by 23 and 24 individually. An output 4-Q of a circuit 4 is held at the level '1'. Thus, such a signal as to be a high level between halfs of the CLK indicated by 28 is outputted at an external output terminal 15 thereby enabling detection of the hazard 29.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a hazard detection circuit, and particularly to a hazard detection circuit that detects a test pattern that includes a risk of a hazard occurring during timing verification in LSI design.

[Conventional technology]

Traditionally, this type of hazard detection is performed after performing a timing simulation to check the normality of the timing.
The hazard detection simulation was performed again to detect points in the test pattern where a hazard occurred or was at risk of occurring.

[Problem to be solved by the invention]

The conventional hazard detection described above is performed by performing timing simulation, so it can only detect the parts of the test pattern where a hazard actually occurs, and the hazard will occur by performing the hazard detection simulation again. Because we are trying to detect potentially dangerous test pattern locations, we end up having to perform two simulations to detect hazards.
Moreover, the time required for one simulation is very long, and there is a drawback that efficient settings cannot be made.

[Means to solve the problem]

The hazard detection circuit of the present invention is an input of a verification block that receives a plurality of inputs that may include hazards that inhibit timing in a timing simulation during the design of a 6LSI consisting of a sequential circuit and a combinational circuit. a plurality of flip-flop circuits which receive each of the above as inputs and operate with a preset clock, a first exclusive OR gate group whose inputs are the input of the combinational block and the output of the flip-flop circuit; a second exclusive OR gate group that takes and inputs a combination of two different inputs from the inputs to the verification block; and a first and second exclusive OR gate group for each of the flip-flop circuits;
a plurality of AND gates that perform logical product by including the outputs of the first exclusive OR circuits corresponding to other flip-flop circuits in different ways in the outputs of the OR gates of the plurality of AND gates; and an OR gate that receives the output and performs a logical sum.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a configuration diagram of an embodiment of the hazard detection circuit of the present invention, in which multiple inputs as a verification block, in this embodiment, an AND gate 1 operated by three people, and inputs to the AND gate.
It comprises a hazard detection circuit 17 connected in parallel to three human power sources A, B and C that may contain a hazard.

The hazard detection circuit 17 includes three flip-flop circuits 2, 3, and 4 corresponding to the three-manpower A, B, and C, and a first exclusive logic in which the inputs and outputs of the flip-flop circuits 2, 3, and 4 are two-manpower. As a sum (XOR) gate group (
7) XOR gate 5, 7゜9.3 XOR gate 6.8, 10 as a second exclusive OR gate inputting two different combinations from A, B and C, flip-flop circuit 2. XOR corresponding to 3 and 4 respectively
In addition to the two outputs of gates 5 and 6, 7 and 8, and 9 and 10, three outputs of different outputs of the first exclusive OR gate corresponding to other flip-flop circuits are received and their logical product is calculated. AND gate 11, 12 and 13, AND gate 1
1. An OR gate 14 that takes the logical sum of 12 and 13;
It includes an external output terminal 15 and an inverter 16 that inverts the polarity of a clock CLK signal and supplies it to flip-flop circuits 2, 3, and 4.

FIG. 2 is a timing chart of main signals in the embodiment of FIG. The operation of the embodiment shown in FIG. 1 will be explained below with reference to FIG.

As shown in FIG. 2, inputs A, B, and C each rise to the "1" level at timing 21.31, and input A rises to the "1" level at timing 21.31.
The waveform that shows a fall at timing 30, the input C is a waveform that is held at a logic value of 1, the input B falls from the "1" level at timing 21, and the waveform that should rise again at timing 31 is the AND gate output output water waveform. The case where the timing is shifted due to the influence of Hazard 29 is taken as an example.

Now, the rising edge 2 of CLK provided from the inverter 16
0, if the inputs A, B and C of the AND gate 1 change at timing 21, the Q output 2-Q of the flip-flop circuit 2.3 latched at the falling edge 22 of CLK.
, 3-Q each change as 23.24. The Q output 4-Q of the flip-flop circuit 4 remains at the high level of "1". The output of XOR gate 5.7 becomes 25.26, and the output of XOR gate 6 remains at high level, so the output of AND gate 11 becomes 27. At this time, the outputs of the other AND gates 11 are as shown in 27.

At this time, the output of the other AND gates 12 and 13 is “0”
is held at the low level of the OR gate 1
The output of 4 will be 28. That is, the external output terminal 15 outputs a signal as shown at 28 which is at a high level for half a clock of CLK, which means that two hazards have been detected.

Also, timing 30 shows the timing when only the A signal changes, and timing 31 shows the timing when both A and B change in level in the same direction, but at this time, of course, no hazard is detected from the external terminal 15. .

〔Effect of the invention〕

As explained above, the present invention enables ``timing simulation to be performed only once'' by connecting the present hazard detection circuit in parallel to the input terminal of each combinational block (AND, OR gate, etc.) whose timing is to be verified. This has the effect of making it possible to immediately detect the occurrence of a hazard or a potentially dangerous test pattern in real time, thereby enabling efficient LSI design.

FIG. 1 is a block diagram of an embodiment of the hazard detection circuit of the present invention, and FIG. 2 is a timing chart of main signals in the embodiment of FIG.

1.11-13...AND gate, 2-4...Flip-flop circuit, 5-10...XOR gate, 11
~13...AND gate, 14...OR gate.

Claims (1)

[Claims] In timing simulation during the design of LSIs consisting of sequential circuits and combinational circuits, each of the inputs of the verification block to be verified receives multiple inputs that may include hazards that impede timing, and a plurality of flip-flop circuits that operate with a set clock, and a first circuit that receives the input of the combinational block and the output of the flip-flop circuit;
a second exclusive OR gate group that inputs a combination of two different inputs from the inputs to the verification block; and a first and second exclusive OR gate group for each of the flip-flop circuits. a plurality of AND gates that perform logical product by including the outputs of the first exclusive OR circuits corresponding to other flip-flop circuits in different ways in the outputs of the OR gates of the plurality of AND gates; What is claimed is: 1. A hazard detection circuit comprising: an OR gate that receives an output and performs a logical sum; and detects a hazard.