JPH0312275B2 - - Google Patents

Description

Detailed Description of the Invention (Technical Field of the Invention) The present invention counts the number of clock pulses between a first time point and a second time point (event), and calculates the duration of the event from the counted value. The present invention relates to a time measurement method that makes it possible to increase the resolution of measurement, which is normally determined by the ability of a clock pulse counter, to a level higher than that ability.

(Technical background of the present invention) For example, in a distance measuring system that calculates the distance to a target by measuring the time from the time when light is projected to the time when the light is reflected by the target and enters the target. For example, if a resolution of 1m (meter) is required, the measurement time resolution should be approximately 6.67nS.
(nanosecond), and for this purpose, by setting the clock pulse frequency to about 150 MHz (period: about 6.67 nS), it is possible to immediately measure time with a resolution of 6.67 nS from the number of clock pulses.

However, even in the case of optimally configured TTL and C-MOS logic, the counting ability of the counter is
Since the frequency is over 15 MHz, the resolution of the conventional technique, that is, the method of immediately determining the time from the number of clock pulses, is 67 nS at most, and the distance measuring system described above can only obtain a resolution of about 10 m.

(Object of the present invention) In view of the above-mentioned problems, the present invention provides a time measurement method that uses a relatively slow counter to obtain the same resolution as a faster counter. It is an object of the present invention to provide a time measurement method in which a lower frequency clock pulse can provide the same resolution as when using a higher frequency clock pulse.

(Summary of the Invention) To this end, the present invention provides clock pulses such that the phase function between the clock pulse and the event is different from each other with a uniform deviation for a plurality of events. Set the relationship between the cycle and the event occurrence cycle, and calculate the average value by integrating the number of clock pulses for N events (N is a natural number of N≧2), that is, the "total number of clock pulses/N", and calculate the average value. The duration of the above event is calculated based on the above.

(Embodiments of the present invention) Hereinafter, embodiments of the present invention will be described with reference to the drawings.

Figures 1 to 3 are block diagrams of the first to third embodiments of the present invention, Figures 4 and 5 are time charts showing the operation of the first embodiment, and Figure 6 is a diagram of the second embodiment. A time chart showing the operation of the example. FIGS. 7 and 8 are time charts showing the operation of the third embodiment. Incidentally, the first to third embodiments are all examples in which the present invention is implemented in the optical transmission time measuring section of the distance measuring system.

First, a first embodiment will be explained with reference to FIGS. 1, 4, and 5.

In FIG. 1, 1 is a clock pulse oscillator (hereinafter referred to as a clock oscillator), 2 is an event cycle setting timer (hereinafter referred to as an event timer), 3 is a light emitting element drive unit (hereinafter referred to as a driver), 4 5 is a light emitting element, 5 is a light receiving element, 6 is a reflected light receiver (hereinafter referred to as a receiver), and 7 is a reset (R-S) flip-flop circuit (hereinafter referred to as a receiver).
It's called a flip-flop. ), 8 is an event count counter (hereinafter referred to as hit counter) 9
is a phase operation unit (hereinafter referred to as a phase shifter),
10 is an AND gate, 11 is a clock pulse number integration counter (hereinafter referred to as a counter), and 12 is a division operation unit (hereinafter referred to as a divider).

First, the functions of each block will be explained.

The clock oscillator 1 generates a clock pulse with a constant period, and the period of this clock pulse determines the resolution of the measurement time based on the cumulative number of events set in a hit counter 8, which will be described later. That is, if the period of the clock pulse is t, the cumulative number of events is N (N≧2 natural number), and the required measurement time resolution is _tA , then there is a relationship of "t=N・_tA ",
It is sufficient to set the period of the clock oscillator 1 to a length N times the resolution.

The event timer 2 sets the event generation cycle based on the clock pulse, and is, for example, a 1/n frequency divider (n is a natural number of n≧2), which generates one pulse every time n clock pulses are counted. Output.

The driver 3 supplies light emitting power to the light emitting element 4, and causes the light emitting element 4 to emit light for a set time period every time a pulse is output from the event timer 2.

The light emitting element 4 is, for example, a semiconductor laser light emitting element (laser diode), and projects light for time measurement (ultimately distance measurement to a target). The light projection period coincides with the output pulse period of the event timer 2, that is, the event generation period, and is "nt".

The light-receiving element 5 is, for example, a photodiode, and receives the projected light from the light-emitting element 4 reflected by the target object.
That is, it receives reflected light.

When the receiver 6 receives the reflected light with the light receiving element 5, it detects the reflected light and converts it into an electrical signal (pulse signal).

The flip-flop 7 is set by the signal from the event timer 2 to raise the level of the output Q, and is reset by the signal from the receiver 6 to lower the level of the output Q, thereby changing the time from the light emission time of the light emitting element 4 to the light reception time of the light receiving element 5. Until, that is, detect an event.

The hit counter 8 counts the number of occurrences of an event by counting the rising edge of the level of the output Q of the flip-flop 7, and each count data is sent to the phase shifter 9 for each count.
1 outputs an enable signal that puts the counter 11 into an operating state from counting 0 to counting the set number of times.

The phase shifter 9 shifts the phase of the clock pulse by a set amount Δt for each count output of the hit counter 8. This phase shift amount Δt is set to "t/N".

The AND gate 10 is for inputting the clock pulse whose phase has been subjected to the phase shifter 9 to the counter 11 during the continuation of the event.

The counter 11 counts the clock pulses that have passed through the AND gate 10, and integrates the clock pulses while the enable signal from the hit counter 8 is present. That is, the number of clock pulses is cumulatively counted for a set number of events N.

The divider 12 divides the cumulative number of pulses output from the counter 11 by the cumulative number of events N.

Next, the operation of the first embodiment will be explained with reference to FIGS. 4 and 5.

The clock oscillator 1 constantly oscillates clock pulses with a period t. The clock pulse from the clock oscillator 1 is input to the event timer 2, which divides the frequency by 1/n, and outputs the clock pulse from the event timer 2 every n periods of the clock pulse, that is, at a time nt.
Each time a pulse signal is output, a driving pulse current is supplied from the driver 3 to the light emitting element 4 every time this pulse signal is input to the driver 3, and the light emitting element 4 projects light onto the target object.

On the other hand, the pulse signal output from the event timer 2 is connected to the set terminal S of the flip-flop 7.
The signal is also input to the output Q, and the level of its output Q is raised to detect the start of an event.

The light projected from the light emitting element 4 is reflected by the target object and is incident on the light receiving element 5. When reflected light is incident on the light receiving element 5, the receiver 6 detects it and sends a pulse signal to the reset terminal R of the flip-flop 7 to lower the level of its output Q.
End of event is detected.

The hit counter 8 increments every time the output Q of the flip-flop 7 rises, that is, every start point (or every end point) of an event, and counts the number of events to be accumulated up to a set number N. In the operation example shown in FIG. 4, the count value of the hit counter 8 becomes "0" at the first event, and thereafter increases until the count value reaches (N-1) every time the start point of the event is input.

The count value of the hit counter 8 is input to a phase shifter 9, which shifts the phase of the clock pulse input therein in accordance with the count value of the hit counter 8. The phase shift amount is set to an integral multiple (including 0) of the minimum shift amount set to "t/N" (this is referred to as a unit phase shift amount Δt). In the embodiment, the amount of phase shift is set to "count value of hit counter 8 x .DELTA.t", and generally at the K-th event, the phase of the clock pulse shifts by "(K-1) .DELTA.t". Specifically, for example, in the first event, the phase shift amount is "0", and for example, in the third event, the phase shift amount is "2Δt". In this way, the phases of the N events are sequentially and averagely shifted from the phase of the clock pulse by Δt (=t/N).

Further, while the hit counter 8 counts the event N times, that is, while the count value is from "0" to "N-1", the hit counter 8 supplies an enable signal to the enable terminal ENABLE of the counter 11. The counter 11 performs the operation of integrating and counting the number of clock pulses, which will be described below.

A clock pulse whose phase is manipulated by the phase shifter 9 for each event is input to the input terminal IN of the counter 11. That is, for each event, the level of the output Q of the flip-flop 7 goes high and the AND gate 10 opens, so that the clock pulse output from the phase shifter 9 is output from the counter 1.
1 input terminal IN. The counter 11 integrates the number of clock pulses input as described above for N events, waits for the end of the N-th event, and then outputs the clock pulses to its output terminal OUT.
Outputs the integrated count value.

The total number of clock pulses during N events, which has been integrated and counted in the above manner, is then input to the divider 12 and divided by "N" to obtain the average value of the number of clock pulses during one event. The duration of the event is this average value multiplied by the period t of the clock pulse. The resolution _tA of the event duration obtained in this way is “t/N”,
The resolution has been improved by N times compared to the conventional method.

Figure 5 is the horizontal direction (time axis direction) in Figure 4.
In order to make it easier to understand the relationship between the events and counter input clock pulses displayed in , the counter input clock pulses for each event are arranged vertically and the time axis is enlarged. Hereinafter, the phase relationship in time measurement in the first embodiment will be explained in detail with reference to FIG. Furthermore, this fifth
In the figure, it is assumed that the counter 11 increments at the leading edge (rising edge) of the clock pulse.

Generally, the phase difference between the event and the clock pulse (the time difference between the rising edge of the event and the rising edge of the first clock pulse during the event) at the Kth event (K is a natural number where K≦N) is “( K-1) Δt” and further “Δt=t/
From the relationship of “N”, the phase difference is “(K-1)・t/
Also, from the above relationship, the maximum value of the phase deviation amount is "{(N-1)/N}・t", and the phase deviation amount does not exceed one period t of the clock pulse. Therefore, the difference (difference) in the number of clock pulses between events with different count values of the number of clock pulses is one.

In the operation example shown in FIG. 5, P clock pulses are counted for each of the first to Kth event duration T, and (P-1) clock pulses are counted for each of the (K+1)th to Nth event duration T. It is being counted. Therefore, the cumulative count value A of the number of clock pulses of the counter 11 is A=K.P+(NK) (P-1)=(P-1) N+K (numbers) . . . (1).

On the other hand, since the last (Pth) clock pulse of the first event is counted from the first to the Kth time, the time T _B shown in FIG.
is a value between "(K-1)Δt" and "KΔtt".
Also, the time T _A shown in Fig. 5 is “(P-1)t”
Therefore, the event duration T is T = T _A + B _B ≒ (P-1) t + K Δt ... (2), and from the above relationship "Δt = t/N", equation (2) further becomes T ≒ ( P-1) t+K・t/N={(P-1)
+K/N}t...(3). From equations (1) and (3), the event duration T
becomes T≒A/Nt...(4).

As is clear from equation (4) above, the event duration T to be measured is the value obtained by dividing the cumulative count value A of the number of clock pulses by the cumulative number of events N, that is, the value obtained by multiplying the average value by the clock pulse period.

Next, a second embodiment will be explained with reference to FIGS. 2 and 6.

In the second embodiment, instead of shifting the phase of the clock pulse in the first embodiment, the phase of the event is shifted. That is, the phase shifter 9 is connected to the output Q of the flip-flop 7, and changes the phase of the event by a set amount Δt (unit phase shift amount) for each count output of the hit counter 8.
shift by one. Further, the clock pulse is input directly to the AND gate 10, and the clock pulse is input to the counter 11 during the continuation of the event subjected to the phase manipulation.

As shown in Figure 6, the K-th event is “(K-1)” from the time when the event actually occurs.
Therefore, the phase relationship between the clock pulse and the event is exactly the same as in the first embodiment, and the operation is the same as in the first embodiment.
This can be easily understood from the operation of the embodiment.

Next, a third embodiment will be explained with reference to FIGS. 3, 7, and 8.

In FIG. 3, 13 is an event pulse oscillator (hereinafter referred to as an event oscillator), and the others are the same as in FIG. 1.

The event oscillator 13 generates a pulse with a constant period (hereinafter referred to as an event pulse) that is the basis of the event generation period, and the period _tE of this event pulse is set to a value slightly different from the period t of the clock pulse. Ru.

Unlike the first embodiment, the event timer 2 sets the event generation cycle based on the event pulse. That is, one pulse is output every time n event pulses are counted, and the event generation cycle is "nt _E ".

The hit counter 8 is different from the first embodiment,
It does not require output for each count and only outputs an enable signal. That is, by counting the rise of the level of the output Q of the flip-flop 7, the number of event occurrences is counted, and the set number of times (N times) is calculated.
An enable signal is output to the counter 11 to keep the counter 11 in operation until the count is counted.

The functions of the other parts mentioned above are the same as those of the first embodiment. However, in the third embodiment, the phase shifter 9 of the first embodiment does not exist.

Referring to FIG. 7, the operation of the third embodiment will be explained in comparison with the operation of the first embodiment.

While the event occurs every "nt" in the first embodiment, it occurs every "nt _E " in the third embodiment. Since the period t of the clock pulse and the period _tE of the event pulse are slightly different, the phase relationship between the clock pulse and the start point of the event differs for each event. In this way, in the third embodiment, the phase relationship between the event pulse and the clock pulse is set to be different depending on the period setting, so there is no need to manipulate the phase of the clock pulse or event as in the first or second embodiment. Clock pulses and events are input directly to AND gate 10.

Since the other operations described above can be easily understood from the operations of the first embodiment, they will not be explained again here.

FIG. 8 is a time chart having the same gist as FIG. 5 of the first embodiment. Hereinafter, the phase relationship in time measurement in the third embodiment will be explained with reference to FIG. In FIG. 8, for ease of understanding, the rising edge (starting point) of the first event and the rising edge of the clock pulse are made to coincide with each other, but the clock oscillator 1 and the event oscillator 13 perform their oscillation operations independently of each other. Therefore, it is rather rare for the rising edge of the event and the clock pulse to coincide as described above. However, if the time axis of the event is shifted by a time corresponding to the difference between the rising edge of the event and the clock pulse, all of the following explanation can be understood.

As already explained, in order to measure time with a resolution of t/N from the integrated value of the number of clock pulses during N events, it is necessary to make the phase difference between the rising edge of the event and the clock pulse different for all N events. For this purpose, the cycle of events is
nt _E satisfies nt _E = m ₁ tβ (m ₁ is a natural number, 0 < β < t) β = t/N・m ₂ (m ₂ is a natural number such that 0 < m ₂ < N), and m ₂ is Set to a value other than an integer multiple of the divisor of .

Specifically, for example, if "N=10", the above "m ₂ " is set to a value other than an integral multiple of 2 and 5.

By doing the above, the phase difference α _K (K is a natural number from 1 to N) between the rising edge of each event and the clock pulse will all have different values, α _K = M・Δt (where M is 1 to (N -1) natural number). M is determined independently of K, and therefore, the phase difference does not occur sequentially by Δt every time an event occurs as in the first embodiment, but different phase differences appear in random order. If these are rearranged sequentially from events with a small phase difference to events with a large phase difference, the relationship will be similar to the relationship shown in FIG.
t/N). ) The phase relationship analysis in the first embodiment can also be applied to the third embodiment. That is, in the third embodiment as well, the event duration T can be determined based on the average value "A/N" obtained by dividing the integrated value A of the number of clock pulses by the number N of events.

(Effects of the present invention) As described above in detail, according to the present invention,
It is possible to measure time with a resolution shorter than the period of the clock pulse, and since the counter only needs to be a counter that can follow the clock pulse, it is possible to measure time with a resolution that was previously impossible due to the ability of the counter, etc. The present invention has extremely significant effects.

Incidentally, in the embodiment, the event to be timed is defined as the period from the emission of light to the reception of light, but the present invention is not limited to this, and the present invention can be implemented to time measurement of any event, such as the passing time of a vehicle between set points. It's not as good as that.

[Brief explanation of the drawing]

1 to 3 are block diagrams showing an embodiment of the present invention, and FIGS. 4 to 8 are time charts explaining the operation of the embodiment of the present invention. 1...Clock pulse oscillator (clock oscillator),
2...Event cycle setting timer (event timer), 4...Light emitting element, 5...Light receiving element, 8...Event count counter (hit counter), 9...Phase operation unit (phase shifter), 11...Clock pulse number integration counter (counter) , 12... Division calculation unit (divider), 13... Event pulse oscillator (event oscillator).

Claims (1)

[Claims] 1. In a time measuring method that includes a clock pulse generation source and measures the duration of the event by counting the number of clock pulses during the duration of the event, occurs multiple times,
For N events (N is a natural number of N≧2), the phase relationship between the clock pulse and the start point of the event is set to be different on average within one cycle of the clock pulse, and the number of clock pulses during the event is set to the above N. A time measurement method that calculates the average value by calculating the number of times, and then calculates the duration of the event from this average value. 2. A phase difference of (K-1)·t/N (K is a natural number that is different for each event, K≦N, and t is the period of the clock pulse) is provided between the start point of each of the N events and the clock pulse. A time measuring method according to claim 1. 3. The time measuring method according to claim 1 or 2, wherein the phase difference between the start point of each event and the clock pulse is generated by manipulating the phase of the clock pulse. 4. The time measuring method according to claim 1 or 2, wherein a phase difference is generated between the start point of each event and the clock pulse by manipulating the phase of each event. 5 The relationship between the event period nt _E and the clock pulse is nt _E = m ₁ t + β (n, m ₁ are natural numbers, 0 < β <
t) The time measuring method according to claim 1, wherein the phase difference between the starting point of each event and the clock pulse is generated by setting β=t/N·m ₂ to satisfy. . However, t...Clock pulse period _m2 ...Natural number smaller than N and other than an integer multiple of a divisor of N _tE ...Original pulse period that creates the event period