JPH03122578A - Logical integrated circuit - Google Patents

Abstract

PURPOSE:To prevent the generation of the shift of timing relation between input data by making the test data transmitted by providing a latch between an external terminal and a function module to be tested periodic at a test rate. CONSTITUTION:The test data ST applied to external terminals EI1 - EIn are sent to the input terminals D1 - Dn of a latch circuit 4 while accompanied by delay times DI7 - DIn through a test circuit 2. These data are latched by the same clock Sc as the test rate inputted from an external terminal ETC in the latch circuit 4. As a result, the outputs Q1 - Qn of the latch circuit 4 are signals delayed by one rate from the aforementioned test data and these signals are inputted to the input terminals I1 - In of a function module 1. At this point of time, the shift of timing is not generated between the data ST inputted to the input terminals I1 - In of the function module 1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a logic integrated circuit, and particularly to a logic integrated circuit having a test circuit and a functional module under test.

[Conventional technology]

Advances in integrated circuit technology are rapidly increasing the upper limit of the number of elements that can be integrated.

As a result, it has become possible to realize a system that has conventionally been realized using a plurality of integrated circuits using a single logic integrated circuit.

In particular, from the viewpoint of ease of design, microprocessors, etc., which have conventionally been realized as separate logic integrated circuits, are not further divided into functions, and their design data (for example, layout data) are prepared as they are as functional modules, and the desired Many design methods have been proposed for realizing logic integrated circuits as a combination of these functional modules.

Now, as a problem associated with the increase in the number of elements, there is the problem of testing.

In general, the complexity of testing logic integrated circuits increases exponentially with the number of elements.

On the other hand, each functional module (for example, a part traditionally realized as a separate integrated circuit, such as a microprocessor)
For each, test data has already been created.

Therefore, it is essential to test each functional module completely separately from other parts using test data that has already been created.

A test method in which a predetermined functional module is completely separated from other parts in this way is called a separation test.

In particular, if the input terminals/output terminals of the functional module under test that are subject to this isolation test are not directly connected to external terminals, in addition to the circuit to realize the desired system configuration, this input terminal/output terminal A circuit (hereinafter referred to as a test circuit) for making the state directly controllable/observable from an external terminal is required outside the functional module.

FIG. 6 is a block diagram showing an example of a conventional logic integrated circuit.

Logic integrated circuit 10. The functional module under test 1 is sandwiched between test circuits 2 and 3 in series.

The test mode for the functional module under test 1 can be set by giving 0'' to the external terminal ET,
The input terminals 11 to 1 of the functional module l are connected to the external terminals E I r to E1 through the test circuit 2 in the test mode.
．． It shall be possible to control directly from

Similarly, output terminal 0 of functional module 1. -0. are connected to external terminals EO1 to E through test circuit 3 in test mode.
It is assumed that it is directly observable from Oyo.

It is assumed that the normal mode can be set by applying "1" to the external terminal ET, and each input terminal/output terminal of the functional module 1 is connected to a predetermined cutting edge/cutting edge through the test circuit 2/3.

On the other hand, test data is prepared in advance for the functional module under test 1, and the test data is input to the input terminal, ~
Figure 7 shows the test operation when applying the force to .

That is, the input terminals 11 to 1 of the functional module 1.

The test is performed by giving input data that changes simultaneously at a constant rate T to , sampling the values of the output terminals 01 to 0, and comparing them with the expected values.

When the delay time of the output terminals 01 to 0 with respect to input data is ~D, the test can be performed correctly by setting the sampling timing S larger than MAX (D, ~D,).

Here, it is the case that D is smaller than Dl.

Next, the operation of the conventional circuit shown in FIG. 6 will be explained.

When testing the functional module 1 under test, the functional module 1 is first isolated by applying "0" to the external terminal ET.

Next, the input terminals of the above-mentioned test data S are processed. The portions corresponding to external terminals E I + to E1. I will give it to

These data ST are sent through the test circuit 2 to the input terminals of the functional module 10.

Output terminals 01 to 0 for this. , the value of test circuit 3
Since it is output from external terminal EO, ~EO, through
By sampling these output values and comparing them with expected values, a predetermined test can be performed on the functional module under test l.

By the way, as shown in FIG. 8, the external terminals EI, .about.E1.
Test data that changes simultaneously at a constant rate T given to
Function module 10λ power terminal 1 after I+~DIn
1~Eng. reach.

That is, unlike the input signals shown in FIG. 7, the input data to the input terminals ˜I of the functional module 1 do not necessarily change simultaneously at a constant rate T.

This discrepancy in the timing relationship between the input data for function module 1 will cause a mismatch between the output data and the expected value, which will complicate the analysis, resulting in a significant increase in the development period. .

[Problem to be solved by the invention]

In the conventional logic integrated circuit described above, when testing the functional module under test by separating it from external terminals using test data prepared in advance, the timing relationship between the input data to the functional module under test is limited due to the signal delay time in the test circuit. As a result, it is necessary to analyze malfunctions due to discrepancies between output data and expected values, which has the disadvantage of significantly increasing product development time.

[Means to solve the problem]

The logic integrated circuit of the present invention has a plurality of functional modules prepared in advance, and one of the plurality of functional modules
In a logic integrated circuit that is tested separately as a functional module under test, the functional module under test;
a first group of external terminals each logically equivalent to a group of input terminals of the functional module under test during the test;
a second external terminal to which a test clock signal is input during the test; and a second external terminal provided between the first external terminal group and the input terminal group and input from the first external terminal group. The device is depicted as including a latch circuit that collectively latches all the test data for the input terminal group using the clock and supplies it to the input terminal group.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

The logic integrated circuit IO receives an external signal S between the test circuit 2 and the functional module under test l. The conventional integrated circuit 1 shown in FIG. 6 is different from the conventional integrated circuit 1 shown in FIG.
0. is the same as

FIG. 2 is a circuit diagram for explaining a more detailed structure of the latch circuit of FIG. 1. FIG.

The latch circuit 4 is a unit pit latch circuit 41. Inverter circuit 42. It has n latch sections each having AND circuits 43 and 44 and an OR circuit 45.

The unit pit latch circuit 41 receives a signal S. Assume that the value at input terminal A is latched and output to output terminal B upon the rising edge of the input.

It is assumed that the same test data as in the conventional example shown in FIG. 6 is prepared in advance for the functional module 1 under test.

Next, the operation of this embodiment will be explained.

First, prior to the test, the expected value on the output side of the test data prepared in advance is shifted backward by one button.

That is, the test data shown in FIG. 6(a) is set as shown in FIG. 3(b).

Further, by applying '0' to the external terminal ET, the functional module l to be tested is isolated.

FIG. 4 is a timing diagram of signals of various parts for explaining the test operation of the circuit of FIG. 1.

First, apply a clock signal S that is the same as the test rate to the external terminal ETC. Enter.

Next, input the test data described above. to external terminals E I + to E1. Let's make it correspond.

External terminals EI, ~EI. These test data S, given to D1. ~D.I. It is sent to the latch circuit 40 input terminals D1 to D7 with a delay time of .

These data are sent to the external terminal ETC in the latch circuit 4.
It is latched by the same clock Sc as the test rate input from.

As a result, the outputs Q1-Q of the latch circuit 4 are initially transferred to the external terminals EI, -E1. These signals are route-delayed from the test data input to the input terminals of the functional module l. is input. It should be noted that at this point, the input end of the function module l is clearly connected. There is no difference in timing between the data 37 input to the data 37.

Now, function module 1 has D1 to D for these inputs.
After a delay time of , a predetermined value is output from output terminals 0 and 01.

These values outputted from the functional module 1 are outputted through the test circuit 3 from the external terminals EO, to EO, with a delay time of DO1 to DO, .

As a result of the above, with respect to the test data initially input to the external terminals EI, ~EI, the operation result of the functional module 1 is D r + DO after l rate, and the external terminal E after a delay time of ~ D + Do. It will be obtained from O+ to EOU.

Therefore, a desired test can be performed by sampling the values of the external terminals EO, -EOI with S larger than MAX (DI+DO1 to Dm+DO,) and comparing them with the above-mentioned modified test data.

FIG. 5 is a block diagram of a second embodiment of the invention.

The difference from the first embodiment is that a latch circuit 5 is newly inserted between the output terminals 01 to 01 of the functional module under test 1 and the test circuit 3, and the other configurations are as follows. This is exactly the same as FIG. 1 of the first embodiment.

The effectiveness of this embodiment is determined by the delay time DO in the test circuit 3.
3~DOm is large, MAX (D, +DO1...
...D, , +DO,) exceeds test lay)T.

In this case, initially the external terminals E I r to E1. The operation results of the functional module under test 1 are obtained at the external terminals BO+ to EO after a delay time of DO1 to DO after two rates.

Therefore, by sampling the values of external terminals EO, ~EOI with S larger than MAX (Dot ~ DO Tests can be performed.

The detailed operation of this embodiment can be easily inferred from that of the first embodiment described above, so the explanation thereof will be omitted here.

〔Effect of the invention〕

As explained above, the present invention provides a latch between the external terminal and the functional module under test when testing the functional module under test prepared in advance by separating it from the external terminal using test data prepared in advance. By synchronizing the test data transferred between these at the test rate, technical problems may occur due to deviations in the timing relationship between the input data to the functional module under test, which causes a discrepancy between the output data and the expected value. It has the effect of preventing

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention;
The figure is a circuit diagram of the latch circuit in Figure 1, Figure 3 (a), (
b) is a diagram showing changes in test data in the first embodiment, FIG. 4 is a timing chart of signals of each part to explain the test operation of the circuit in FIG. 1, and FIG. 5 is a diagram showing changes in test data in the first embodiment. A block diagram showing an embodiment, FIG. 6 is a block diagram showing an example of a conventional logic integrated circuit, and FIG. 7 explains a test operation using test data prepared in advance for the functional module under test shown in FIG. 6. The timing diagram for Figure 8 is the timing diagram for Figure 6.
FIG. 4 is a timing diagram showing a delay in the test circuit of test data input from the external terminal shown in the figure. 1... Function module, 2, 3... Test circuit, 4.5... Latch circuit, 10, 10
．． ...Logic integrated circuit, 41 ... Unit pit latch circuit, 42 ... Inverter circuit, 4
3.44...AND circuit, 45...O
R circuit.

Claims (1)

[Claims] In a logic integrated circuit that has a plurality of functional modules prepared in advance and one of the plurality of functional modules is tested separately as a functional module under test, the functional module under test and the a first external terminal group each logically equivalent to the input terminal group of the functional module under test; a second external terminal to which a test clock signal is input during the test;
All test data for the input terminal group provided between the external terminal group and the input terminal group and inputted from the first external terminal group are latched together by the clock and sent to the input terminal group. A logic integrated circuit comprising: a latch circuit that provides a latch circuit.