JPH03119562A - Information reproducing device - Google Patents

Abstract

PURPOSE:To prevent the sudden change of a clock signal frequency and to smoothly perform a reproducing action by providing a frequency shift control circuit and gradually shifting and switching the clock frequency. CONSTITUTION:The frequency shift control circuit 100 is provided in a clock signal generation circuit 7. In the case of switching a fixed frequency clock signal generation circuit 8 to a variable frequency clock signal generation circuit 9, the output frequency of the circuit 9 is switched to the output frequency of the circuit 8 by the 1st switching control circuit 101 of the circuit 100 and the circuit 8 is switched to the circuit 9 by a 1st switch S1, then the output frequency of the circuit 9 is gradually changed to be shifted. Meanwhile, in the case of switching the circuit 9 to the circuit 8, the output frequency of the circuit 9 is gradually changed to be shifted by operating a 2nd switch S2. When it coincides with the output frequency of the circuit 8, the circuit 9 is switched to the circuit 8 through the switch S1. With such constitution, the sudden change of the clock signal frequency is prevented and the reproducing action is smoothly performed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information reproducing apparatus such as a CD player, and particularly to an information reproducing apparatus having a variable reproduction speed function suitable for so-called karaoke and the like.

[Conventional technology]

As a karaoke device, L V D (Lase + Vi
sionDisc) player, compact cassette, 8
Although track cassettes and the like are widely used, it is also possible to use CD players.

Usually, karaoke machines are equipped with a pitch control function so that the pitch can be adjusted to each person's pitch.

When a CD player is used as a karaoke device and is provided with a pitch control function, the pitch is controlled by making the playback speed of the CD variable for boat fishing. In this case, the problem is that when the playback speed is changed, the frequency of the clock signal used inside the CD player must also be changed. This is because, for example, the servo system may become out of synchronization.

FIG. 6 shows a schematic configuration of a conventional CD player having a variable playback speed function.

The CD player 1 rotates a CD at a predetermined speed using a spindle motor M, reads information on the CD using a pickup P, and outputs the information to an audio reproduction section 2 and a servo section 3. The audio reproduction section 2 converts the input information into an audio signal and outputs it. The servo unit 3 performs servo control such as spindle servo and tracking servo based on the input information. The control section 4 controls the entire CD player 1 based on input from the operation section 5, and causes the display section 6 to display playback information other than the audio playback signal as necessary.

The control section 4 is equipped with a clock signal generation circuit 7, and the CD player 1 operates based on the clock signal output from the clock signal generation circuit 7.

As shown in FIG. 7, the clock signal generation circuit 7 includes a fixed frequency clock signal generation circuit 8 that generates a first clock signal C81 with a fixed frequency, and a variable frequency clock signal generation circuit 8 that generates a second clock signal CS□ with a variable frequency. Generation circuit 9
, a first switch S that selectively switches the connection to the fixed frequency clock signal generation circuit 8 or the variable frequency clock signal generation circuit 9, and a second switch S that generates a control signal 10 that does not control the switching operation of the first switch S1. It is configured to include a switch S.

Next, the operation will be explained. The modes of switching the clock signal include switching from the first clock signal C3l to the second clock signal C32, and switching from the second clock signal C to the first clock signal C31.
There are two cases in which the clock signal is switched to C3l.

First, the case of switching from the first clock signal C81 to the second clock signal C32 will be described. Here, the first
It is assumed that the switch S1 is connected to the fixed frequency clock signal generation circuit 8 side.

Now, when the second switch S2 is turned on, the control signal 10
is transmitted to the first switch S1, and the first switch S1 is switched to the variable frequency clock signal generation circuit 9 side. As a result, the clock signal MC output to any circuit such as the audio reproduction section 2 is immediately switched to the second clock signal C32. As a result, the frequency fMo of clock signal MC
As shown in FIG. 8, when the second switch S2 is turned on at time 10, the first clock signal C suddenly changes.
The frequency fφ1 of the second clock signal C81 changes to the frequency fφ2 of the second clock signal C82.

Conversely, when switching the clock signal from the second clock signal C82 to the first clock signal C81, the second
Simultaneously with the switching of switch S2, the frequency fMC of clock signal MC changes rapidly.

[Problem to be solved by the invention]

The problem with the above conventional device is that at the same time as the switching operation of the second switch S2 is performed, the frequency fM of the clock signal MC is
The problem is that c changes rapidly. This is because, if the frequencies of both clock signals before and after switching are significantly different, the circuit that constitutes the audio playback section 2,
Among the circuits constituting the servo section 3, the circuits operating using the clock signal MC have the frequency f of the clock signal MC.
This is because there is a risk that a situation may arise in which it is not possible to follow sudden changes in MC. This effect leads to malfunctions such as skipping.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an information reproducing device that prevents sudden frequency changes in a clock signal when switching the clock signal in a CD player or the like, and enables smooth reproducing operation.

[Means to solve the problem]

In order to solve the above problems, the present invention has a clock signal generation circuit that can selectively switch and output a plurality of clock signals having different frequencies, and a In an information reproducing device that performs an information reproducing operation, when switching the clock signal, the frequency of the clock signal supplied to the information reproducing device is gradually shifted from the frequency of the clock signal before switching to the frequency of the clock signal after switching. It is configured to include a frequency transition control circuit.

[Effect]

According to the present invention, when the clock signal is switched, the frequency of the clock signal is gradually shifted from the frequency of the clock signal before switching to the frequency of the clock signal after switching by the frequency control circuit.

〔Example〕

Next, embodiments of the present invention will be described with reference to FIGS. 1 to 4.

FIG. 1 shows an embodiment of the present invention. Components that are the same as those in the conventional example shown in FIG. 7 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The difference from the conventional example shown in FIG. 7 is that the clock signal generation circuit 7
The present invention includes a frequency shift control circuit 100 that gradually shifts the frequency of the clock signal from the frequency of one clock signal to the frequency of the other clock signal when switching the clock signal. That is, the frequency shift control circuit 100 is connected between the second switch S2 and the first switch S1, and the frequency shift control circuit 100 provides the frequency control signal 13 to the variable frequency clock signal generation circuit 9. It has become.

The frequency transition control circuit 100 includes a first . Clock signal C8
When switching the clock signal MC from the first clock signal C32 having a fixed frequency to the second clock signal C32 having an arbitrary frequency, the variable frequency clock signal generating circuit 9 is controlled by the frequency control signal 13 to switch the first clock signal having a fixed frequency to the second clock signal C32 having a desired frequency. First switching control circuit 101 that gradually shifts to signal C82
When switching from the second clock signal C32 of an arbitrary frequency to the first clock signal C3l, the variable frequency clock signal generation circuit 9 is controlled by the frequency control signal 1-3 to switch from the second clock signal C82 of an arbitrary frequency to the first clock signal C3l. The second switching control circuit 10 gradually shifts to the 1 clock signal C81.
2.

When switching from the fixed frequency clock signal generation circuit 8 side to the variable frequency clock signal generation circuit 9 side, the first switching control circuit 101 changes the clock frequency of the variable frequency clock signal generation circuit 9 in advance to the fixed frequency clock signal generation circuit 8 side. Keep it the same as the clock frequency. Next, the first switch S1 is switched to the variable frequency circuit 9 side, and then the clock frequency of the variable frequency switching circuit 9 is gradually shifted to a desired frequency.

The second switching control circuit 102 switches the first switch S1 from the variable frequency clock signal generation circuit 9 side to the fixed frequency clock signal generation circuit 8 side when switching from the variable frequency clock signal generation circuit 9 side to the fixed frequency clock signal generation circuit 8 side.
The clock frequency of the variable frequency circuit 9 is gradually made to be the same as the clock frequency of the fixed frequency clock signal generation circuit 8 while the first switch SI is kept on the side of the fixed frequency clock signal generation circuit 8.

Here, the operation will be explained with reference to FIG. To simplify the explanation, a case will be described in which the frequency of the clock signal is changed from the frequency fφ1 of the first clock signal to the frequency fφ2 of the second clock signal. However, fφ 〈fφ2
shall be.

When the second switch S2 is turned on at time t, the clock signal MC gradually shifts to a higher frequency side, that is, the clock signal frequency f. is the transition frequency f from fφ
After passing through T, it becomes fφ2 at time J, and becomes a clock signal of a desired frequency. In this way, when switching the clock frequency of the clock signal, the frequency before switching gradually shifts to the frequency after switching, so that no sudden change in the clock signal frequency occurs. Therefore, the audio playback section 2
A circuit operating using the clock signal MC, such as the above, can follow the frequency change of the clock signal MC, and can operate normally.

FIG. 3 shows a more specific example of the embodiment shown in FIG.

The first switching control circuit 101 includes a charging circuit including a resistor R1 and a capacitor C, and the second switching control circuit 102 includes a discharging circuit including a resistor R and a capacitor C, and a discharging circuit including a resistor R1 and a capacitor C1.
and a delay circuit having a delay circuit.

Next, the operation will be explained based on the timing chart of FIG.

First, from the first clock signal C81 to the second clock signal C81,
The case of switching to 82 will be explained. Here, in the initial state, it is assumed that the first switch S1 is connected to the fixed frequency clock signal generation circuit 8 side, the second switch S2 is off, and the third switch s3 is on. At time to, the second switch S
2 is turned on, the control signal 1o becomes the ground level, and the first switch s1 is switched to the variable frequency clock signal generation circuit 9 side. At the same time, the third switch S3 is also turned off by the second switch control signal 11. At this time, the input voltage (2) of the voltage controlled oscillator 12 is at the ground level, and the oscillation frequency of the voltage controlled oscillator 12, that is, the transition frequency f of the second clock signal C82.

is the same as the clock frequency fφ1 of the fixed frequency clock signal generation circuit 8. After that, the voltage controlled oscillator 1
The input voltage V of 2 is the resistance R and V
Due to the time constant of the voltage control oscillator 12 and the time constant of the capacitor C, the voltage gradually becomes the desired voltage based on the voltage control position, and accordingly, the oscillation frequency of the voltage controlled oscillator 12, that is, the second clock signal C32
The transition frequency f. gradually changes, and reaches the set frequency fφ2 at time t1.

Here, operation 1 of the circuit shown in FIG. 3 when the characteristics of the voltage controlled oscillator 12 are as shown in FIG. 5 will be described. The input voltage of the voltage controlled oscillator 12 in FIG. Conversely, if the clock frequency of the fixed frequency generation circuit 2 or the clock frequency of the variable frequency generation circuit 3 is lower, the route shown by the broken line is followed. Similarly, when the clock signal frequency fMc is higher than the clock frequency fφ1 of the fixed frequency clock signal generation circuit 8 or the clock frequency fφ2 of the variable frequency generation circuit 9, the path shown by the solid line is followed, and conversely, the fixed frequency clock The clock frequency fφ1 of the signal generation circuit 8 is variable frequency clock signal generation circuit 9
If the clock frequency is lower than the clock frequency fφ2, the route shown by the broken line will be followed.

Thereafter, at time t2, when the second switch S2 is turned off again, the transition frequency f outputted by the variable frequency clock signal 2 signal generation circuit 9 gradually changes depending on the time constant of the resistor R and the capacitor C. The clock frequency fφ1 of the signal generating circuit 8 approaches and becomes equal at time t3. At the same time, the voltage of the control signal 10 gradually increases due to the time constant of the delay circuit C and the resistor R1, and the first switch S1 is switched to the fixed frequency clock signal generation circuit 8 side at time t4.

As described above, by gradually switching the clock frequency using the frequency transition control circuit 100, instantaneous changes in the operating clock frequency can be prevented, and malfunctions such as skipping can be prevented.

In the above description, switching between the first switch S1 and the third switch S3 was performed by a delay circuit, but it is also possible to perform switching under control of a microcomputer.

In addition, in the above explanation, the case where the frequency is changed using a fixed frequency clock signal generation circuit and a variable frequency clock signal generation circuit is described, but the frequency is changed by using a plurality of fixed frequency clock signal generation circuits having different frequencies. The present invention can also be applied to such cases. However, in this case, in order to make the speed variable for karaoke, it is necessary to include a variable frequency clock generation circuit in the transition frequency control circuit. Of course, it goes without saying that the present invention can also be applied to variable frequency clock generation circuits.

Furthermore, in the above description, a continuously variable type was used as the variable frequency clock signal generating circuit, but it is also possible to use a step variable type.

〔Effect of the invention〕

Since the present invention is configured as described above, in an information reproducing apparatus in which the reproduction speed can be changed, the operating clock frequency does not change instantaneously, and malfunctions do not occur at the time of switching.

[Brief Description of the Drawings] Fig. 1 is a block diagram of the clock signal generation circuit of the present invention, Fig. 2 is an explanatory diagram of the operation of the embodiment shown in Fig. 11, and 3 4 Fig. 3 is a block diagram of the embodiment of the embodiment shown in Fig. 1. A block diagram of a more specific example, FIG. 4 is an operation timing chart of the embodiment shown in FIG. 3, FIG. 5 is a diagram showing an example of the characteristics of a voltage controlled oscillator, and FIG. 6 is a block diagram of a conventional CD player. , FIG. 7 is a block diagram of a conventional clock signal generation circuit, and FIG. 8 is an explanatory diagram of the operation of the conventional example shown in FIG. 1...CD player 2...Audio playback unit 3...Servo unit 4...Control unit 5...Operation unit 6...Display unit 7...Clock signal generation circuit 8...Fixed Frequency clock signal generation circuit 9...Variable frequency clock signal generation circuit 10...Control signal 11...Second switch control signal 12...Voltage controlled oscillator 13 -Frequency control signal 100...Frequency transition control circuit 10 ↑...First switching control circuit 102...Second switching control circuit C81...First clock signal C82...Second clock signal Sl...First switch 82-...Second switch S3...・Third switch

Claims (1)

[Claims] A clock signal generation circuit that can selectively switch and output a plurality of clock signals having different frequencies, and performs an information reproducing operation based on the clock signal supplied from the clock signal generation circuit. The information reproducing device includes a frequency transition control circuit that gradually shifts the frequency of the clock signal supplied to the information reproducing device from the frequency of the clock signal before switching to the frequency of the clock signal after switching when switching the clock signal. An information reproducing device characterized by comprising: