JPH03118629A - Data transfer device - Google Patents

Abstract

PURPOSE:To reduce the load of a host system by storing both data and ECC parts of a sector including a detected read error into a buffer RAM and inhibiting the transfer of both parts to the host system. CONSTITUTION:The serial data read out through a hard disk driver HDD is directly decoded by an ECC decoding circuit EDEC. At the same time, the decoded serial data is converted into the parallel data by a parallel/serial conversion circuit P/S and stored in a data buffer memory DBM through an internal bus BUS. When the read data includes no ECC error, a data part stored in the DBM and its corresponding ECC part are transferred to a host system HOST. If an ECC error is detected, no data is transferred to the HOST and the end of abnormality is decided. Thus it is possible to reduce the load of the HOST and also to detect a bus transmission error via the circuit EDEC of the HOST side.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data transfer device, and relates to a technique that is effective for use in, for example, a hard disk memory control device.

[Conventional technology]

For example, in hard disk memory, multiple disks are attached to a common spindle. A head is attached to each side of each disk. These heads move in the radial direction of the disk surface. As a result, a plurality of concentric trunks (recording surfaces) are formed on each disk surface. Each track consists of several dozen sectors.

The spindle that rotates the disk is equipped with a sensor whose output tells it where the track begins.

This signal is called an index signal, and sectors are arranged in the correct order immediately after this signal. Each sector is ID (
It consists of a pair of an identifier section and a data section. The ID section and the data section each have ECC (Error Correct) for detecting and correcting read errors.
tion code) section is added.

Of these, 10 parts are made up of address information consisting of a cylinder address indicating the physical address of the cylinder, a head address indicating the physical address of the head, and a sector address indicating the logical address of the sector in the trunk.

[Problem to be solved by the invention]

In the above-mentioned hard disk memory control device, no consideration is given to transmission errors in the bus that connects the host system and the disk memory control device. For example, even if the disk memory control device successfully reads data from the disk, The host system may receive erroneous data due to the occurrence of a transmission error on the bus.

That is, there is a problem in that the host system cannot detect transmission errors on the bus.

Furthermore, even in the above-mentioned floppy disk memory control device equipped with instructions for transmitting and receiving a data section and a subsequent <ECC section, for example, when a disk read error is detected,
The data part and ECC part of the sector in which the error exists are transferred to the host system.

Therefore, a problem arises in that the burden of managing the number of read sectors on the host system increases.

An object of the present invention is to provide a data transfer device that can detect bus transmission errors while reducing the burden on the host system.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, a buffer RAM with a storage capacity of one sector.
When transferring the data section read from the memory and the ECC section added to it to the host system, the data section and ECC section of the sector in which the error exists are saved in the buffer RAM and transferred to the host system. Try not to.

[For production]

According to the above-mentioned means, the erroneous data section and ECC
Since no part is transferred, the host system can detect bus transmission errors while reducing the burden on the host system.

〔Example〕

FIG. 1 shows a block diagram of an embodiment of a hard disk control bag W (hereinafter sometimes simply referred to as HDC) to which the present invention is applied.

In the figure, each circuit block surrounded by a dashed line is
It is formed on a single semiconductor substrate such as, but not limited to, single crystal silicon using known semiconductor integrated circuit manufacturing techniques.

Processing unit PU receives clock signal CLK, reset signal R3T, and signals ERR and COR from an ECC decoding circuit as described later, and forms various control signals and timing signals (not shown) necessary for operation of internal circuits.

The multiplexer MPX is coupled to a peripheral bus (I10 bus) as described later on the host system HO3T side, and is used to send and receive write/read data and to
Receives commands supplied from O3T.

Data exchanged via multiplexer MPX is stored in data buffer memory DBM.

Although not particularly limited, the data buffer memory DBM
has a two-sided buffer memory and is designed to exchange data at high speed. Therefore, data buffer memory DB
The human output section of M is provided with a multiplexer circuit for alternately switching between the two panzer memories.

The commands supplied via the multiplexer MPX are:
The signal is supplied to the register section REG. This register section REG
has a command register, a status register indicating the status of the IDC, etc.

The control circuit C0NT receives a write/read control signal, an interrupt signal, etc. supplied from the host system HO3T, and controls the switching operation of the multiplexer Mpx.

The format control circuit FC generates write/read data, internal synchronization signals, etc. for the hard disk driver HDD, and performs parallel/read data as described below.
It includes a serial conversion circuit P/S, an ECC code circuit EC0D, and an ECC decoding circuit EDEC. The parallel/serial conversion circuit P/S transmits and receives data in bytes in parallel with the internal bus BUS, and serially transmits and receives data in bits with a hard disk driver HDD (not shown).

The ECC decoding circuit EDEC is the hard disk driver H
It receives read data from the DD and performs error detection and correction (decoding). Furthermore, in the command to load the data part received from the host system HOST and the ECC part added thereto into the hard disk driver HDD, the data received from the host system HO3T is decoded.

The ECC code circuit EC0D generates (encodes) an ECC part in a command to receive only the data part from the host system and write it to the hard disk driver HDD. Here, the ECC code circuit EC0D is not needed in a hard disk control device that supports only instructions to which the present invention is applied. The above ECC is a CRC (Cyclic
In other words, ECC in this embodiment is used as a general term for error detection code and error correction. When a read error is detected, an error detection signal ERR is transmitted to the processing unit PU, and when error correction is successfully completed, a COR signal is transmitted to the processing unit PU.

The disk interface DIG generates drive selection signals, head selection signals, and the like.

Processing unit PU1 data buffer memory DBM, register section REG, format control circuit FC
and the disk interface DIC is connected to the internal bus BU.
They are connected to each other via S.

FIG. 2 shows a block diagram of an embodiment of a microcomputer system equipped with the above HDC.

The host system HO3T is a microprocessor MPU
, a main memory MEM, a direct memory access controller DMAC, and a host adapter 1 (ADP).The host adapter HADP is composed of an ECC code circuit EC0D, an ECC decoding circuit EDEC, and an I10 bus conversion circuit IC0N similar to those described above. The I10 bus conversion circuit IC0N is the system bus and peripheral bus (■10 bus)
Perform a physical transformation with. The host system HO3T and the hard disk control bag WHDc are connected by a peripheral bus (I10 bus).

Next, the operation of the hard disk controller HDC when it receives a command to transfer the data part and ECC part to the host system HO3T will be explained.

Serial data read through the hard disk driver HDD is directly decoded by the ECC decoding circuit EDEC, and at the same time, it is decoded by the parallel/serial conversion circuit P/
After being converted to parallel data by S, internal bus BU
The data is stored in the data buffer memory DBM through S.

When there is no ECC error in the read data, the data section stored in the data buffer memory DBM and the ECC section corresponding thereto are transferred to the host system HO3T.

When an ECC error is detected in the read data, two types of processing are performed depending on whether the automatic correction mode is selected. If it is not the automatic correction mode, the read data is not transferred to the host system HO3T and the process ends abnormally. In automatic correction mode, automatic correction is performed, and if correction is possible, the corrected data is sent to the host system HO3T.
If correction is not possible, the read data is not transferred to the host system HO3T and the process ends abnormally.

Next, the hard disk controller ID when the host system HO3T receives a command to write the data section and ECC section to the hard disk driver HDD.
The operation of C will be explained.

Data received from the host system HO3T is stored in the data buffer memory DBM and simultaneously transferred to the parallel/serial conversion circuit P/S via the internal bus. After being converted to serial data, ECC decoding circuit E
TIf! Checks whether there is an ECC error by DEC! recognized. If there is no ECC error, the data stored in the data buffer memory DBM is transferred to the hard disk driver H.
Written to DD. If an ECC error is detected,
In other words, if an error occurs in the peripheral bus (110 bus) that connects the host system HO3T and the hard disk drive device IDC, the next It is divided into two types of processing. If it is not in the automatic correction mode, the receiver terminates abnormally without loading the received data to the hard disk driver HDD.

In automatic correction mode, automatic correction is performed, and if correction is possible, the corrected data is transferred to the hard disk driver HD.
If correction is impossible, the data is not written to the hard disk driver (IDD) and the process ends abnormally.

This also applies to the host system HO5T. That is, when an error occurs on the above-mentioned I10 bus, the ECC decoding circuit EDEC included in the host adapter HADP detects the data error and performs automatic correction according to the above-mentioned automatic correction mode.

The effects obtained from the above examples are as follows. That is, (1) A buffer RAM with a storage capacity of at least one sector is provided, and when the data section read from the memory and the ECC section added to it are transferred to the host system, the sector in which the error exists is By saving the data part, ECC part, and buffer RAM and preventing it from being transferred to the host system, the error data part and tEc
Since part c is not transferred, it is possible to reduce the burden on the host system and to have the effect that bus transmission errors can be detected by the ECC decoding circuit on the host system side.

(2) When equipped with an automatic correction function, the effect of increasing data transfer efficiency is to perform data writing, etc. when correction is possible according to the result of automatic correction, and terminate abnormally when correction is not possible. It will be done.

Although the invention made by the present inventor has been specifically explained based on Examples above, the present invention is not limited to the above-mentioned Examples, and it goes without saying that various changes can be made without departing from the gist thereof. Nor. For example, in addition to hard disk memory, the present invention can be similarly applied to floppy disk memory and the like.

In addition to the above-mentioned disk memory, the memory may also be one that uses magnetic tape, or a V-conductor RAM or RO.
It may be M, etc. In other words, the above-mentioned method can also be applied to a data transfer device that transfers data in these memories to a host via a peripheral bus.

The present invention can be widely used in data transfer devices that transfer data stored in memory.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. In other words, a buffer RAM having a storage capacity of at least one sector is provided, and when the data portion read from the memory and the ECC portion added thereto are transferred to the host system, the data portion of the sector in which the error exists and E
The data is saved in the CC unit and buffer RAM so as not to be transferred to the host system. This configuration reduces the burden on the host system because it does not transfer the erroneous data part and ECC part.
It can be detected by a CC decoding circuit.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a hard disk control device to which the present invention is applied, and FIG. 2 is a block diagram showing an embodiment of a microcomputer system equipped with the hard disk control device. IDC...Hard disk control device, PU...Processing unit, MPX...Multiplexer, DBM...
Data buffer memory, REG... register section, C0N
T...control circuit, BUS...internal bus, DIC...disk interface, FC...format control circuit, P/S...parallel/serial conversion circuit, EC0D...
・ECC code circuit, EDEC...ECC decoding circuit, HO
8'F...Host system, HDD...Hard disk driver, MPU...Microprocessor, MEM...
・Main memory, DMAC・・Direct memory access controller i・Roller, E(ADP・・Host adapter, I
CON...I10 bus conversion circuit.

Claims (1)

[Scope of Claims] 1. A buffer RAM that has the function of transferring the data section read from the memory and the ECC section added thereto to the host system, and has a storage capacity of at least one sector of the data section and the ECC section. 1. A data transfer device characterized in that when a read error is detected, the data part and ECC part of a sector in which an error exists are stored in a buffer RAM and are not transferred to a host system. 2. The data transfer device is characterized in that when the read error is detected, if the error can be corrected using a built-in automatic correction function, the data transfer device transfers the corrected data part and ECC part to the host system. A data transfer device according to claim 1.