JPH03117160A - Automatic level adjustment device - Google Patents

Abstract

PURPOSE:To realize an automatic level adjustment device with high control efficiency and wide level adjustment range by controlling a charge storage time in response to an output level of a CCD to adjust the output level of the CCD to a prescribed level automatically. CONSTITUTION:A sample-and-hold circuit 2 samples and holds a reference white level signal from a CCD image sensor 1 in response to a sample-and-hold pulse PSH to output a pseudo white level signal VW. A comparator circuit 4 compares a reference voltage VS supplied separately with the pseudo white level signal VW and applies the output to a switching control circuit 18. When the pre-scanning is finished and the original picture is scanned, the switching control circuit 8 fixes a transfer gate pulse PTG till the original picture scanning is finished. Simultaneously, the sample-and-hold circuit 2 samples and holds the picture signal from the CCD image sensor 1 with the sample-and-hold pulse PSH from a sample-and-hold pulse control circuit 3 to give the result to an A/D converter circuit.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an automatic level adjustment device, particularly in a plane scanning type reader of image information including halftones, when the amount of light emitted from a fluorescent lamp as a light source changes. The present invention relates to an automatic level adjustment device that prevents fluctuations in output level.

[Conventional technology]

In general, black and white binary image reading devices use the so-called automatic slicing method, in which the slice level for binary conversion is changed based on the original image base paper density obtained from the image sensor. Changes in the amount of fluorescent light emitted by the fluorescent lamp over time and changes in ambient temperature can be virtually ignored.

In flat scanning type reading devices for image information including halftones, it is necessary to detect the absolute level of original images such as photographs. It is necessary to control the output level so that changes in the amount of emitted light do not cause fluctuations in the output level of the image sensor.

Conventionally, this type of automatic level adjustment device includes, for example,
By detecting the amount of light emitted by the fluorescent lamp with a light-receiving diode, comparing the output voltage from the light-receiving diode with a preset reference voltage, and controlling the input current of the fluorescent lamp according to the comparison result, Changes in the amount of emitted light are maintained within a certain range to prevent fluctuations in the image signal level from the image sensor.

[Problem to be solved by the invention]

In the above-mentioned conventional automatic level adjustment device, not only does the single DC source capacity for lighting the fluorescent lamp become large, but a portion of the change in the input terminal is converted into thermal energy and becomes ineffective, resulting in poor control efficiency. , and the input current cannot be changed over a wide range, so there is a problem that the variable control range is narrow.

[Means to solve the problem]

The automatic level adjustment device of the present invention includes a CCD image sensor that outputs a reference white signal during a pre-scanning period prior to scanning an original image, and a CCD image sensor that outputs a reference white signal corresponding to one scanning line at a predetermined period n(n; a sample-and-hold circuit that samples and holds a pixel level corresponding to a pixel (positive integer) and outputs a pseudo-white signal; a comparison circuit that compares the pseudo-white signal from this sample-and-hold circuit with a preset reference voltage;
A plurality of transfer gate pulse generation circuits that generate transfer gate pulses that set the accumulation time of the CCD image sensor, and a plurality of transfer gate pulses from the plurality of transfer gate pulse generation circuits are switched according to the comparison result of the comparison circuit. It includes a switching control circuit, and is configured to adjust the level by changing the storage time of the CCD image sensor.

[Effect]

In the present invention, a CCD (Charge Couple
The charge accumulation time is controlled according to the output level of the CCD (edDevica), and the output level of the CCD is automatically adjusted to a predetermined value.

〔Example] Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In the figure, 1 is a CCD image sensor that outputs a reference white signal during a pre-scanning period prior to scanning an original image, and 2 is a CCD image sensor that outputs a reference white signal during a pre-scanning period prior to scanning an original image.
: Positive integer) A sample and hold circuit that samples and holds the pixel level corresponding to the pixel and outputs a pseudo white signal.
3 is a sample and hold pulse control circuit; 4 is a comparison circuit that ratios the pseudo white signal from the sample and hold circuit 2 to a preset reference voltage; and 5, 6.7 is a transfer circuit that sets the accumulation time of the CCD image sensor 1. A transfer gate pulse generation circuit 8 that generates a gate pulse is a comparison control circuit that switches a plurality of transfer gate pulses from the transfer gate pulse generation circuits 5 to 7 according to the comparison result of the comparison circuit 4.

The device is configured to adjust the p level by changing the storage time of the CCD image sensor.

Figure 2 is a time chart used to explain the operation of Figure 1.
&) indicates the transfer gate pulse Pro; (
b) shows the reference white signal V, (e) shows the sample hold pulse pgu, and (d) shows the pseudo white signal vv. And ■ indicates the reference voltage.

Next, the operation of the embodiment shown in FIG. 1 will be explained with reference to FIG. 2.

First, during a pre-scanning period prior to scanning the CCDC image sensor original image, for example, a reference white plate provided in the original image reading section (not shown) is main-scanned to output a reference white signal V, and the sample is held. Supplied to circuit 2.

This reference white signal V has a main scanning period T, and the envelope of the white pixel level forming each scanning line is high at the center and low at the periphery due to the lens characteristics of the reading unit. , which has a so-called shading waveform 2, where the period T is the period of the transfer gate pulse PTG, which is the output signal from the transfer gate Hals generation circuits 5 to 7.

Also, each pixel level is the CCD image sensor 1
is the output level corresponding to each individual optical sensor.

- The sample bold pulse control circuit 3 generates a sample hold pulse PIT with period T! 1 is generated and supplied to the sample hold circuit 2. This sample hold circuit 2 is CC
The reference white (No. S) from the D image sensor 1 is sampled and held in response to the sample-and-hold pulse PIIH, and the pseudo-confidence -vw shown in FIG. 2(d) is output.

Here, the pulse width of the sample and hold pulses P, , I corresponds to n pixels (n is a positive integer), and the sample and hold pulses are sampled and held at the average level of the pixel level corresponding to n pixels.

This removes the effects of shading mentioned above,
In addition, by setting n to a plurality of values, it is possible to prevent malfunctions caused by fine scratches, dust, etc. on the reference white plate.

The pseudo white signal VW from the sample hold circuit 2 is supplied to the comparison circuit 4. This comparator circuit 4 compares the reference voltage V, which is supplied separately in advance, with the pseudo white signal VW, and outputs a "-high" level when the potential of the pseudo white signal 1 is high, and a "low" level when it is low. Switching 11] Supply 8V to both circuits. Furthermore, m transfer gate pulse generation circuits are connected to this switching control circuit 8.

Next, prior to explaining the operation of the transfer gate pulse generating circuits 5 to 7, the principle of automatic adjustment of the output level of the CCDC soy sensor 1 will be explained with reference to FIG.

FIG. 3 is a diagram showing the relationship between the exposure amount (Lux-sec) and the output level (V) for the CCD. In general, C
The output level of the CD is proportional to the amount of charge stored in the COD. That is, the amount obtained by time-integrating the amount of light irradiated onto the COD is accumulated.

As shown in FIG. 3, the output level (V) increases in proportion to the exposure amount until the exposure amount increases and reaches the saturation level a. As long as the cycle of the transfer gate pulse pyo that controls the accumulation time is longer than time t1 and shorter than time t2, the CCD can operate without problems. However, time t! is the shortest accumulation time to transfer a predetermined focus, and time t2 is the accumulation time when the output level reaches the saturation point.

Therefore, transfer gate pulse P? . ``tl〈P,.

By varying the cycle within the range of t2, the output level (V) of the CCD can be made variable at the same amount of irradiation light.

There are m transfer gate pulse generation circuits, each of which generates a signal with a different period. That is,
A transfer gate pulse p is output from the transfer gate pulse generation circuit 5.
ta I is output, the transfer gate pulse generation circuit 6 outputs the transfer gate pulse PTG2, and the transfer gate pulse generation circuit 7 outputs the transfer gate pulse P? . . is output.

In FIG. 1, from the point of view of period, Pta+<Pa. 2ku...<pt. . It becomes. In the initial state, the switching control circuit 8 receives a transfer gate pulse PTO! which is a signal from the transfer gate pulse generating circuit 5. Select. Further, the switching control circuit 8 sequentially selects the transfer gate pulse PTG with a long period when the output level from the comparator circuit 4 is 10-'' level, and selects the transfer gate pulse PTG with a short period when the output level is ``high'' level. works to select.

Now, as shown in FIG. 2, when the pseudo white signal v1 is lower than the reference voltage vlI, the output level from the comparator circuit 4 is "low" and the period of the transfer gate pulse PTG from the switching control circuit 8 is becomes longer. Therefore, from FIG. 3, the level of the reference white signal vP of the CCD image sensor 1 becomes high. Then, the level of the reference white signal V increases,
When the pseudo white signal VW becomes higher than the reference voltage 6, the output level from the comparison circuit 4 becomes 1-high.

When the "high" level is input, the switching control circuit 8 stops switching the signal from the transfer gate pulse generation circuit.

Then, when the pre-scanning is finished and the scanning of the original image begins, the switching control circuit 8 outputs a transfer gate pulse P? . is fixed until the scanning of the original image is completed. At the same time, the sample hold circuit 2 pull-holds the image signal from the PCCD image sensor 1 for each pixel level using the sample hold pulse P811 from the sample bold pulse control circuit 3, and converts it to an analog-to-digital conversion circuit (not shown). supply

In this way, since fluorescent lamps are used at their rated values, the DC power supply only needs to be small and small in capacity, and there is no loss of energy during level adjustment, resulting in high control efficiency. Moreover, since the time t2 can usually be at least 10 times longer than the time tl, the range of level adjustment can be widened.

〔Effect of the invention〕

As explained above, the present invention, instead of automatically controlling the amount of emitted light by changing the input current of the fluorescent lamp, controls the charge accumulation time according to the output level of the COD, and sets the output level of the CCD to a predetermined value. By automatically adjusting to
It is possible to control the fluorescent lamp for a long period of time, reducing the frequency of adjusting the light amount when replacing the lamp, and reducing the cost of the device.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing one embodiment of the present invention, Fig. 2 is a time chart for the operation blessing shown in Fig. 41, and Fig. 3 is a block diagram showing an embodiment of the present invention.
FIG. 3 is a diagram showing the relationship between exposure amount and output level with respect to OD. 11I...COD image sensor, 2@...sample hold circuit, 4...comparison circuit, 5-7...
Transfer gate pulse generation circuit, 8... switching control circuit.

Claims (1)

[Claims] A CCD image sensor that outputs a reference white signal during a pre-scanning period prior to scanning an original image, and a pixel corresponding to n (n: positive integer) pixels at a predetermined period for each reference white signal corresponding to one scanning line. A sample and hold circuit that samples and holds the level and outputs a pseudo white signal, a comparison circuit that compares the pseudo white signal from this sample and hold circuit with a preset reference voltage, and an accumulation time of the CCD image sensor is set. The CCD includes a plurality of transfer gate pulse generation circuits that generate transfer gate pulses, and a switching control circuit that switches the plurality of transfer gate pulses from the plurality of transfer gate pulse generation circuits in accordance with a comparison result of the comparison circuit. An automatic level adjustment device characterized in that level adjustment is performed by changing the accumulation time of an image sensor.