JPH03117106A - Differential amplifying circuit - Google Patents

Abstract

PURPOSE:To suppress flicker noise and an offset voltage without limiting high speed operation by constituting the circuit of a pair of differential bipolar transistors, and an active load consisting of a pair of MOSFETs formed in a current mirror provided the collector sides of the differential bipolar transistors. CONSTITUTION:As for the differential amplifying circuit, a pair of NPN type bipolar transistor T1, T2 contained in an A/D converting circuit of a MODEM for communication, and brought to differential form are its fundamental constitution. To bases of these transistors, a prescribed complementary input signal is supplied from a pre-stage circuit of the A/D converting circuit. Between collectors of T1 and T2, and a power supply voltage Vcc of the circuit, a pair of P channel MOSFETs Q1, Q2 are provided. The MOSFETs Q1, Q2 are brought to current mirror form, and operate as an active load to the differential transistors T1, T2. By using the bipolar transistor as an input transistor, a flicker noise is suppressed, and also, by constituting the active load of the MOSFET, an offset voltage is suppressed.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to a differential amplifier circuit, for example, an A/D (analog/digital) conversion circuit of a communication modem (MODEM). The present invention relates to a technique that is particularly effective when used in the included differential amplifier circuit.

[Conventional technology]

Basically, a pair of differential MOSFETs (metal oxide semiconductor field effect transistors; in this specification, MOSFETs are collectively referred to as insulated gate field effect transistors) or differential bipolar transistors (hereinafter abbreviated as transistors). There is a differential amplifier circuit configured as follows. Also,
There are A/D conversion circuits that include differential amplifier circuits, and there are communication modulation and demodulation devices that include such A/D conversion circuits.

Regarding differential amplifier circuits, for example, see the IEEE Journal of Solid State Circuits (December 1982).
nal Of 5olid-3tate C1r-
Cuits) Vol. SC17, No. 6J, etc.

[Problem to be solved by the invention]

In Figure 2, a pair of differential MOSFETs QI 2 and Q13 are shown.
A circuit diagram of a conventional CMO3 type O3 amplifier circuit having the basic configuration is illustrated. Further, FIG. 3 illustrates a circuit diagram of a conventional bipolar differential amplifier circuit whose basic configuration is a pair of differential transistors T5 and T6.

Among these, in the CMO3 type O3 amplifier circuit shown in FIG.
An active load consisting of Q4 and Q4 is provided. Therefore, the operating current supplied by the constant current source consisting of MOSFET QI4 is
2 and Q13, thereby eliminating the offset voltage of the differential amplifier circuit. On the other hand, in the bipolar differential amplifier circuit shown in Fig. 3, by using differential transistors as the basic configuration, the amplification factor of the differential amplifier circuit can be increased. The S/N ratio of the amplifier circuit can be increased.

However, the inventors of the present application have discovered that these differential amplifier circuits each have the following problems. In other words, the S/N ratio of a differential amplifier circuit is influenced by the flicker noise generated from the differential transistors in the input stage, especially when the MOSFET has a horizontal structure.
In the differential amplifier circuit shown in Fig. 2, which has the basic configuration as follows, the input MO
Flicker noise generated from SFETQ12 and Q13 greatly reduces the S/N ratio of the differential amplifier circuit. As is well known, the flicker noise Veq in a differential amplifier circuit is calculated by setting the channel width and channel length of the input MOS FET to WI and Ll, respectively, and the load MOS FET to
The channel length of T is L2, the flicker-noise coefficients of P-channel MC) SFET and N-channel MOSFET are Kp and Kn, respectively, and the mobility is μp and μn, respectively.
, when the frequency is f, which is inversely proportional to the channel width and channel length of the input MOSFETs QI2 and Q13. Therefore, to reduce flicker noise, input MOSFET QI
It is necessary to increase the size of Q2 and Q43, ie, the channel width and channel length. This increases the required layout area of the differential amplifier circuit, increases the parasitic capacitance of the input MOSFETs Q12 and Q13, and becomes a factor that limits speeding up of the differential amplifier circuit.

On the other hand, in the bipolar differential amplifier circuit shown in FIG. 3, the input transistors are replaced with bipolar transistors T5 and T6 of a so-called vertical product structure, so that the flicker noise as described above is almost not a problem. However, the slight difference in the base currents of the transistors T3 and T4 that constitute the active load causes the differential transistors T5 and T6 to
This causes a relatively large imbalance in the collector currents of the differential amplifiers, increasing the offset voltage of the differential amplifier circuit.

An object of the present invention is to suppress flicker noise in a differential amplifier circuit without increasing the required layout area and limiting high speed, and without increasing the offset voltage. Another object of the present invention is to reduce the cost and speed up and stabilize the operation of an A/D conversion circuit and a communication modulation device including a differential amplifier circuit.
The purpose is to increase the S/N ratio.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a differential amplifier circuit included in an A/D conversion circuit or the like of a communication modulation sub-device is constructed by a pair of differential bipolar transistors receiving complementary input signals and a current mirror provided on the collector side of the differential bipolar transistors. It is basically configured with an active load consisting of a pair of MOS FETs.

[For production]

According to the above-described means, by using a bipolar transistor as the input transistor, it is possible to suppress flicker noise without increasing the required layout area of the differential amplifier circuit and without limiting its speedup. In addition, the active load can be MOS
By using FETs, the collector currents of the differential bipolar transistors can be made uniform, and the offset voltage of the differential amplifier circuit can be suppressed. As a result, the A/D conversion circuit including the differential amplifier circuit and the communication modulation/demodulation device can be lowered in cost and operated faster and more stably, while increasing the S/N ratio thereof.

〔Example〕

FIG. 1 shows a circuit diagram of an embodiment of a differential amplifier circuit to which the present invention is applied. Although the differential amplifier circuit of this embodiment is not particularly limited,
Included in the conversion circuit. Each circuit element in the figure is formed on one semiconductor substrate such as single crystal silicon, although not particularly limited, together with other circuit elements (not shown) of the A/D conversion circuit and the communication modem/demodulator. In addition, the first
In the figure, the MOSFET whose channel (back gate) part is marked with an arrow is a P-channel type, and
It is shown to be distinguished from the N-channel O5FET, which is not marked with an arrow. Further, among the illustrated bipolar transistors, transistors T3 and T4 are PNP transistors, although not particularly limited, and all other transistors are NPN transistors.

In FIG. 1, the basic configuration of the differential amplifier circuit is a pair of bipolar transistors T1 and T2 in a differential configuration. The base of these transistors has an A/D
Predetermined complementary input signals, that is, a non-inverting input signal Vip and an inverting input signal V, are supplied from a pre-stage circuit (not shown) of the conversion circuit.
ln are respectively supplied.

A pair of P-channel MOSFETQ is connected between the collectors of transistors T1 and T2 and the circuit power supply voltage Vcc.
I and Q2 are provided. Here, the circuit power supply voltage Vc
c is a positive power supply voltage such as +5V, although it is not particularly limited. The gates of the MO5FETs Q1 and Q2 are commonly coupled, and, although not particularly limited, the gates of the MO5FETs Q1 and Q2 are also connected to a transistor T
1 collector. This allows MOSFET
Q2 and Q2 are in the form of a current mirror and act as active loads for the differential transistors T1 and T2. MO8
The drain voltage of FETQ2, that is, the collector voltage of transistor T2, is the output voltage of the differential amplifier circuit ■0,
The signal is supplied to a subsequent stage circuit (not shown) of the A/D conversion circuit.

The commonly coupled emifters of the differential transistors T1 and T2 may be N-channel MOSFETQ, although not particularly limited.
I1 is coupled to the circuit's ground potential. MOSF
A predetermined constant voltage Vg is supplied to the gate of ETQI 1 from a voltage generating circuit (not shown) of a communication modulation/demodulation device. Thereby, the MOSFET QI 1 acts as a constant current source that provides a predetermined operating current according to the constant voltage Vg to the differential transistors TI and T2. As aforementioned,
MOSFETs QI and Q2 are in a current mirror configuration. Therefore, the operating current supplied by the constant current source is uniformly shunted to the transistors T1 and T2, thereby suppressing the offset voltage of the differential amplifier circuit.

When the levels of the non-inverting input signal ip and the inverting input signal Vin match, the transistors T1 and T2 have approximately the same conductance, and the output voltage Vo is a predetermined value determined by the shunted operating current and the conductance of the transistor T2. It becomes an intermediate potential. However, when the non-inverting input signal Vip becomes higher than the inverting input signal Vin and the base current of the transistor T1 is made larger than that of the transistor T2, the conductance of the transistor T1 is increased, and conversely, the conductance of the transistor T2 is decreased. As a result, the output voltage VO is high. On the other hand, when the non-inverting input signal Vip becomes lower than the inverting input signal Vin and the base current of the transistor T1 is made less than that of the transistor T2, the conductance of the transistor T1 is made small; Instead, the conductance of the transistor T2 is increased.As a result, the output voltage VO is lowered.That is, the output voltage vO is lower than the non-inverting input signal Vip.
The inverted input signal Vln is changed in phase in response to changes in Vln.
It changes in the opposite phase in response to the change in .

By the way, as mentioned above, the differential amplifier circuit of this embodiment has the basic configuration of differential transistors T1 and T2. As is well known, these bipolar transistors have a so-called vertical stack structure, and the flicker noise caused by surface current on the semiconductor substrate surface is so small that it does not pose a problem. Therefore, it is not necessary to increase the size of the input transistor in order to suppress flicker noise, and there is no increase in parasitic capacitance due to the increase in the size of the input transistor.

As described above, the differential amplifier circuit of this embodiment is included in the A/D conversion circuit of the communication modem device, and the complementary input signal Vi
A pair of differential bipolar transistors T1 and T2 receiving p-Vin, and a pair of P transistors provided on the collector side of these differential bipolar transistors in a current mirror configuration.
and an active load consisting of channel MOSFETs QI and Q2. The differential amplifier circuit further includes a constant current source provided between the commonly coupled emitters of the differential transistors T1 and T2 and the ground potential of the circuit, and the operating current supplied by the constant current source is The current is uniformly shunted to dynamic transistors T1 and T2. For these reasons, in this example, the active load is a pair of MOs in the form of a current mirror.
SFET (consisting basically of hl and Q2, the operating current supplied from the constant current source is the differential transistor T1, T
2, the off-cent voltage of the differential amplifier circuit is suppressed, and since the input transistor is composed of a bipolar transistor with a so-called vertical product structure, it is possible to reduce the offset voltage of the differential amplifier circuit without increasing its size. Noise can be suppressed. Therefore, without increasing the required layout area of the differential amplifier circuit and limiting its high-speed operation, and without increasing its offset voltage,
The flicker noise can be suppressed and the S/N ratio can be increased. As a result, it is possible to reduce the cost of the A/D conversion circuit including the differential amplifier circuit, and ultimately to the communication modulation/demodulation device, and to increase the speed and stability of the operation while increasing the S/N ratio thereof.

2. As shown in the above-described embodiments, the following effects can be obtained by applying the present invention to a differential amplifier circuit included in an A/D conversion circuit or the like of a communications modulation/demodulation device. In other words, (11) a differential amplifier circuit included in an A/D conversion circuit, etc. of a communications modem is connected to a pair of differential bipolar transistors that receive complementary input signals, and a current mirror provided on the collector side of the differential bipolar transistors. By basically configuring an active load consisting of a pair of MOSFETs in the same configuration, it is possible to suppress flicker noise of the differential amplifier circuit without increasing the size of the input transistor.

(2) According to the above item (11), the S/N ratio of the differential amplifier circuit can be increased without increasing the required layout area and limiting the speedup of its operation.

(3) According to the above item (1), it is possible to equally divide the operating current supplied from the constant current source to each of the differential bipolar transistors, thereby making the collector currents uniform.

(4) Item (3) above provides the effect of suppressing the offset voltage of the differential amplifier circuit.

(5) Items (1) to (4) above reduce the cost, speed up, and stabilize the operation of A/D conversion circuits including differential amplifier circuits, as well as communication modem devices including A/D conversion circuits. It is possible to obtain the effect that the S/N ratio can be increased while achieving the same.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in FIG. 1, the power supply voltage Vcc of the circuit can be replaced with a ground potential, and the ground potential of the circuit can be replaced with a negative power supply voltage such as -5.2V. Furthermore, by reversing the polarity of the power supply voltage, the differential transistors T1 and T2 can be replaced with PNP type bipolar transistors, and the MOSFETs Q1 and Q2 can be replaced with N-channel MO, 5FETs. The constant current source provided between the commonly coupled emitters of the differential transistors T1 and T2 and the ground potential of the circuit may be configured based on a bipolar transistor, or may be configured, for example, in series with these constant current sources. , a switch means for selectively operating the differential amplifier circuit may be provided. For example, a circuit for stabilizing or compensating the frequency characteristics of the differential amplifier circuit may be added to the front and rear stages of the differential amplifier circuit. Furthermore, the specific circuit configuration of the differential amplifier circuit shown in FIG. 1 can take various embodiments.

In the above explanation, the invention made by the present inventor was mainly explained in the case where it was applied to a differential amplifier circuit included in an A/D conversion circuit of a communication modem and demodulator, which is the field of application in which the invention was made, but it is limited to this. It is not something that is done, but
For example, the present invention can be applied to other circuits of communication modulation/demodulation equipment and similar differential amplifier circuits included in various devices. The present invention
The present invention can be widely used in differential amplifier circuits having at least differential transistors as a basic configuration and semiconductor integrated circuit devices including such differential amplifier circuits.

5 [Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below. That is, a differential amplifier circuit included in an A/D conversion circuit or the like of a communication modulation/demodulation device is configured with a pair of differential bipolar transistors receiving complementary input signals and a current mirror configuration provided on the collector side of the differential bipolar transistors. By configuring the active load as a basic structure consisting of a pair of MOSFETs, the flicker noise of the differential amplifier circuit can be suppressed and the offset voltage can be reduced without increasing the required layout area and limiting high-speed operation. It can be suppressed.

As a result, the A/D conversion circuit including the differential amplifier circuit and the communication modulation/demodulation device can be lowered in cost and operated faster and more stably, while increasing the S/N ratio thereof.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a differential amplifier circuit to which the present invention is applied. FIG. 2 is a circuit diagram showing an example of a conventional CMO3 type O3 amplifier circuit. FIG. 1 is a circuit diagram showing an example of a conventional bipolar differential amplifier circuit. Tl~T2. T5~T7...-NPN type bipolar transistor, T3~T4...PNP type bipolar transistor, Q1~Q4...P channel MOSFE
T, Ql 1~Q14...N channel MOSFET
, R1...resistance.

Claims (1)

[Claims] 1. A pair of differential bipolar transistors receiving complementary input signals, and a pair of MOSFEs provided on the collector side of the differential bipolar transistors and configured as a current mirror.
A differential amplifier circuit characterized by comprising an active load consisting of T. 2. The differential amplifier circuit is included in an A/D conversion circuit of a communication modem device, and the differential bipolar transistor and MOSFET are respectively an NPN bipolar transistor and a P channel MOSFET.
2. The differential amplifier circuit according to claim 1, wherein the differential amplifier circuit comprises an ET.