JPH03116971A - Mask programmable rom - Google Patents

Abstract

PURPOSE:To enable a glass mask to be decreased in manufacturing cost and shortened in turnaround time by a method wherein binary data to be set on an unused region are made correspondent to data not patterned on the glass mask out of the data programmed on the glass mask if there is the unused region in a memory cell. CONSTITUTION:A mask programmable ROM is composed of MOS transistors Tr1 and Tr2, a NAND gate NA1, an inverter IN, and NOR gates NOR1 and NOR2. When an E-type transistor forming a memory cell is made correspondent to '0', the transistor Tr1 is made to be of a D type, and when the E-type transistor forming a memory cell is made correspondent to '1', the transistor Tr2 is made to be of a D type. As mentioned above, it is determined that data outputted from a sense amplifier are transmitted to an output circuit as they are or inverted. Therefore, data on a glass mask correspondent to the unused region of a memory cell become unneeded. By this setup, a glass mask can be decreased in manufacturing cost and shortened in turnaround time.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) The present invention is a NAND-type mask program ROM (Read Only Me) using a MOS transistor as a memory cell.
mory).

(Prior Art) A mask program ROM is one in which information is written using a mask during the wafer manufacturing process, and is classified into a NOR type and a NAND type depending on the circuit configuration of the memory cell array. The Noah type described above is suitable for high-speed operation, but has the disadvantage that the chip size becomes large. on the other hand,
The NAND type has the advantage of requiring a relatively small chip size, and as the memory capacity increases to the megabit level, the need to reduce the chip size increases due to yield and cost considerations, so the NAND type is often used. Become.

For part of the memory cell array of this type of conventional NAND-type ROM, the planar pattern and circuit on the chip are
Shown in Figures (a) and (b). Figures 3(a) and (b)
), one bit line BL is provided in common between two transistor columns, and one bit line BL is provided as a transistor for selecting the NAND bundle (transistors T1 to T) of each transistor column.
enhancement-type (E-type) transistors T and 1
depletion type (D type) transistors T′
are connected in series, and two selection word lines W are connected to each NAND bundle.
L and WL' are connected. This S
In the case of S, the selection transistors of each NAND bundle in the transistor rows on both sides of the bit line BL are provided so that the corresponding transistor types (E type and D type) are different from each other. Therefore, when selecting a certain memory cell and reading its data, the word line WL' corresponding to the D-type transistor T' of the two NAND selection transistors in the NAND bundle to which this memory cell belongs is connected to the ground potential, S
The word line WL8 corresponding to the SE type transistor T is set to a power supply potential V (for example, 5V), and the word line WL . C. Set the word line WL of the gate electrode of the selected memory cell transistor to the ground potential. Then, data corresponding to the on or off state of the selected cell transistor (for example, T1) of the selected NAND bundle appears on the bit line BL.

The memory cell transistor stores stored information as “0” or “
Since they are made of D-type or E-type transistors corresponding to 1°, all unselected cell transistors to which the power supply potential V is applied to their gates are turned on, but when the ground potential is applied to their gates, If the selected cell transistor is E type, it is turned off, and if it is D type, it is turned on. Data is read out in this on/off state.

For the NAND bundle of the adjacent transistor row corresponding to the selected NAND bundle, the E-type transistor of the two NAND selection transistor rows is turned off, so data is read from this NAND bundle to the bit line BL. It won't happen.

In the pattern shown in FIG. 3(a), 32 is a contact portion between the bit gBL and one end of the NAND bundle transistor array, and the shaded area represents the gate and channel region of the D-type transistor T'.

In the configurations shown in FIGS. 3(a) and 3(b) above, one bit line is provided for two transistor columns, so the number of bit lines is reduced and the chip size in the bit line wiring width direction is reduced. to shrink. For this reason, the number is now widespread.

When manufacturing such a mask program ROM,
First, all memory cells are made into E type. Then, the coordinate values of the location on the chip of the transistor to be made into a D type are input into an electronic computer for conversion processing. Thereafter, based on the converted data, ion implantation information for the transistor to be made into a D type is written on the glass mask. This glass mask is then used to selectively create D-type transistors and write binary data.

(Problems to be Solved by the Invention) For this reason, as the storage capacity increases, the coordinate value data on the D-type transistor chip that is input to the computer also increases, which increases the processing time of the computer and increases the The cost of use has also increased, and the cost of using a computer has come to account for a large proportion of the total cost for making one glass mask. Therefore, as memory capacity increases, not only does the manufacturing cost of the glass mask borne by the user increase, but also the processing time of the computer increases, which reduces the time it takes from the user placing an order to receiving the mask ROM. It's going to be long.

On the other hand, in mask ROMs, although data may be written to all of the memory capacity, there are also cases where there is unused memory area where no data is written, and as the memory capacity increases, unused memory The area tends to increase. For example, in a 16 Mbit mask ROM, a 15 Mbit area is used and the IM bit is left unused.

The data of memory cells in such an unused area are set to all 1'' or all 0m, but the data is set to ``1#''.
It was up to the user to decide whether to set it to "0" or "0". Therefore, depending on the user, it is necessary to make all unused areas into D-type transistors, and in this case, the manufacturing cost of the glass mask and the manufacturing time are the greatest.

In addition, mask ROM manufacturers inspect not only the used area but also the unused area during product inspection, and check whether the data in this unused area is all "1 degree" or "0", and However, if there was incorrect data, it would be discarded as a defective product.For this reason, even though it was an unused area,
This was one of the causes of decreased product yield.

The present invention has been made in consideration of the above circumstances, and is a mask that can reduce the manufacturing cost of glass masks and shorten the turnaround time (the time from specifying program data to product delivery). The purpose is to provide a program ROM. Another object of the present invention is to improve the yield of products and provide an inexpensive mask program ROM.

[Structure of the invention]

(Means for Solving the Problems) A first invention provides a mask program ROM having memory cells that stores binary data at the manufacturing stage based on data programmed by patterning a glass mask. If there is an unused area, a means is provided for making the unpatterned data of the glass mask correspond to the binary data '0' or '1' set in the unused area, among the data programmed in the glass mask. It is characterized by

A second aspect of the present invention is a mask program ROM having a plurality of sets of a plurality of memory cells connected in series, in which a selection means selects the plurality of memory cells connected in series, in which one of the plurality of sets of memory cells is selected. The present invention is characterized in that the data of the plurality of memory cells of the width of a set are all the same, and the selection operation by the selection means is not performed for a set that becomes non-conductive when selected.

(Function) The mask program R of the ml invention configured as described above
According to OM, when a memory cell has an unused area, binary data set in the unused area is made to correspond to unpatterned data on the glass mask among the data programmed in the glass mask. This eliminates the need for data on the glass mask corresponding to unused areas, shortens computer processing time, reduces manufacturing cost of the glass mask, and shortens turnaround time.

Further, according to the mask program ROM of the second invention configured as described above, the memory cell becomes non-conductive when selected, and for a group in which the data of a plurality of memory cells are all the same, the selection means The selection operation is not performed. As a result, the yield of the product can be improved and the product cost can be reduced.

(Example) Mask program R according to the first invention with reference to FIG.
An example of OM will be described.

The mask program ROM of this embodiment differs from the conventional mask program ROM in that binary data '0° or This corresponds to “1”. In other words, if all memory cells composed of E-type transistors in the unused area are set to "0°" according to the user's request,
"0" corresponds to the E-type transistors that make up the memory cell.On the other hand, if all the memory cells that are made up of E-type transistors in the unused area are set to "1m" according to the user's request, the memory To make the E-type transistor that makes up the cell correspond to '1'. Then, in order to make the E-type transistor that makes up the memory cell correspond to '1' or '0', for example, as shown in FIG. This can be done by providing a circuit between the sense amplifier and the output circuit.The circuit shown in Figure 1 is a MOS).
It consists of a transistor Trl' Tr2, a Nant gate NAI, an inverter IN, and a NOR gate N0R1°N0R2.
To make the transistor Trl correspond to 0", make the transistor Trl a D type; to make the E type transistor that constitutes the mesori cell correspond to a 1, make the transistor Tr2 a D type. By doing this, the data from the sense amplifier It is determined whether the data is transmitted to the output circuit as is or is inverted and transmitted.Therefore, the data read by the sense amplifier in the E-type transistor constituting the memory cell is always '1'. However, if the transistor Tr1 in the circuit shown in FIG. 1 is of the D type and the transistor "r2 is of the E type, the potential level of the intermediate node N1 between the transistors "rl and Tr2 will be "1°." Gate NAI, inverter IN, NOR gate N0R2
After that, it becomes a "0" level and is transmitted to the output circuit.

Note that the transistor Trl is of E type, and the transistor Tr2 is of E type.
If it is made into a D type, if the data of the E type transistor read by the sense amplifier is "1", 1m will be transmitted to the output circuit.

In this way, even if the data of the memory cells detected by the sense amplifier is the same, the transistor Tr of the circuit shown in FIG.
By simply programming either Tr1 or Tr2 to be D'42, it is possible to invert the binary data corresponding to the E-type and D-type transistors that make up the memory cell, or leave them as they are. Become. As a result, in the mask program ROM of this embodiment, the data on the glass mask corresponding to the unused area is unnecessary, so the processing time of the computer is shortened, and the manufacturing cost of the glass mask can be reduced. At the same time, turnaround time can be shortened.

Next, an embodiment of the mask program ROM according to the second invention will be described with reference to FIG.

In general, in a mask program ROM, since all memory cells in unused areas have the same data, it is not necessary to select them using the word line WL and read out the data. If memory cell transistors Tl-Tn are all E-type, there is no current path through T1-T. Therefore, the state is equivalent to not selecting S by the selected word lines WL and WL'. Therefore, in this embodiment, the selected word line WL is in an unused area.

Transistors T, TS connected to WL'
S
S is all E type, transistor T,
T' is prevented from performing a selection operation based on S S . Therefore,
Even if one of the memory cell transistors Tt to Tn is defective and a current path exists in the transistors T1 to Tn due to leakage current with the substrate, the selection transistor T.

Since T' is turned off, it is not defective.

As described above, according to this embodiment, it is possible to improve the yield of the product and to reduce the product cost.

Note that in the above embodiment, the selection transistor T is used.

Although T' is made of E type so as not to perform the selection operation, the contact 32 may be omitted, for example.

However, if the transistors T and T' are changed to E type, S
Since writing data into the memory cell can be done using the same glass mask, it is most efficient to change the transistors T and T' to E-type by increasing or decreasing the unused area.

Furthermore, in addition to applying the second invention to an unused area, the transistor T,
-T, are all E-type, the yield can be further improved by applying the second invention.

〔Effect of the invention〕

According to the first invention, data on the glass mask corresponding to unused areas is not required, so the processing time of the electronic λ1 calculator is shortened, and the manufacturing cost of the glass mask can be reduced. Around time can be shortened.

Moreover, according to the second invention, the yield of the product can be improved and the product cost can be reduced.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram explaining the operation of one embodiment of the mask program ROM according to the first invention, and FIGS. 2(a) and (
b) is a plane pattern on a chip and a circuit diagram related to a memory cell array, illustrating an embodiment of a mask program ROM according to the second invention; FIGS. 3(a) and (b);
1 is a planar pattern on a chip and a circuit diagram of a memory cell array of a conventional NAND-type ROM.

Claims (1)

[Claims] 1. In a mask program ROM having memory cells that store binary data at the manufacturing stage based on data programmed by patterning a glass mask, if the memory cells have an unused area. , characterized by comprising means for making binary data "0" or "1" set in the unused area among the data programmed in the glass mask correspond to unpatterned data of the glass mask. Mask program RO
M. 2. It has multiple sets of multiple memory cells connected in series,
In the mask program ROM in which a plurality of memory cells connected in series are selected by a selection means, data of the plurality of memory cells having a width of one set among the plurality of sets of memory cells are all the same, and the selected memory cells are selected. 2. A mask program ROM, characterized in that said selection means does not perform a selection operation for a group which becomes non-conductive when