JPH03116344A - Extended memory identifying system - Google Patents

Abstract

PURPOSE:To automatically identify the classification of an extended memory set to a connector by providing an identifying means which identifies the extended memory based on coincidence or disaccord between write data and read data. CONSTITUTION:A CPU 11 accesses address 200000 of an extended memory 30 set to, for example, a connector C1 to write prescribed data there in cooperation with a memory controller 18. Thereafter, data is read out from its start address 100000; and in the case of uncoincidence between read data and write data to address 200000, it is recognized that the 4M-byte extended memory is set to the connector C1. In the case of coincidence, it is recognized that the 2M-byte extended memory is set to the connector C1. Thus, the classification of the extended memory set to the connector is automatically discriminated, and the extended memory can be set to an arbitrary connector independently of its storage capacity.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention is directed to an identification method (conventional Technology) In recent years, various laptop-type personal computers have been developed that are easy to carry and can be operated by internal batteries.

In order to improve data processing functions, this type of personal computer is configured so that not only internal memory but also expansion memory can be added as needed. As the expansion memory, for example, a 2 Mbyte memory board or a 4 Mbyte memory board is often used. When such an expanded memory is used, for example, 1 MB of internal memory can be used as 3 MB or 5 MB of memory.

Therefore, by using the expansion memory, the user can expand the storage capacity of the internal memory to a desired capacity depending on the purpose of using the personal computer.

However, in conventional personal computers, the relationship between the storage capacity of the expansion memory and the expansion memory connector for installing the expansion memory is fixed under certain conditions in order to facilitate address assignment to the expansion memory. It is determined that That is, conventionally, 2M
There were separate connectors for the byte expansion memory and 4M byte expansion memory, and memory boards could only be attached to the corresponding connectors.

For this reason, when expanding expansion memory, the user must identify each connector type before installing the memory board, creating a problem in which the user's work to expand the memory becomes complicated. .

Furthermore, since the storage capacity of the expansion memory that can be attached is determined for each connector, the memory can only be expanded within a very limited range, and there is a drawback that the degree of freedom in expanding the memory capacity is low.

(Problems to be Solved by the Invention) As mentioned above, in the past, the storage capacity of the expansion memory that can be installed is determined for each connector, which complicates the user's work to expand the memory and makes it difficult to expand the memory capacity. The drawback was that the degree of freedom was low.

This invention was made in view of these points, and in order to enable the expansion memory to be installed in any connector regardless of its storage capacity, it automatically identifies the type of expansion memory installed in the connector. The purpose of this invention is to provide an extended memory identification method that can

[Configuration of the Invention (Means and Effects for Solving Imposition) The extended memory identification system according to the present invention has a first storage capacity and an address space is divided into blocks by a plurality of control signals. an expanded memory; and a second memory having a second memory capacity larger than the first memory capacity, and in which the address space is divided into blocks according to a predetermined control signal among the plurality of control signals.
expansion memory mounting means for selectively mounting the expansion memory; and identification information holding means for holding identification information for identifying whether or not activation of the control signal is permitted for each of the control signals. and information setting means for setting identification information corresponding to the second expansion memory in the identification information holding means so that activation of a control signal corresponding to the second expansion memory is only permitted; control means for controlling energization of the control signal based on the identification information when accessing the expansion memory installed in the expansion memory loading means; a first access means for performing a write access to the extended memory mounted on the extended memory mounting means at a predetermined first address in the first extended memory; a second access means for executing a read access to the extended memory mounted on the extended memory mounting means at a 27th address corresponding to the control signal corresponding to the first address; and determine whether the expansion memory installed in the expansion memory installation means is one of the first and second expansion memories, based on whether the data read by the second access means are the same. It is characterized by comprising an identification means for identifying.

In this identification method, only the control signals permitted by the identification information are activated, so that the predetermined first address in the first extended memory corresponding to the control signal whose activation is not permitted by the identification information is activated. When a write access is executed, when the first extended memory is mounted on the mounting means, data is written to the second address instead of the first address in the first extended memory. on the other hand,
Since all the control signals corresponding to the second expansion memory are enabled, when the second expansion memory is attached to the attachment means, data is written to the first address in the second expansion memory. . Therefore, if the data written by the first access means and the data read from the second address match, it can be recognized that the first expansion memory is installed, and if they do not match, the second expansion memory You can recognize that it is attached. Therefore, regardless of whether the first or second expansion memory is attached to the attachment means, the type of expansion memory can be identified, making it possible to realize memory expansion with a high degree of freedom.

(Example) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a system configuration in an embodiment of the present invention.

In FIG. 1, numeral 11 is a main CPU that controls the entire system, and here it is realized by a 32-bit CPU chip. 12. 13 is an internal bus connected to the CPU 11, of which 12 is a 16-bit wide internal data bus, and 13 is a 24-bit wide internal address bus. 14 is an optional numerical arithmetic processor (Nun+erlcalData Processor) selectively connected to the internal data bus 12 via a connector.
). 15 is a 16-bit wide data bus 15D;
This system bus is composed of a 20-bit wide lower address bus 15L and a 7-bit wide upper address bus 15U. 16 is a bus driver (BUS-DRV) that provides a connection interface between the internal buses 12 and 13 and the system bus 15; 17 is a bus controller (BUS-CNT) that controls the system bus 15;
Reference numeral 18 denotes a memory controller (MEM-CNT) that controls address transfer between the address buses 13-15 (U, L), controls read/write of the main memory 19, and controls read/write of the extended memory 30. , the configuration of the memory controller 18 will be described later with reference to FIGS. 7 and 8. 19 is a main memory (1-R
AM). 20 is a BI08-ROM that stores BiO2 (basic turnout program). 21 decodes the I10 address on the system bus 15 and passes it to the corresponding I10 element (chip).
lo-DEC), 22 is an I10 controller (l1O-CNT) that controls input/output of I10 data, and 23 is a super integration IC (SlO-CNT) that houses various I10 controllers such as a floppy disk interface, hard disk interface, DMA controller, and interrupt controller. ), 24 is a frequency oscillator (VFO) that generates a clock for the floppy disk drive (FDD), 25 is a floppy disk drive interface (FDD-1/F), 2B is a hard disk drive interface (HDD-I/F)
, 27 is a keyboard controller (KBC), 28 is a keyboard scan controller (SCC), 29 is a backup RAM (B-RAM) provided for the resume function, etc., and 30 is an optional expansion memory board connector C1 as required. , C2, and C3 (see Figure 4).The configuration of this expansion memory board 30 is as shown in Figures 2 and 3.
This will be described later with reference to the drawings. 31 has its own operating battery and memory (CMOS-RAM) backed up by the same battery.
) with a clock module (RTC; Real-Tl
se C1ock), 32 is an input/output board (PRT/FD) to which input/output devices such as external floppy disk drives (FDD) and printers (PRT) are connected.
D-IF), 33 is a serial human output interface (SIO) to which an R8-2320 interface device or the like is connected. 34 is a power control CPU (PC-CPU) that supplies and controls power for operating the device.
It is an intelligent power supply (PS) equipped with two main battery batteries (BT-L,
BT-R) can be connected, and the power control CP
It controls each operating power supply under the control of the U (PC-CPU), and the status of each power supply is notified to the CPU II via the I10 controller 22.

35 is a display controller (DIS P-CNT) which is a display system in the device, and here, it is a display controller (hereinafter referred to as FDP), a liquid crystal display (hereinafter referred to as LCD), and a color panel (hereinafter referred to as FDP). so-called flat panel displays such as color LCDs,
Each drive target is a CRT display (hereinafter referred to as CRT). A floppy disk drive (FDD) 41 is connected to the floppy disk drive interface 25 and is installed in the device.
, 42 is a hard disk drive (HDD) connected to the hard disk controller 26, 43 is a keyboard unit (KB) connected to the keyboard scan controller 28, and 44 is a numeric keypad (HDD) connected to the hard disk controller 26.
y), 45 to 47 are display devices connected to the display controller 35, and among these,
45 is a backlit LCD, 46 is a PDP, 47
is a CRT. cio is a flat panel display connecting connector, C1l is a connector of the LCD 45 coupled to the flat panel display connecting connector C10,
C12 is the same <: PDP4B connector.

FIG. 2 shows the configuration of a 4 Mbyte extended memory board used as the extended memory 3o shown in FIG. 1.

As shown in Figure 2 (A), this 4MB expanded memory includes eight dynamic RAMs (DRAs).
M) is used, and each of these dynamic RAMs has a 1MX4 bit configuration.

For example, if address allocation to this extended memory starts from the 1M byte, as shown in the figure,
First and second dynamic RAM (DRAMI
, 2) from address 100000 to address IFF
Similarly, the third and fourth dynamic RAMs (DRAM3.4) are assigned addresses 200000 to 2r'PFPr', and the fifth and sixth dynamic RAMs (DRAM5.8) are assigned addresses 2r'PFPr' and The address apppppp is from aooooo,
seventh and eighth dynamic RAMs (DRAM7.
8) Address 400000 to address 4PPP
PP is assigned.

As mentioned above, since the data bus 12 connected to the connectors 01 to C3 has a 16-bit configuration, access to the extended memory is executed in units of 16 bits. That is, the first to fourth dynamic RAMs (DRAM1
~4) constitute the first access block, and the fifth
The second access block is composed of the eight dynamic RAMs (DRAMs 5 to 8).

In this way, this 4M byte extended memory is divided into two access blocks, so the dynamic RAM
The row address strobe signal (RA
Two control signals, RASO and RASI, are used as S). The control signal RASO is at address 10000
The control signal RASI is activated when any address from 0 to 2PPPPP is accessed, and the control signal RASI is activated when any address from address aooooo to 4FFPFF is accessed.

In other words, the address space of this 4M byte extended memory is divided into blocks by two control signals, RASO and RASI, and when the control signal RASO is activated,
Any address from address 1ooooo to 2FPFFF is selected and designated by the memory address signal (MAO-9) supplied from the memory controller 18. On the other hand, when the control signal RASI is activated,
Any address from address aoooooo to 4FPFFF is selected and specified by the memory address signal (MAO-9) supplied from the memory controller 18.

In this way, the address space from addresses 100000 to 2FPPP and the address space from addresses aooooo to 4PFFFF are defined by the same repeated address, and the memory address signal supplied from the memory controller 18 is
PPP address space and addresses 300000 to 4
Which of the FFFFF address spaces is designated is determined by which of the control signals RASO and RASI is activated.

FIG. 2(B) is a block diagram schematically showing the 4 Mbyte extended memory shown in FIG. 2(A).

FIG. 3 shows the configuration of a 2 Mbyte expansion memory board used as the expansion memory 30 shown in FIG.

As shown in Figure 3(A), this 2M byte expanded memory includes 16 dynamic RAMs (DR
AM1-1G) are used, and each of these dynamic RAMs has a 256K×4 bit configuration.

Access to this 2M byte extended memory is also executed in units of 16 bits. That is, the first to fourth dynamic RAMs (DRAMs 1 to 4) constitute a first access block, the fifth to eighth dynamic RAMs (DRAMs 5 to 8) constitute a second access block, and the ninth to fourth dynamic RAMs (DRAMs 5 to 8) constitute a second access block. 12 dynamic RAMs
(DRAMs 9 to 12) constitute a third access block, and the 13th to 16th dynamic RAMs (DRAMs 9 to 12) constitute a third access block.
DRAMs 13 to 18) constitute a fourth access block.

In this way, this 2MB expanded memory is divided into four access blocks, so dynamic RAM
The row address strobe signal (RA
S) is RASO.

Four control signals are used: RASI, RAS2, and RAS3.

2M byte address space of this extended memory 10000
0 to 2PFPPP are control signals RASO, RASIRA
S2. and is divided into four by RAS3.

In the address space of this 2M byte extended memory, there is an address space corresponding to addresses 100000 to l FFPPP and addresses 200000 to 2FFPFF.
address spaces corresponding to each are defined by the same repeating address, and a control signal RASO.

RASI is activated, an address in the address space from address 100000 to 2PFPPP is specified by the memory address signal supplied from the memory controller 18, and the control signal RAS2. R.A.
When either S3 is activated, a memory address signal supplied from the memory controller 18 specifies an address in the address space from address 200000 to 2PFPPP.

FIG. 3(B) is a block diagram schematically showing the 2 Mbyte extended memory shown in FIG. 3(A).

FIG. 4 shows the expansion memory connector C1 shown in FIG.
An example is shown. As shown in the figure, the connector C1 has a 4M byte expansion memory supplied from the memory controller 18 so that either the 4M byte expansion memory shown in FIG. 2 or the 2M byte expansion memory shown in FIG. A slot is provided for receiving two control signals RASO-RAS4. The connectors C2 and C3 also have the same configuration as the connector CI, and each of the connectors C2 and C3 is provided with slots for receiving four control signals RASO to RAS4.

5 and 6 show a chip type register CTR and an existence register E provided in the memory controller 18 to identify the type of expansion memory attached to the connectors 01 to C3.
The configuration of R is shown respectively.

The chip type register CTR shown in FIG.
The memory chip that makes up the expansion memory installed in the connector is 1MX4 bit configuration or 256
This is used to identify whether the control signal is a KX4 bit configuration in units of control signals RASO to RAS3, and holds 1° in the case of a 1MX4 bit configuration, and holds '0'' in the case of a 256KX4 bit configuration.

This chip type register CTR consists of a 4-bit register section CTRI corresponding to connector CI, a 4-bit register section CTR2 corresponding to connector C2, and a 4-bit register section CTR3 corresponding to connector C3.
Although it has a 2-bit configuration, it actually consists of two 8-bit type registers. In this case, the register has a total of 16 bits, of which 4 bits are not used.

For example, if the 4M byte expansion memory shown in Figure 2 is attached to connector C1, the 4M byte expansion memory will be used as a dynamic RA with an IM x 4 bit configuration as described above.
As shown in the figure, in the register CTRI, the bits corresponding to RASO and RASI of the register CTRI are set to 1#, and the bits corresponding to RAS2 and RAS3 are set to 0#, respectively. Ru.

Ibistance ER shown in FIG.
It is used to identify each unit of SO to RAS3, and holds '1' if an extended memory is installed, and holds '0' if it is not installed.

This resistance register ER includes a 4-bit register section ERI corresponding to the connector CI, a 4-bit register section ER2 corresponding to the connector C2, and a 4-bit register section ER2 corresponding to the connector C3.
Although it has a 12-bit configuration consisting of a 4-bit register section ER3 corresponding to , it actually consists of two 8-bit type registers. In this case, the register has a total of 16 bits, of which 4 bits are not used.

For example, when the 4 MB expansion memory shown in Figure 2 is installed in the connector CI, two control signals, RASO and RASI, are used for the 4 MB expansion memory as described above, and RAS2 and RAS3 are Since it is not used,
As shown in the figure, '1' is set in the bits corresponding to RASO and RASI of register ERI, and RAS2
'0' is set in each bit corresponding to ゜RAS3.

FIG. 7 shows an example of the configuration of the memory controller 18. In Figure 7, 101 is the main CPU
This is a decoder that decodes the upper 4 bits A20-23 of address signals AO-23 supplied from I. 102
103 is the aforementioned chip type register CT RL02, and 103 is the aforementioned eviction register ER. Reference numeral 104 denotes an effective address calculation circuit that calculates the effective address range of the expansion memory connected to each connector based on the contents of the chip type register CTR and the eviction register ER.

This effective address calculation circuit 104 is, for example, a connector C.
1 is equipped with a 4M byte expansion memory, the contents ro011J of the register section CTRL of the chip type register CTR and the contents r0011J of the register section ERI of the event register ER explained in FIGS. 5 and 6. Based on this, for example, a 4M byte address space from address 100000 to 4PFFFF is calculated as a valid address. This calculation of the effective address is actually executed in units of each control signal of RASO to RAS3, that is, in units of each bit of the chip type register section CTRI and the exhaustion register section ERI. In other words,
When a 4M byte expansion memory is installed in connector C1, the control signal RASO is set to address to.
The first 2M bytes of 2PPPP from oooo are valid, and for the control signal RAS1, the address is 20000.
The valid address calculation circuit 104 calculates that the remaining 2M bytes from 0 to 4PFPPF are valid.

105 is a control circuit that controls the supply of control signals RASO to RAS3 to each connector to which the expansion memory 30 is attached, and based on the decoding result of the decoder 101 and the calculation result of the effective address calculation circuit 104,
A necessary control signal is generated among O to RAS3. 10
B and 107 are the lower 20 bits AO~20 to 1 of the address signal AO~23 supplied from the main CPU II.
A row address buffer and a column address buffer that receive a 0-bit row address and a 10-bit column address, respectively. 108 is a selector that alternately selects a row address and a column address, and the selected address is 10 for each connector to which the expansion memory 30 is installed.
It is supplied as a bit memory address MAO-9.

FIG. 8 shows a decoder 101 and a chip type register CTR 102 provided in the memory controller 18.
, existence register E R103, effective address calculation circuit 104. An example of a specific configuration corresponding to one connector C1 in the control circuit 105 is shown.

In FIG. 8, 201 to 204 are decoders corresponding to the connector CI of the decoder 101, and when each of these decoders 201 to 204 receives a predetermined address,
A "1" level signal is supplied to the corresponding AND gate.

Effective address calculation circuits 301 to 304 correspond to the connectors CI of the effective address calculation circuit 104, and calculate effective addresses based on corresponding bit data of the chip type register section CTRI and the existence register section ERI, respectively. 401a to 404as and 401b to 404b are AND games) Gl-
These are an upper limit comparator and a lower limit comparator that together with 04 constitute a part corresponding to the connector C1 of the control circuit 105. The upper limit comparators 401a to 404a compare the upper limits of the effective address range calculated by the corresponding effective address calculation circuits with the addresses A2G to 23, and determine whether the addresses specified by the addresses A20 to 23 are the upper limits of the effective address range. When less than, the corresponding AND
Supply a “1 rubel signal to the gate. Lower limit comparator 40
1b to 404b compare the lower limit of the effective address range calculated by the corresponding effective address calculation circuit with the addresses A20 to 23, and calculate the addresses A20 to 23.
When the address specified by is larger than the lower limit of the effective address range, a "1" level signal is supplied to the corresponding AND gate.

Next, with reference to the flowchart of FIG. 9, the processing procedure of the extended memory identification method, which is a feature of the present invention, will be explained.

Since the extended memory is identified using the same procedure for each connector, the extended memory identification method will be explained here using the connector CI as an example.

First, the CPU 1l selects the chip type register section C regardless of the type of expansion memory installed in the connector C1.
Identification information corresponding to the extended memory with the larger storage capacity, that is, the 4 MB type extended memory, is initially set in the TRL (Step-AI). In this case, the chip type register CTR1 has "1" in the bit corresponding to the control signals RASO and RASI, as shown in FIG.
Control signal RAS2, the bit corresponding to RASO is “0”
” are forcibly set.

Next, the CPU 11 registers the existence register section ER.
I set the expanded memory with larger storage capacity, i.e. 4M
Identification information corresponding to the byte type extended memory is initialized (step A2). In this case, as shown in FIG. 6, the control signal RASO is input to the immunity register section ERI.

“1” in the bit corresponding to RASI indicates control signal RAS
2. The bits corresponding to RAS3 are forcibly set to 0, which causes the two RAS signals (RAS
O, RASI) are enabled and their activation is permitted.

Next, the CPU 11, in collaboration with the memory controller 18, writes access to the first address, for example, address 100000, of the expanded memory attached to the connector CI, writes predetermined data, and then reads the data from the first address. Then, the CPU 11 compares the written data with the actually read data (step A3).
).

If extended memory is connected to connector CI,
Regardless of whether the extended memory is a 4 Mbyte or 2 Mbyte extended memory, data can be written to the first address, so the written data matches the data actually read from the first address.

Therefore, if the written data and the actually read data match, it is recognized that the extended memory is connected to the connector C1, and the steps A5 to A5 for identifying the storage capacity of the extended memory are then performed. The process of A8 is performed. On the other hand, if no expansion memory is connected to the connector CI, data cannot be written to the first address, so the data read from the first address does not match the written data. Therefore, if the written data and the actually read data do not match, it is recognized that the extended memory is not connected to the connector CI, so all bits of the evisistance register ERI are set to "0". After that (step A4), the identification process ends.

If the data written to the first address matches the data actually read, first, the CPU II, in collaboration with the memory controller 18, sets the extended memory attached to the connector CI to address 200000, that is, to the valid state. If the control signal RAS2 or RAS3 is not set, write access is made to any address in the address space (addresses 200000 to 2FPFFF) of the 2M byte extended memory corresponding to the control signal RAS2 or RAS3, and predetermined data is written (step A5).

In this case, when the expansion memory installed in the connector C1 is a 4M byte expansion memory, the control signals RASO and R set to the valid state by the chip type register section CTRI and the existence register section ERI are
Since address 200000 is a valid address according to ASI, data can be normally written to address 200000. On the other hand, if the expansion memory attached to connector C1 is a 2M byte expansion memory, the control signal R corresponding to address 200000
Since AS2 is not set to the valid state and the control signals RASO and RASI are set to the valid state, data cannot be written to address 200000 of the 2M byte extended memory, and the 2M byte extended memory is Data is written to the first address of , that is, address 100000. As mentioned above, in a 2M byte expanded memory, this is from address 100000 to I F
The address space up to FFFF and the address space from address 200000 to 2FPPP are defined by the same repeating address, and
This is because the address space to which the address 100000 corresponding to 00000 belongs is forcibly set to a valid state by the control signal RASO.

Next, the CPU 11 cooperates with the memory controller 18 to access the first address of the extended memory mounted on the connector C1, that is, address 100000, and read out the data (Step A6), and then read data from that first address. The data is compared with the write data for address 200000 (step A7).

If a 4M byte expansion memory is connected to connector C1, data can be written to address 200000, so the data read from the first address and address 20
It does not match the write data for 0000. Therefore, the data read from the first address and address 20
If the write data for 0000 does not match, it can be recognized that a 4M byte expansion memory is installed in connector C1, so leave the settings of the chip type register section CTRI and existence register ERI as they are. End the identification process.

On the other hand, if a 2M byte expansion memory is attached to the connector CI, data is written to the first address instead of address 200000, so the data read from the first address and the data written to address 200000 match. Therefore, if the data read from the first address and the data written to address 200000 match, it can be recognized that a 2M byte expansion memory is installed in the connector C1, so the chip type register section CTRL and the existence register section After changing the contents of the ERI to identification information corresponding to the 2M byte extended memory (step A8), the identification process is ended.

As explained above, in this embodiment, regardless of whether a 2M byte expansion memory or a 4M byte expansion memory is installed in each connector 01 to C3, whether the installed expansion memory is of the 2M type or not, You can identify whether it is a 4M type. Therefore, one connector has two
It is possible to install either an MB expansion memory or a 4 MB expansion memory. Therefore, it is no longer necessary for the user to identify the connector type, which was conventionally necessary, before installing the memory board, and it becomes possible to easily expand the memory. Furthermore, since the storage capacity of the expandable memory that can be attached is not determined for each connector, the memory capacity can be expanded more freely.

[Effects of the Invention] As described above, according to the present invention, it becomes possible to automatically identify the type of extended memory attached to a connector, and the extended memory can be connected to any connector regardless of its storage capacity. It is possible to create a system that can be worn.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the overall configuration of a system according to an embodiment of the present invention, FIGS. 2 and 3 are diagrams each showing an extended memory added to this system, and FIG. 4 is a block diagram showing the extended memory added to this system. Figures 5 and 6 are diagrams showing a connector to be installed in this system, Figures 5 and 6 are diagrams respectively showing a chip type register and an impedance register provided in this system, and Figure 7 is a diagram showing a memory installed in this system. FIG. 8 is a block diagram showing the configuration of the controller; FIG. 8 is a block diagram showing the specific configuration of a portion of the memory controller shown in FIG. 7; FIG. 9 is a flowchart explaining the operation of extended memory identification processing in this system. be. DESCRIPTION OF SYMBOLS 11... Main CPU, 18... Memory controller, 30... Expansion memory, Cl-C5... Connector for expansion memory, 102... Chip type register (C
TR), 103... Ibidistance register (ER)
.

Claims (1)

[Scope of Claims] A first expanded memory having a first storage capacity and having an address space divided into blocks according to a plurality of control signals, and a second storage capacity larger than the first storage capacity. an expansion memory installation means for selectively installing a second expansion memory whose address space is divided into blocks according to a predetermined control signal among the plurality of control signals; identification information holding means for holding identification information for each of the control signals to identify whether or not the second expansion memory is activated; information setting means for setting identification information corresponding to the second extended memory in the holding means; and activating the control signal based on the identification information when accessing the extended memory mounted on the extended memory mounting means. a control means for controlling the extended memory mounted in the extended memory mounting means at a predetermined first address in the first extended memory corresponding to a control signal whose energization is not permitted according to the identification information; a first access means for performing a write access with a second address; and a first access means for performing a write access with a second address corresponding to a control signal whose activation is permitted by the identification information and corresponding to the first address. a second access means that performs a read access to the extended memory that has been accessed; and whether the write data written by the first access means and the data read by the second access means are the same. based on the above, the expansion memory installed in the expansion memory installation means
1. An extended memory identification method, comprising: identification means for identifying which of the extended memories.