JPH03116343A - Extended memory control system - Google Patents

Abstract

PURPOSE:To set an extended memory to an arbitrary connector independently of its storage capacity by providing a discrimination information holding means for each extended memory setting means. CONSTITUTION:A memory controller 18 is provided with a chip type register and an existence register for the purpose of discriminating classifications of extended memories 30 set to connectors C1 to C3. Extended memories 30 set to connectors C1 to C3 are addressed in accordance with contents of the chip type register and the existence register where discrimination information corresponding to each of connectors C1 to C3 are held, and energization of a control signal can be controlled whether set extended memories 30 have 2M bytes or 4M bytes. Thus, the extended memory is set to an arbitrary connector independently of its storage capacity.

Description

Detailed Description of the Invention [Objective of the Invention] (Industrial Application Field) The present invention provides a control method for an extended memory 2 that is added to a computer system such as a laptop type personal computer as needed. BACKGROUND OF THE INVENTION In recent years, various laptop-type personal computers have been developed that are easy to carry and can be operated with an internal battery.

In order to improve data processing functions, this type of personal computer is configured so that not only internal memory but also expansion memory can be added as needed. As the expansion memory, for example, a 2 Mbyte memory board or a 4 Mbyte memory board is often used. When such an expanded memory is used, for example, 1 MB of internal memory can be used as 3 MB or 5 MB of memory.

Therefore, by using the expansion memory, the user can expand the storage capacity of the internal memory to a desired capacity depending on the purpose of using the personal computer.

However, in conventional personal computers, the relationship between the storage capacity of the expansion memory and the expansion memory connector for installing the expansion memory is fixed under certain conditions in order to facilitate address assignment to the expansion memory. It is determined that That is, conventionally, 2M
There were separate connectors for the byte expansion memory and 4M byte expansion memory, and memory boards could only be attached to the corresponding connectors. Therefore, when adding expanded memory,
Prior to installing the memory board, the user must identify each connector type individually, creating a problem in which the user's work to expand the memory becomes complicated.

Furthermore, when adding two or more expansion memories to three or more connectors, attach the expansion memories to the connectors in a predetermined order so that there are no empty connectors between the connectors being used. There was a need. For this reason, the memory can only be expanded to a limited extent under certain restrictions, and the degree of freedom in expanding the memory capacity is low.

(Problem to be Solved by the Invention) As mentioned above, conventionally, the storage capacity of the expansion memory that can be installed is determined for each connector, and when multiple expansion memories are installed, the installation position of each expansion memory is also specified. As a result, the user has to complicate the task of adding memory, and the degree of freedom in expanding the memory capacity is low.

This invention was made in view of these points, and provides an expansion memory that allows expansion memory to be attached to any connector regardless of its storage capacity, and that allows multiple expansion memories to be added without specifying the attachment position. The purpose is to provide a control method.

[Structure of the Invention] (Means and Effects for Solving the Problems) The extended memory control method according to the present invention has a first storage capacity, and a first extended memory in which an address space is divided into blocks by a plurality of control signals. a second memory having a second memory capacity larger than the first memory capacity, and having an address space divided into blocks according to a predetermined control signal among the plurality of control signals;
expansion memory and multiple expansion modules that can be selectively installed.
memory mounting means, provided for each of the extended memory mounting means, and determining whether or not an extended memory is mounted on each extended memory mounting means, and the first memory mounting means for each extended memory mounting means.
and a plurality of identification information holding pieces for each of the control signals, each holding identification information indicating whether activation of the control signal is permitted or not, in order to identify which second expansion memory is installed. and control means for recognizing the effective address of each of the expansion memory mounting means according to the identification information held in the identification information holding means and controlling the activation of each of the control signals based on the recognition result. It is characterized by comprising the following.

In this expansion memory control method, identification information holding means is provided for each expansion memory installation means, and the identification information is used to determine whether the first or second expansion memory is installed in each expansion memory installation. Each method can be recognized. Therefore, regardless of whether the first or second expansion memory is installed, it is possible to recognize the effective address for each expansion memory, and thereby control the energization of the control signal.

Therefore, the extended memory can be attached to any connector regardless of its storage capacity. Further, since it is possible to recognize whether an expansion memory is installed or not for each expansion memory installation/means based on the identification information, the effective address can be correctly recognized even if there is an empty connector between the connectors in use. Therefore, it is possible to add a plurality of expansion memories without specifying the mounting position.

(Example) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a system configuration in an embodiment of the present invention.

In FIG. 1, numeral 11 is a main CPU that controls the entire system, and here it is realized by a 32-bit CPU chip. 12 and 13 are internal buses connected to CPULI, of which 12 is a 16-bit wide internal data bus and 13 is a 24-bit wide internal address bus. 14 is an optional numerical calculation processor (14) selectively connected to the internal data bus 12 via a connector
(Numercal Data Processor)
15 is a 16-bit wide data bus 15D,
This system bus is composed of a 20-bit wide lower address bus 15L and a 7-bit wide upper address bus 15U.

1B is a bus driver (BUS
-DRV)" 17 is a bus controller (BUS-CNT) that controls the system bus 15. +8 is a bus controller (BUS-CNT) that controls address buses 13-15 (U, L), controls the transfer of addresses between each other, and controls read/write of the main memory 19. , a memory controller (MEM-CN T) that controls read/write of the extended memory 3°, and the configuration of the memory controller 18 will be described later with reference to FIGS. Main memory accessed under address control (1-RA
M). 20 is BIOS (basic output program)
This is a B I 08-ROM that stores . 21 decodes the I10 address on the system bus 15 and passes it to the corresponding I10 element (chip).
o-DEC) 22 is an I10 controller (Ilo-CNT) that controls input/output of I10 data, 23 is a super integration IC (81 ), 24 is a frequency oscillator (VFO) that generates a clock for the floppy disk drive (FDD), 25 is a floppy disk drive interface (FDD-1/F), 2B is a hard disk drive interface (HDD-1/F),
27 is a keyboard controller (WBC), 28 is a keyboard scan controller (SCC), 29 is a backup RAM (CB-RAM) provided for the resume (1?EsIJMR) function, etc., and 30 is an optional expansion memory board connector as required. This is an extended memory board (EXTM) installed in C1, C2, and C3 (see Figure 4), and the configuration of this extended memory board 30 is shown in Figures 2 and 3.
This will be described later with reference to the drawings. 31 has its own operating battery and memory backed up by the same battery (0MO5-RAM
) with a clock module (RTC; Real-Tl
seClock), 32 is an input/output board (PRT/FDD-
IF), 33 is a serial input/output interface (SI
O). 34 is an intelligent power supply (PS) equipped with a power control CPU (PC-CPU) that supplies and controls power for the operation of the device, and here two main memories (BT-L, BT-R) are installed.
can be connected to a power control CPU (PC
-CPU) controls various operating power supplies under the control of the CPU II, and the status of each power supply is notified to the CPU II via the I10 controller 22. 35 is a display controller CDl5P-C which is a display system within the device.
NT), and here we refer to so-called flat panel displays such as plasma displays (hereinafter referred to as FDPs), liquid crystal displays (hereinafter referred to as LCDs), color panels (color LCDs), and CRT displays (hereinafter referred to as CRTs).
(referred to as ) are the drive targets.

41 is floppy disk drive interface 2
5 is a floppy disk drive (FDD) mounted in the device, and 42 is a hard disk drive (HDD) connected to one hard disk controller 2B.
D), 43 is a keyboard unit (KB) connected to the keyboard scan controller 28, 44 is a numeric keypad (tenkey), and 45 to 47 are display devices connected to the display controller 35, of which 45 is a keyboard unit (KB) connected to the keyboard scan controller 28; LCD with backlight
, 46 is an FDP, and 47 is a CRT. CIG is a flat panel display connecting connector, and C1l is L connected to the flat panel display connecting connector CIO.
The connector C12 of the CD45 is the same connector of the PDP46.

FIG. 2 shows the configuration of a 4 MB expansion memory board used as the expansion memory 30 shown in FIG.

As shown in Figure 2 (A), this 4MB expanded memory includes eight dynamic RAMs (DRAs).
M) is used, and each of these dynamic RAMs has an IM×4 bit configuration. For example, if address allocation to this extended memory starts from the 1M byte, as shown in the figure, the first and second dynamic RAMs (DRAMl, 2) will have addresses +0
The address IFPPFF is assigned from 0000, and the third and fourth dynamic RAMs (DR
AM3.4)1. : is address 200000 and address 2FFPPP is the fifth and sixth dynamic R
AM (DRAM5.8)1. :4. t7 dress 3o
oooo address 3PFPPF is the 7th and 8th
Addresses 400000 to 4FPPFF are assigned to the dynamic RAM (DRAM7.8).

As mentioned above, since the data bus 12 connected to the connectors 01 to c3 has a 16-bit configuration, access to the extended memory is executed in units of 16 bits. That is, the first to fourth dynamic RAMs (DRAM1
~4) constitute the first access block, and the fifth
The second access block is composed of the eight dynamic RAMs (DRAMs 5 to 8).

In this way, this 4M byte extended memory is divided into two access blocks, so the dynamic RAM
The row address strobe signal (RA
Two control signals, RASO and RASI, are used as S). The control signal RASO is the address toooo
The control signal RASI is activated when any address from o to 2FFPPF is accessed, and the control signal RASI is activated when any address from address 300000 to 4PFFFF is accessed.

In other words, the address space of this 4M byte extended memory is divided into blocks by two control signals, RASO and RASI, and when the control signal RASO is activated,
Any address from address 100000 to 2PFPPP is selected and designated by the memory address signal (MAO-9) supplied from the memory controller 18. On the other hand, when the control signal RASI is activated,
Any address from address 300000 to 4FPPP is selected and specified by the memory address signal (MAO-9) supplied from the memory controller 18.

In this way, the address space from address tooooo to 2PFFFF and the address space from address 300000 to 4PPPP are each defined by the same repeated address, and the memory address signal supplied from the memory controller 18 is
FFFF address space and addresses 300000 to 4
Which of the FFFFF address spaces is designated is determined by which of the control signals RASO and RASI is activated.

FIG. 2(B) is a block diagram schematically showing the 4 Mbyte extended memory shown in FIG. 2(A).

FIG. 3 shows the configuration of a 2 Mbyte expansion memory board used as the expansion memory 30 shown in FIG.

As shown in Figure 3(A), this 2M byte expanded memory includes 16 dynamic RAMs (DR
AM1-1B) are used, and each of these dynamic RAMs has a 256Kx4 bit configuration.

Access to this 2M byte extended memory is also executed in units of 16 bits. That is, the first to fourth dynamic RAMs (DRAMs 1 to 4) constitute a first access block, the fifth to eighth dynamic RAMs (DRAMs 5 to 8) constitute a second access block, and the ninth to fourth dynamic RAMs (DRAMs 5 to 8) constitute a second access block. 12 dynamic RAMs
(DRAMs 9 to 12) constitute a third access block, and the 13th to 16th dynamic RAMs (DRAMs 9 to 12) constitute a third access block.
DRAMs 13 to 1B) constitute a fourth access block.

In this way, this 2MB expanded memory is divided into four access blocks, so dynamic RA
A row address strobe signal (R
AS) Toshiteha, RASO.

Four control signals are used: RASI, RAS2, and RAS3. The 2M byte address space 100000 to 2PPPP of this extended memory is controlled by the control signal R.
It is divided into four by ASO, RASI, RAS2, and RAS3.

In the address space of this 2M byte extended memory, there is an address space corresponding to tppr'pp from address 100000 and 2PP17P from address 200000.
A control signal RASO in which the address spaces corresponding to F are each defined by the same repeated address.

RASI is activated, an address within the address space from address 100000 to 2PFFFF is specified by the memory address signal supplied from the memory controller 18, and the control signal RAS2. R.A.
When either S3 is activated, a memory address signal supplied from the memory controller 18 specifies an address in the address space from address 200000 to 2PFPPF.

FIG. 3(B) is a block diagram schematically showing the 2 Mbyte extended memory shown in FIG. 3(A).

FIG. 4 shows the expansion memory connector C1 shown in FIG.
An example is shown. As shown in the figure, the connector CI is supplied with 4M bytes of expansion memory supplied from the memory controller 18 so that either the 4M byte expansion memory shown in FIG. 2 or the 2M byte expansion memory shown in FIG. Slots are provided for receiving control signals RASO to RAS4. The connectors C2 and C3 have the same configuration as the connector C1, and each of the connectors C2 and C3 is provided with slots for receiving four control signals RASO to RAS4.

5 and 6 respectively show the configuration of a chip type register CTR and an ExisLence register ER provided in the memory controller 18 to identify the type of expansion memory attached to the connector CI-C3. ing.

The chip type register CTR shown in FIG.
The memory chip that makes up the extended memory installed in the connector is IM x 4 bit configuration or 256
This is used to identify whether the control signal is a KX4 bit configuration in units of control signals RASO to RAS3, and holds a 1 s in the case of the IM×4 bit configuration, and holds '0'' in the case of the 256K×4 bit configuration.

This chip type register CTR includes a 4-bit register section CTRI corresponding to connector C1, a 4-bit register section CTR2 corresponding to connector C2, and a 4-bit register section CTRI corresponding to connector C2.
12 consisting of a 4-bit register section CTR3 corresponding to
Although it has a bit configuration, it actually consists of two 8-bit type registers. In this case, 1 in total
Since it is a 6-bit register, 4 bits of it are not used.

For example, if the 4M byte expansion memory shown in Figure 2 is attached to connector C1, the 4M byte expansion memory will be used as a dynamic RA with an IM x 4 bit configuration as described above.
As shown in the figure, in the register CTRI, the bits corresponding to RASO and RASI of the register CTRI are each set to "1", and the RAS2
.

01 is set in each bit corresponding to RAS3.

The eviction register ER shown in FIG.
This is used to identify whether or not expansion memory is installed in the connector in units of each control signal RASO to RAS3. If expansion memory is installed, it holds "1", and if it is not installed, it holds "1". holds “0”.

This resistance register ER has a 12-bit configuration consisting of a 4-bit register section ERI corresponding to the connector C1, a 4-bit register section ER2 corresponding to the connector C2, and a 4-bit register section ER3 corresponding to the connector C3. Actually, the 8-bit type register 2
It is composed of individuals. In this case, the register has a total of 16 bits, of which 4 bits are not used.

For example, when the 4M byte expansion memory shown in Figure 2 is installed in connector C1, two control signals, RASO and RASI, are used for the 4M byte expansion memory as described above, and RAS2 and RAS3 are Since it is not used,
As shown in the figure, "1" is set in the bits corresponding to RASO and RASI of register ERI, and RAS2
.

"0'" is set in each bit corresponding to RAS3.

FIG. 7 shows the correspondence between the expansion memories attached to the connectors 01 to C3 and the contents of the chip type register CTR and the resistance register ER.

Here, connector C1 has a 4MB expansion memory 30.
As an example, a case is shown in which a connector C21: a 2M byte expansion memory 3ob is installed, and no expansion memory is installed in the connector C3. In this case, the chip type register section CT corresponding to the connector C1
In RL, as mentioned above, RASO.

“1” is set in the bit corresponding to RASI, and RAS
2. The bit corresponding to RAS3 is set to 0. Similarly, in the immunity register ERI corresponding to the connector CI, the bit corresponding to RASO and RASI is set to "1", and the bit corresponding to RAS2 and RAS3 is set to "1". '0' is set in the corresponding bit. Also, connector c2
In the chip type register section CTRI corresponding to , the 2M byte extended memory is composed of a dynamic RAM with a 256x4 bit configuration, so as shown in the figure, all bits corresponding to the four control signals RASO to RAS3 are set to '01'. Set. In the event resistance register section ER2 corresponding to the connector C2, the 2M byte expansion memory uses all four control signals RASO to RAS3, so as shown in the figure, RASO.

"1#" is set in the bits corresponding to RASI, RAS2, and RAS3.Furthermore, in the eviction register section ER3 corresponding to the connector C3,
Since no expansion memory is attached to the connector C3, all bits corresponding to the four control signals RASO to RAS3 are set to "0". In the chip type register section CTR3 corresponding to the connector C3, since no expansion memory is installed in the connector C3, the four control signals RA
All bits corresponding to SO to RAS3 are in an undefined state, and are set to, for example, "0" as shown in the figure.

For example, if the priority is assigned in the order of connectors C1, C2 and C3 while the chip type register CTR and the resistance register ER are set as described above, the 4 MB expansion memory 30a is The 2M byte address space from address 10000G to 2FPFPF is allocated as a valid address by the control signal RASO, and the 2M byte address space from address 300000 to 4PPPPF is allocated as a valid address by the control signal RASI.
Bytes of address space are allocated as effective addresses. i.e. address 100000 and 2FPFPF
When accessing the expanded memory at an address between the two, the control signal RASO for the connector CI is activated. Further, when accessing the extended memory at an address between 300000 and 4FPFPF, the control signal RASI for the connector C1 is activated.

On the other hand, the control signal R is stored in the 2M byte expansion memory 30b.
Address 500000-57PFFF by ASO
The address space of 0.5M bytes up to 5FFPPP is allocated as a valid address, and similarly, the address space of 0.5M bytes from address 580000 to 5FFPPP is allocated as a valid address.
Byte address space, 80 by control signal RAS2
0.5M byte address space from 0000 to 87FPPP and control signal RAS3
Address spaces of 065 Mbytes from o to 6PFFFF are respectively allocated as valid addresses. In other words, when accessing the extended memory at an address between address 500000 and 57Pl'PF, connector C
The control signal RASO for 2 is activated. In addition, when accessing the extended memory at an address between addresses 580000 and 51'FPFl', the control signal RASI for connector C2 is
When accessing the extended memory using an address between PPs, the control signal RAS2 for connector C2 is
When accessing the extended memory with an address between soooo and 6PFPFF, control signal R to connector C2
AS3 are respectively energized.

In this way, addresses are assigned to the expansion memory attached to connectors Cl-C5 for each connector C1-C3.
The activation of the control signal is performed according to the contents of the chip type register CTR and the existence register ER, which hold identification information corresponding to the can be controlled. Therefore, it is possible to attach the expanded memory to any connector regardless of its storage capacity.

In addition, the presence or absence of expansion memory can be recognized for each connector based on the contents of the resistance register ER.
Valid addresses can be recognized correctly even if there is an empty connector between the connectors being used. For this reason, for example, in FIG. 7, even if a 2M byte expansion memory 30b is attached to connector C3 and connector C2 is used as an empty connector, no valid address is set to connector C2, so the memory 30b is attached to connector C3. The same address space (addresses 500000 to 6PFFFF) as described above can be allocated to the 2M byte expanded memory 30b.

FIG. 8 shows an example of the configuration of a memory controller 1B that controls the generation of control signals RASO to RASI. In FIG. 8, lot is the upper 4 bits A20 of address signals AO to 23 supplied from the main CPU II.
This is a decoder that decodes ~23. 102 is the aforementioned chip type register CT R102, and 103
is the above-mentioned eviction register ER. 104
is an effective address calculation circuit that calculates the effective address range of the expansion memory connected to each connector based on the contents of the chip type register CTR and the existence register ER.

This effective address calculation circuit 104 is, for example, a connector C.
1 is equipped with a 4M byte expansion memory, the contents r0011J of the register section CTRL of the chip type register CTH and the contents r0011J of the register section ERI of the event register ER explained in FIGS. 5 and 6. Based on this, for example, a 4M byte address space from address 100000 to 4PPPP is calculated as a valid address. As described above, this calculation of the effective address is actually executed in units of each control signal of RASO to RAS8, that is, in units of each bit of the chip type register section CTRL and the intensity register section ERI. In other words, if the connector CIl:l:4M byte expansion memory is installed, the control signal RASO
For the control signal RASI, the first 2M bytes from addresses 100000 to 2PFPFF are valid, and for the control signal RASI, the remaining 2M bytes from addresses 200000 to 4FFFFF are valid.
The effective address calculation circuit 10 determines that M bytes are valid.
Calculated by 4.

105 is a control circuit that controls the supply of control signals RASO to RAS3 to each connector to which the expansion memory 30 is attached, and based on the decoding result of the decoder Lot and the calculation result of the effective address calculation circuit 104,
A necessary control signal is generated among O to RAS3. lO
B and 107 are the lower 20 bits AO~20 to 1 of the address signal AO~23 supplied from the main CPU II.
A row address buffer and a column address buffer that receive a 0-bit row address and a 10-bit column address, respectively. 108 is a selector that alternately selects a row address and a column address, and the selected address is 10 for each connector to which the expansion memory 30 is installed.
It is supplied as a bit memory address MAO-9.

FIG. 9 shows a decoder 101.1 provided in the memory controller 18. Chip type register CTR102,
Ibistance register E R103, effective address calculation circuit 104. An example of a specific configuration corresponding to one connector C1 in the control circuit 105 is shown.

In FIG. 9, 201 to 204 are decoders corresponding to the connector C1 of the decoder 101, and when each of these decoders 201 to 204 receives a predetermined address,
A "1" level signal is supplied to the corresponding AND gate.

Numerals 301 to 304 are effective address calculation circuits corresponding to the connectors CI of the effective address calculation circuit 104, and each calculates an effective address based on the corresponding set data of the chip type register section CTRI and the existence register section ERI. 401a to 404a and 401b to 404b are AND gates 61 to 404b, respectively.
Together with G4, this is an upper limit comparator and a lower limit comparator that constitute a part corresponding to the connector C1 of the control circuit 105. The upper limit comparators 401a to 404a compare the upper limits of the effective address range calculated by the corresponding effective address calculation circuits with the addresses A20 to 23, and determine whether the addresses specified by the addresses A20 to 2B are the upper limits of the effective address range. When less than, the corresponding AND
A “1” level signal is supplied to the gate. Lower limit comparator 40
1b to 404b compare the lower limit of the effective address range calculated by the corresponding effective address calculation circuit with the addresses A20 to 23, and calculate the addresses A20 to 23.
When the address specified by is larger than the lower limit of the effective address range, a "1 rubel signal is supplied to the corresponding AND gate.

As explained above, in this embodiment, the chip type register CTR and the resistance register ER are
Based on the identification information set in , it is possible to recognize for each connector Cl-C8 whether a 4M byte or 2M byte expansion memory is installed. For this reason, 4
Regardless of whether M-byte or 2-Mbyte expansion memory is installed, it is possible to recognize the effective addresses for each connector 01 to C3, and thereby control the activation of control signals RASo to RAS3. .

Therefore, it is possible to attach the expanded memory to any connector regardless of its storage capacity.

In addition, the presence or absence of expansion memory installed in each connector 01-
Since each C3 can be recognized, the effective address can be recognized normally even if there is an empty connector between the connectors being used. Therefore, it is possible to add a plurality of expansion memories without specifying the mounting position.

[Effects of the Invention] As described above, according to the present invention, a system is provided in which an expansion memory can be attached to any connector regardless of its storage capacity, and a plurality of expansion memories can be added without specifying the attachment position. realizable.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the overall configuration of a system according to an embodiment of the present invention, FIGS. 2 and 3 are diagrams each showing an extended memory added to this system, and FIG. 4 is a block diagram showing the extended memory added to this system. Figures 5 and 6 are diagrams showing the connectors to be installed in this system, Figures 5 and 6 are diagrams respectively showing the chip type register and the resistance register provided in this system, and Figure 7 is the type of expansion memory and the chip type register. FIG. 8 is a block diagram showing the configuration of the memory controller provided in this system.
FIG. 9 is a block diagram showing a specific configuration of a portion of the memory controller shown in FIG. 8. DESCRIPTION OF SYMBOLS 11... Main CPU, 1g... Memory controller, 30... Expansion memory, C1-C3... Connector for expansion memory, 102... Chip type register (CTR) 03... Ibidistance register (ER)

Claims (1)

[Scope of Claims] A first expanded memory having a first storage capacity and having an address space divided into blocks according to a plurality of control signals, and a second storage capacity larger than the first storage capacity. a plurality of expansion memory mounting means for selectively mounting a second expansion memory whose address space is divided into blocks according to a predetermined control signal among the plurality of control signals; and a plurality of expansion memory mounting means for each of the expansion memory mounting means. for identifying whether or not an expansion memory is installed in each expansion memory installation means, and which of the first and second expansion memories is installed in each expansion memory installation means,
a plurality of identification information holding means each holding identification information indicating whether or not activation of the control signal is permitted for each of the control signals; Recognizes the effective address of each expansion memory installation means,
An extended memory control system comprising: control means for controlling energization of each of the control signals based on the recognition result.