JPH03113773A - Spindle controller for optical disk recording and reproducing device - Google Patents

Abstract

PURPOSE:To surely detect a vertical synchronizing mark, and to favorably execute the phase control of a spindle motor based of it by generating time base reference signals with prescribed time difference in response to the switching of the operation modes of two heads. CONSTITUTION:The heads HD1,HD2 are arranged at the positions nearly symmetrical in relation to the axis of the center of rotation of the spindle motor 23. Then, a vertical synchronizing mark detection circuit 17 detects the vertical synchronizing mark VM, and outputs a synchronism mark detection signal. Besides, selector switches 28a, 28b are switched in response to the operation mode switching signals of the heads HD1,HD2. Thus, the output of a timing generation circuit 11 is switched, and the time base reference signals with the prescribed time difference are generated alternately from a phase counter 13. Then, a spindle control circuit 27 executes the phase control of the motor 23 according to the phase difference of the synchronism mark detection signal from the time base reference signal.

Description

Detailed Description of the Invention Technical Field The present invention relates to a spindle control device, and in particular to a spindle control device that controls a composite video signal of one frame per track for an optical disk (including magneto-optical disks and phase-change optical disks) having vertical synchronization marks. The present invention relates to a spindle control device for an optical disc recording and reproducing apparatus that records, reproduces, or erases synchronization signals (including synchronization signals such as horizontal synchronization signals and vertical synchronization signals).

BACKGROUND ART In conventional playback-only video disc players, since a composite video signal is already recorded on the optical disc to be played, a standard for the reproduction horizontal synchronization signal contained in the composite video signal obtained by reading and demodulating the optical disc is determined. A phase difference with respect to a horizontal synchronizing signal is detected, and spindle servo is performed according to this phase difference.

On the other hand, in a system that records a composite video signal of one frame per track on an optical disc and plays or erases it, since there is no composite video signal on the surface of the disc before recording, it is only used for playback. It is not possible to use the playback horizontal synchronization signal to apply spindle servo, as in the case of a player. For this reason, for example, a vertical synchronization mark made of a mirror surface that does not cut the pre-group for each track of the disc can be placed once per revolution of the disc.
The vertical synchronization marks are detected during recording, and the spindle servo is applied so that the timing of this detection corresponds to a predetermined position on the time axis of the composite video signal. .

By the way, write-once (DRAM) type or erase/rewrite (ED) type
Conventionally, in a recording/reproducing device for a RAM (RAM) type optical disk, recording/reproducing (or erasing) has been performed using one head. On the other hand, by providing two heads at approximately symmetrical positions with respect to the rotation center axis of the spindle motor, and configuring one head to erase and the other to record, it becomes possible to erase and record in real time. . At that time, the detection of the vertical synchronization mark is performed based on the read signal of one of the heads depending on the operating mode of the head, and a changeover switch is used to switch one of the read signals of the two heads to the operating mode. It is conceivable to adopt a configuration in which the signals are selected accordingly and supplied to the vertical synchronization mark detection circuit.

However, such a configuration is not preferable because a vertical synchronization mark may arrive at the time when the changeover switch is switched. Furthermore, there is a possibility that erroneous detection of vertical synchronization marks may occur due to switching of laser power for erasing or recording.

Summary of the Invention [Object of the Invention] Therefore, an object of the present invention is to provide a spindle control device for an optical disc recording/reproducing device that can reliably detect a vertical synchronization mark and perform good phase control of a spindle motor based on the vertical synchronization mark. shall be.

[Structure of the Invention] A spindle control device according to the present invention is a spindle control device for an optical disk recording and reproducing device that records one frame of composite video signal on one track on an optical disk having a vertical synchronization mark, and plays or erases the composite video signal. And,
a spindle motor that rotationally drives the optical disk; two heads disposed at substantially symmetrical positions with respect to a rotation center axis of the spindle motor; and a detection means that detects the vertical synchronization mark and generates a synchronization mark detection signal; reference signal generating means for alternately generating time axis reference signals having a predetermined time difference in response to switching of the operation modes of the two heads; and control means for controlling the phase of the spindle motor.

[Operation of the Invention] In the spindle control device according to the present invention, one frame per track is recorded on an optical disk having a vertical synchronization mark by one of the two heads arranged at substantially symmetrical positions with respect to the rotation center axis of the spindle motor. A composite video signal is recorded, and the other head plays back or erases it, detects a vertical synchronization mark and generates a synchronization mark detection signal, and also generates a synchronization mark detection signal according to the switching of the operation mode of the two heads. Time axis reference signals having time differences are generated alternately, and the phase of the spindle motor is controlled according to the phase difference between the synchronization mark detection signal and the time axis reference signal.

Example Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

As shown in FIGS. 1 and 2, an optical disc recording and reproducing apparatus equipped with a spindle control device according to the present invention is arranged at approximately symmetrical positions with respect to the rotation center axis O of a spindle motor SM that rotationally drives a disc D. two heads H
It has DI and HD2. These two head MDI,
The HD 2 is used, for example, as a combination of a recording head and an erasing head, or at least one of them is used as a reproducing head. Further, as will be described later, it is assumed that the above-mentioned vertical synchronization mark VM is detected based on the read RF multiplied signal of the head HDI, for example.

Next, the configuration of the spindle control device according to the present invention will be explained based on the block diagram of FIG. 3. In FIG. 3, a composite video signal to be recorded is applied to the input terminal IN, and an external synchronization signal is applied to the input terminal IN2. These input signals become two input signals of the selector 1, and one of them is selected by the switching control signal a and becomes one input of the selector 2. Selector 2 is clock generation circuit 3
A composite synchronization signal generated as an internal synchronization signal from the synchronization generation circuit 4 based on a master clock having a frequency of 4fsc (fsc is the color subcarrier frequency) from Either input signal is selected and output.

In other words, when recording a composite video signal, the composite video signal is
An external synchronization signal is selected during external synchronization operation, and an internal synchronization signal (composite synchronization signal) is selected during internal synchronization operation. The selected signal is supplied to the synchronization separation circuit 5. In the synchronization separation circuit 5, the vertical synchronization signal and the composite synchronization signal are separated and supplied to the vertical synchronization compensation circuit 6 and the horizontal synchronization compensation circuit 7, respectively.

When the horizontal synchronization signal in the composite synchronization signal is detected multiple times in succession by the internal counter, the horizontal synchronization compensation circuit 7 determines that the circuit is in a synchronized state and outputs a high-level horizontal synchronization OK signal. A horizontal synchronization clock is generated in synchronization with the horizontal synchronization signal and having a frequency twice the horizontal synchronization frequency. The composite synchronization signal is also provided to the selection logic 8. The selection logic 8 also receives the horizontal synchronization OK double signal and timing gate signal output from the horizontal synchronization compensation circuit 7, and allows the composite synchronization signal to pass through as is when the horizontal synchronization OK double signal is not input, that is, when there is no horizontal synchronization. When the horizontal synchronization OK double signal is input, that is, during horizontal synchronization, only the horizontal synchronization signal is extracted from the composite synchronization signal based on the timing gate signal.
It is supplied to the LL circuit 9. The PLL circuit 9 generates a regenerated clock having a frequency of 4 fsc in synchronization with the horizontal synchronizing signal.

The above-mentioned horizontal synchronization compensation circuit 7, selection logic 8 and PL
The specific circuit configuration and circuit operation of the L circuit 9 are described in detail in Japanese Patent Application No. 1-111343 filed by the present applicant.

The master clock with a frequency of 4fsc generated by the clock generation circuit 3 and the regenerated clock with a frequency of 4fsc generated by the PLL circuit 9 are the two-man power of the selector 10,
The switching control signal selects the mask clock from the clock generation circuit 3 during internal synchronous operation, and selects the recovered clock from the PLL circuit 9 during external synchronous operation, and supplies the selected clock to the horizontal synchronization compensation circuit 7 and timing generation circuit 11 as the system clock.

Count data of the internal counter of the vertical synchronization compensation circuit 6,
The horizontal synchronization clock outputted from the horizontal synchronization compensation circuit 7, the count data of the synchronization compensation counter, and the system clock are supplied to the timing generation circuit 11. The timing generation circuit 11 generates a count enable signal ENBL1. for the phase counter 13, which will be described later. ENBL2 and clear signal CLI.

Cl3, an address gate signal for extracting the address data contained in the read RF signal, as well as a write (
Various timing signals are generated, including a write gate signal for recording. Count enable signal ENBL
The generation timings of I, ENBL2 and clear signals CLI, CL2 are shown in FIG.
BL2 is generated as a several H width pulse at timings of 525H and 259°5H, respectively, and clear signals CLI and Cl3 are generated at timings of 259.5H and 525H, respectively. That is, count enable signals ENBLI and E
NBL2 and clear signals CLI and Cl3 each have a time difference equivalent to one field (262, 5H).

Count enable signals BNBLI, ENBL2 and clear signals CL1. CL2 is the changeover switch 28a
, 28b selects one of them, and the delay circuit 1
2a and 12b, the signal is delayed by a predetermined delay time and is supplied to the phase counter 13. The changeover switches 28a and 28b are controlled by a mode change signal issued from a controller (not shown) in order to change the operating mode of the system from one head to the other head. The phase counter 13 receives the count enable signal ENBLI or E.
The count is enabled only while NBL2 is at a high level, and when the clear signal CLI or Cl3 is input, the count data is cleared and becomes all 0s. Note that the phase counter 13 is supplied with a clock obtained by dividing the system clock by N in a frequency dividing circuit 14 .

Count data of the phase counter 13 is supplied to a latch circuit 15 and an all-1 detection circuit 16.

When the all 1 detection circuit 16 detects that the count data of the phase counter 13 is all 1, the phase counter 1
A hold signal is output for 3.

When this hold signal is input, the phase counter 13 stops counting operation, and the count data maintains a state of all 1s until the next clear signal is input.

As mentioned earlier, a vertical synchronization mark VM is provided for each track on an optical disc at one location per one revolution of the disc, and this vertical synchronization mark VM is connected to the read RF multiplied signal input from the head HDI (see Figure 1), for example. It is detected by the vertical synchronization mark detection circuit 17. The vertical synchronization mark detection circuit 17 detects a synchronization mark component included in the read RF signal and outputs a synchronization mark detection signal. This synchronization mark detection signal is supplied to the synchronization mark detection compensation circuit 18 and becomes one input of a two-manual AND gate 19. The synchronization mark detection compensation circuit 18 basically has the same circuit configuration as the horizontal synchronization compensation circuit 7, and when the synchronization mark detection signal is detected multiple times in succession at a predetermined interval, a high-level synchronization mark detection OK signal is generated. If the synchronization mark detection signal is consecutively missed a plurality of times within a predetermined window after the synchronization is OK, the output of the synchronization mark detection OK signal is stopped.

The synchronization mark detection OK signal becomes the extraction input of the AND gate 19 and also becomes the one-man power of the three-man power AND gate 20. A
The ND gate 20 is supplied with the horizontal synchronization OK signal outputted from the horizontal synchronization compensation circuit 7 as another signal.

When the synchronization mark detection OK signal is output from the synchronization mark detection compensation circuit 18, the synchronization mark detection OK signal passes through the AND gate 19 and is supplied to the latch circuit 15 as a latch signal. As a result, the count data of the phase counter 13 is latched at the detection timing of the vertical synchronization mark, and the count data of the phase lock detection circuit 21 and the selector 2 are latched as phase data.
2. The phase lock detection circuit 21 determines that the phase lock is completed if the position data is within a predetermined range, and outputs a spindle lock signal. Here, the resolution of the phase control is that one horizontal opening period is IH-fsex2/4
Since it is 55-4 fsc/910 and the clock of the phase counter 13 is 4 fsc/N, it becomes.

A frequency generator (FG) that detects the rotational speed of the motor is attached to the spindle motor 23 that rotationally drives the disk, and an FG multiplier signal is output from the frequency generator as rotational speed information via the input terminal INB. and is supplied to the frequency error detection circuit 24. The frequency error detection circuit 24 detects an error in the rotational speed of the spindle motor 23 with respect to the reference speed based on the FG multiplied signal, and outputs a frequency error signal indicating the error. Further, the frequency normality detection circuit 25 detects whether the frequency error signal level is within a predetermined range, and if it is within the predetermined range, it is determined to be normal and outputs a frequency OK multiplied signal. This frequency O
This becomes the remaining one-man power of the three-man power AND gate 20 at the destination of the K times signal.

AND gate 20 generates an output when all of the synchronization mark detection OK signal, horizontal synchronization OK double signal and frequency OK double signal are input, and the output becomes a switching control input of selector 22. As a result, when the output of the AND gate 20 is generated, the selector 22 selects the phase data latched by the latch circuit 15 and supplies it to the DA converter 26 at the next stage, and otherwise uses the center value of the DA converter 26. Select and output data corresponding to the DA converter 26
The output of is the phase error signal. That is, the phase error signal is output only when horizontal synchronization is achieved, the vertical synchronization mark is normally detected, and the FG frequency falls within a predetermined range.

The frequency error signal and the phase error signal are supplied to a spindle control circuit 27 to control the phase of the spindle motor 23.

Next, the operation of phase control will be explained with reference to the timing chart of FIG. In order to simplify the explanation, the operation will be explained with respect to only one of the count enable signal ENBLI and the clear signal CLI.

One frame of composite video signal is recorded on one rotation of the disk, that is, on one track, and a count enable signal (a) is generated by the timing generation circuit 11 within a predetermined range within this one frame, and this signal is sent to the delay circuit 1.
2 and becomes a delayed enable signal (b), which is supplied to the phase counter 13. The phase counter 13 is in a count enable state and performs a counting operation during the period when the delay enable signal (b) is at a high level.

On the other hand, a clear signal (C) is generated by the timing generation circuit 11 at a location shifted by one field (1/2 frame) with respect to the count enable signal (a), and this is delayed by the delay circuit 12 to generate a delayed clear signal. (d) and is supplied to the phase counter 13. Note that if the amount of delay by the delay circuit 12 is not too large, it is not necessary to delay the clear signal (C). The count data of the phase counter 13 is cleared by this delayed clear signal (d).

As a result, the count data (e) of the phase counter 13 shown in analog form becomes all 0s due to the delayed clear signal (d), increases in clock cycles by applying the delayed enable signal (b), and becomes all 1s at the point in time. This becomes a trapezoidal wave that maintains all 1s until the next delayed clear signal (d) is applied. The slope portion of the trapezoidal wave of this count data (e) becomes a time axis basic signal that is generated at a predetermined position on the time axis in synchronization with the composite video signal to be recorded.

Therefore, when applying phase control using this trapezoidal wave,
Phase entrainment is performed at the slope part of the trapezoidal wave, and its resolution is as described above.

Now, in FIGS. 1 and 2, if the head MDI is used for reproduction, the head HD2 is used for recording, and the vertical synchronization mark is detected based on the read RF multiplied signal of the head HDI, then the phase of the spindle motor 23 described above is assumed to be As a result of the control, as shown in FIG.
It is generated in a period of 4H and is controlled to be located at the center of the slope of the trapezoidal wave (a). At this time, in the reproduction system (not shown), the read R is read by the address gate signal (C) generated from the timing generation circuit 11 in the period 13H to 19H.
It is assumed that the address data contained in the F-fold signal b) is extracted and read.

On the other hand, since the head HD2 is located at a position 180@ opposite to the head HDI, the address data read by the head HD2 is shifted by an amount equivalent to one field. Therefore, when switching the operating mode of the system from the reproduction head HD1 to the recording head HD2, the count enable signal is changed from ENBLI to ENBL2 by controlling the changeover switches 28a and 28b in FIG. 3 using the mode changeover signal.
The clear signal is switched from CLI to Cl3. As a result, in the playback mode, 522H to 522H as shown in FIG. 7A.
A trapezoidal wave with a slope at 524H is the 7th wave in recording mode.
As shown in Figure B, 1 field (1 frame is 525H)
It becomes a trapezoidal wave with a slope portion between 259.5H and 261.5H with a corresponding deviation. That is, the phase control of the system is performed by the vertical synchronization mark VM obtained by the head MDI, and this vertical synchronization mark VM is 259.
Since the head HD2 is located in the period from 5H to 261.5H, the head HD2 is equivalently located in the period from 522H to 524H.

In the above embodiment, a vertical synchronization mark VM is provided for each track, and two heads HDI are provided.

Although the configuration is such that the vertical synchronization mark detection circuit 17 detects the vertical synchronization mark VM based on the read RF signal from only one side of the HD 2, the present invention is not limited to this. For example, vertical synchronization may be performed only on the inner or outer circumference of the disk. A configuration may also be adopted in which a mark VM is provided and the vertical synchronization mark VM is directly detected by a vertical synchronization mark detector such as a photocoupler. In this case, the time difference in shifting the slope of the trapezoidal wave as the time axis reference signal according to the switching of the operation mode is:
The time corresponds to the difference between the angular position of the detector in the disk rotation direction and the angular position of the head corresponding to the current mode.

As described in detail, the spindle control device according to the present invention records one frame of composite video signal on one track on an optical disc having a vertical synchronization mark, and performs optical disc recording/playback for reproducing or erasing the composite video signal. The device has two heads arranged at approximately symmetrical positions with respect to the rotation center axis of the spindle motor, and detects a vertical synchronization mark and generates a synchronization mark detection signal.
A configuration in which a time axis reference signal having a predetermined time difference is alternately generated according to switching of the operation mode of two heads, and a spindle motor phase is controlled according to a phase difference of a synchronization mark detection signal with respect to the time axis reference signal. As a result, even if the operation mode is switched between two heads, a time axis reference signal corresponding to each head is generated, so that the phase of the spindle motor can be controlled satisfactorily.

[Brief explanation of drawings]

FIG. 1 is a schematic perspective view showing the configuration of a recording and reproducing section of an optical disk recording and reproducing apparatus equipped with a spindle control device according to the present invention, FIG. 2 is a plan view thereof, and FIG. 3 is an implementation of the spindle control device according to the present invention. A block diagram illustrating an example, FIG. 4, shows count enable signals ENBL1. ENBL2 and clear signal CL1. FIG. 5 is a timing chart showing the timing of generation of CL2. FIG. 5 is a timing chart for explaining the operation of phase control. FIG. Timing chart shown, No. 7
Figure A is a timing chart in playback mode, Figure 7B
The figure is a timing chart in recording mode. Explanation of symbols of main parts 3...Clock generation circuit 5...Synchronization separation circuit 9...PLL
Circuit 11... Timing generation circuit 13... Phase counter 17... Vertical synchronization mark detection circuit 23...
... Spindle motor 24 ... Frequency error detection circuit 27 ...
・Spindle control circuit

Claims (5)

[Claims] (1) A spindle control device for an optical disc recording and reproducing apparatus that records one frame of composite video signal on one track on an optical disc having a vertical synchronization mark, and plays or erases the same, and that rotationally drives the optical disc. a spindle motor; two heads disposed at substantially symmetrical positions with respect to a rotation center axis of the spindle motor; a detection means for detecting the vertical synchronization mark and generating a synchronization mark detection signal; and operation of the two heads. a reference signal generating means that alternately generates time axis reference signals having a predetermined time difference in response to mode switching; and phase control of the spindle motor in accordance with a phase difference of the synchronization mark detection signal with respect to the time axis reference signal. 1. A spindle control device comprising a control means. (2) The spindle control device according to claim 1, wherein the detection means comprises a detection circuit that detects the vertical synchronization mark based on a read signal from the optical disk of only one of the two heads. (3) The spindle control device according to claim 2, wherein the predetermined time difference is equivalent to one field. (4) The spindle control device according to claim 1, wherein the detection means comprises a detector that directly detects the vertical synchronization mark from the optical disc. (5) The spindle control according to claim 4, wherein the predetermined time difference is a time corresponding to a difference between the angular position of the detector and the angular position of the head corresponding to the current mode in the disk rotation direction. Device.