JPH03113543A - Cpu device - Google Patents

Abstract

PURPOSE:To prevent the CPU runaway due to the absence of plastic to be executed by providing an function selecting means which resets a CPU only when a detection means that detects the connection or non-connection of a ROM detects the connection of the ROM. CONSTITUTION:When a ROM 4 is attached to a socket 7, the light of a light emitting element 2 is reflected by the bottom part of the ROM 4. A light receiving element 3 receives the reflected light and is turned on. Meanwhile the element 3 is unable to receive the light of the element 2 if the ROM 4 is not attached to the socket 7. As a result, the output of a comparator 5 is kept at 'Lo' and a CPU 6 performs no processing action. Thus a sensor 1 decides whether the ROM 4 is attached or not. If not, the processing action of the CPU 6 is inhibited. Therefore the CPU runaway is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Industrial field of application This invention relates to a ROM that stores a processing program for a CPU.
This invention relates to a CPU device that is externally attached.

(bl Conventional Technology Generally, a control unit that controls the operation of input/output equipment is
As shown in FIG. 4, a CPU device consisting of a CPU 30 to which a ROM 31 and a RAM 32 are connected is used. A program that defines the processing operations of the CPU 30 is stored in the ROM 31 in advance. The RAM 32 is used as a buffer memory and a calculation area for flags and the like required for control operations. CPU 30 outputs control data to driver array 36 via I10 interface 34 in accordance with a program stored in ROM 31 in response to signals input from signal input device 35 via I10 interface 33. The driver array 36 is C
Each input/output device is driven according to control data output from the PU 30. When the processing operation of the CPU 30 is relatively simple, the amount of programs to be stored in the ROM 31 is small, and the ROM 31 and the RAM 32 are integrated with the CPU 30 in a one-chip IC. However, C.P.
If the processing operation of tJ30 is complex and the amount of programs to be stored in the ROM 31 is large, or if replacing the program later is considered, the ROM 31 is externally attached to the CPU 30.

(C) Problems to be Solved by the Invention However, when the ROM 31 is externally attached to the CPU 30, the ROM 31 may not be properly connected due to a mistake in the manufacturing process. In this way CPU30
When the ROM 31 is not connected to the ROM 31, the program data at each address becomes F F H as shown in FIG. When the power is turned on to the CPU 30 in this state, as shown in FIG.
FFFF is stored in C (nl). As a result, the CPU 30 jumps to the address F F F F, and executes the instruction at this address, that is, C
Execute ALLT (7Fu) (n2).

This is 007F)l, 0080. Contents of the address (F
FFFH).

As a result of this process, in the RAM 32 shown in FIG.
3) Calculate the contents of stack pointer SP by 2ffA (
n4). Therefore, the contents of the stack pointer SP become the address 5P-2 shown in FIG.

Since OO7F and I are called in the process of n2, the contents of the program counter PC are always set to FFFF□, and the processes of 02 to n4 are repeatedly executed. As a result, the process n3 is executed for the memory areas of all addresses in the RAM 32 from the address with the highest number to the address with the lowest number, and the contents of all the writable memory areas become 0. , C
There is a problem in that the PU 30 causes what is called a runaway, and also makes it impossible to carry out processing operations after the runaway.

The purpose of this invention is to prevent the CPU from ROM-ROM when the power is turned on to the CPU with no ROM connected to the CPU.
It is an object of the present invention to provide a CPU device capable of preventing a CPU from running out of control by not executing a normal processing operation performed by referring to a program stored in a CPU.

(d) Means for Solving the Problems The CPU device according to the invention described in claim (1) is a CPU device that executes processing operations according to a program written in advance in an externally attached ROM, and the ROM is connected to the CPU device. detection means for detecting whether or not the
The present invention is characterized in that it includes operation selection means for resetting the CPU only when the detection means detects that the ROM is connected.

Further, the CPU device according to the invention described in claim (2) is a CPU device that executes processing operations according to a program written in advance in an externally attached ROM, and detects whether or not the ROM is connected. detection means;
The storage means that stores an error mode program that does not refer to the program written in the RAM, and the detection means are R.
R depending on whether the OM detects that it is connected or not.
In the invention described in claim Tl above (effect e1), the invention is characterized in that a switching means is provided for selectively validating either the program of the OM or the program of the storage means. The CPU will only be reset if it is connected. Therefore, when the ROM is not connected, the CPU is not reset, and even when the power is turned on, the CPU does not start processing operations.

Furthermore, in the invention described in claim (2), the CPU
If ROM is connected to °ζ, I? The programmer 1) of the OM is enabled, and if the ROM is not connected to the CPU, the program of the storage means is enabled. Since this storage means stores an error mode program that does not refer to the ROM program, the CPU executes the error mode processing operation when the ROM is not connected. FIG. 2 is a circuit diagram showing the configuration of an embodiment of the CPU device according to the invention described in item (1).

The output terminal of the comparator 5 is connected to the reset terminal R3T of the CPU 6. A non-inverting input terminal of this comparator 5 is connected to a collector terminal of a light receiving element 3 constituting a sensor l which is a detection means of the present invention. The sensor 1 consists of a light emitting element 2 and a light receiving element 3, and is fixed upward to the bottom of a ROM mounting socket 7, as shown in FIG. Therefore, when the ROM 4 is attached to the socket 7, the light from the light emitting element 2 is reflected at the bottom of the ROM 4, and the light receiving element 3 receives this reflected light and turns on.

When the light receiving element 3 is turned on in this manner, the output of the comparator 5 becomes "Hi", the reset terminal R3T becomes "Hi", and the CPU 6 executes processing operations according to the program stored in the ROM 4.

On the other hand, when the ROM 4 is not installed in the socket 7, the light receiving element 3 cannot receive the light from the light emitting element 2 and is not turned on. Therefore, the output of comparator 5 is “Lo
” and the CPU 6 does not execute any processing operation.

As described above, it is possible to determine whether or not the ROM 4 is installed using the sensor l, and prevent the CPU 6 from executing processing operations when the ROM 4 is not installed, thereby preventing the runaway shown in FIG. 6. .

FIG. 3 is a circuit diagram of an embodiment of the CPU device according to the invention set forth in claim (2).

The output terminal of the comparator 5 is connected to the address bus A15 of the CPU 16. The inverting input terminal of this comparator 5 is connected to a sensor 1 having a configuration similar to that shown in FIG.
The collector terminal of the light receiving element 3 is connected. The sensor 1 is installed in the state shown in FIG. 2, similar to the configuration shown in FIG. 1, and the light receiving element 3 is turned on/off depending on whether the ROM 4 is installed in the socket 7.

When the ROM4 is installed in the socket 7 and the light receiving element 3 is turned on, the address bus A15 becomes "Lo" and the CPU1
6 executes the program stored in r20M4. On the other hand, if the ROM 4 is not installed in the socket 7 and the light receiving element 3 is off, the address bus A15 is "
ROM18, which is the storage means of this invention.
Enable. Therefore, when the ROM 4 is not installed, the CPU 16 executes the processing procedure according to the program stored in the ROM 18. This ROM
18 stores a program for displaying a message regarding a ROM connection failure on a display section (not shown), and the CPU 1
According to this program of No. 6, the ROM connection failure is displayed on the display section. As described in 1- below, according to this embodiment, when the ROM 4 is not connected, the ROM 18
By executing the error mode program stored in C1), runaway of C1) can be prevented.

In each of the above embodiments, a reflective photosensor is used as the detection means, but a microsinch or the like that turns on by contacting the CPU 4 may also be used.

(Effect of invention a) According to the invention described in claim [1], since the CPU does not operate when the ROM is not connected, it is possible to prevent the CPU from running out of control due to the lack of a program to be executed. There are advantages.

Further, according to the invention described in claim (2), since the error mode program stored in the storage means is executed when the ROM is not connected, the CPU does not run out of control.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of a CPU device according to the invention set forth in claim +1), and FIG. 2 is a plan view of a detection means forming a part of the CPU device. Figure 3 is claim (2)
FIG. 2 is a circuit diagram showing an embodiment of a CPU device according to the invention described in FIG. Further, FIG. 4 is a block diagram of a control section constituted by a general CPU device including an embodiment of the present invention. Furthermore, FIGS. 5 and 6 are diagrams showing the configuration and processing operation of a conventional CPU device, and FIG. 5 is a diagram showing data and instructions at each address when the ROM is not connected. Figure 6 is a flowchart showing the processing operation when the ROM is not connected;
FIG. 7 is a schematic diagram showing the configuration of the RAM connected to the CPU. 1-Senna (detection means), 5-Comparator (operation selection means), 6.16-CPU, 15-Comparator (switching means), 18-ROM (memory means) Fig. 6

Claims (2)

[Claims] (1) In a CPU device that executes processing operations according to a program written in advance in an externally attached ROM, a detection means for detecting whether or not the ROM is connected;
A CPU device comprising operation selection means for resetting the CPU only when the detection means detects that a ROM is connected. (2) in a CPU device that executes processing operations according to a program written in advance in an externally attached ROM, a detection means for detecting whether or not the ROM is connected;
The storage means that stores an error mode program that does not refer to the program written in the ROM, and the detection means are R.
R depending on whether the OM detects that it is connected or not.
A CPU device characterized by comprising: switching means for selectively validating either the OM program or the storage means program.