JPH03112969U - - Google Patents

Info

Publication number
JPH03112969U
JPH03112969U JP2044790U JP2044790U JPH03112969U JP H03112969 U JPH03112969 U JP H03112969U JP 2044790 U JP2044790 U JP 2044790U JP 2044790 U JP2044790 U JP 2044790U JP H03112969 U JPH03112969 U JP H03112969U
Authority
JP
Japan
Prior art keywords
wiring board
inner layer
layer pattern
electronic component
packaged
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2044790U
Other languages
English (en)
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP2044790U priority Critical patent/JPH03112969U/ja
Publication of JPH03112969U publication Critical patent/JPH03112969U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
JP2044790U 1990-03-02 1990-03-02 Pending JPH03112969U (me)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2044790U JPH03112969U (me) 1990-03-02 1990-03-02

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2044790U JPH03112969U (me) 1990-03-02 1990-03-02

Publications (1)

Publication Number Publication Date
JPH03112969U true JPH03112969U (me) 1991-11-19

Family

ID=31523538

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2044790U Pending JPH03112969U (me) 1990-03-02 1990-03-02

Country Status (1)

Country Link
JP (1) JPH03112969U (me)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5839071B2 (ja) * 1978-08-25 1983-08-27 日本電産コパル株式会社 ワイヤ−式ドツトプリントヘツド
JPS5999752A (ja) * 1982-11-29 1984-06-08 Toshiba Corp 混成集積回路装置
JPS6042765B2 (ja) * 1977-06-27 1985-09-25 ドラゴコ・ゲルベルデインク・アンド・コムパニ−・ゲゼルシヤフト・ミト・ベシユレンクテル・ハフツング 細菌増殖抑制法ならびに制菌剤
JPS61268049A (ja) * 1985-05-23 1986-11-27 Nec Corp Lsiパッケージ

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6042765B2 (ja) * 1977-06-27 1985-09-25 ドラゴコ・ゲルベルデインク・アンド・コムパニ−・ゲゼルシヤフト・ミト・ベシユレンクテル・ハフツング 細菌増殖抑制法ならびに制菌剤
JPS5839071B2 (ja) * 1978-08-25 1983-08-27 日本電産コパル株式会社 ワイヤ−式ドツトプリントヘツド
JPS5999752A (ja) * 1982-11-29 1984-06-08 Toshiba Corp 混成集積回路装置
JPS61268049A (ja) * 1985-05-23 1986-11-27 Nec Corp Lsiパッケージ

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