JPH03112278A - External signal input synthesis device for vtr - Google Patents

Abstract

PURPOSE:To attain the synthesis by generating a mask data based on the presence of an external video signal and synthesizing the external video signal and a reproduced video signal from a deshuffling circuit via the mask data. CONSTITUTION:An AND circuit 2d2 of a synthesis circuit 2d ANDs a reproduced video signal from a frame memory I33c of a memory board 33 and a NOTed mask data at a NOT circuit 2d1 from a mask data memory 2e of an external signal synthesis circuit 2. On the other hand, an AND circuit 2d4 ANDs an external video signal from a synthesis frame memory I'2c of the external signal synthesis circuit 2 and the mask data from the mask data memory 2e, outputs of the AND circuit 2d2, 2d4. are fed to an OR circuit 2d3 to OR them. When the mask data is logical 1, a reproduced video signal is brought into logical 0, an external signal goes to logical 1 and the external video signal is outputted. When the mask data is logical 0, the reproduced video signal is conversely outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an external signal input synthesis device applied to a VTR for recording and reproducing high-definition television signals such as high-definition television.

[Conventional technology]

A high-definition television system has been developed that has significantly superior image quality and quality compared to conventional television systems.
In Japan, there are plans to put it into practical use under the name Hi-Vision.

In this high-definition system, a wide video signal band such as a luminance signal of 20Ml1z and a color difference signal of 7M](z) is used, so a V T for recording and reproducing such information signals is used.
For R (Video Tape Records?), the conventional method cannot be applied as is; for example, the rotation speed of the magnetic head is tripled, the relative speed of the ζ tape is increased, and the video signal is converted into a digital format. , so-called TCI (Time Compress'sed
A method has been developed that performs time axis expansion or time axis compression by converting the signal into a narrow band.

In such a VTR, during playback, the playback video signal has
For example, when inputting an external video signal from a camera and creating a °C composite image, this is done in an analog manner using a composition circuit as shown in FIG.

In FIG. 5, a reproduced video signal obtained by reproducing a signal recorded on a tape is input to a synthesis circuit 51, and is input to a synchronization separation circuit 52, where a synchronization signal is separated. The separated vertical and horizontal synchronizing signals are input to the encoder 53, which detects the position at which the external video signal input to the encoder 53 is to be combined, and the analog switch 51a of the combining circuit 51 combines the reproduced signal and the external signal. The signals are switched and amplified by an amplifier 54 to obtain a composite video output.

[Problem to be solved by the invention]

However, the above-mentioned conventional synthesis circuit shown in Fig. 5 handles analog video signals, so it requires a complex video processing circuit, requires troublesome adjustment, and is difficult to maintain stable synthesis accuracy at all times. It is difficult to do so. In addition, since each circuit cannot be expected to be integrated into an IC, and is generally manufactured using discrete components, this brings about the problem of a considerable increase in cost.

[Means to solve the problem]

In order to solve the above-mentioned problems, the external signal manual synthesis device for a VTR according to the present invention digitizes the video signal to be recorded, divides and arranges fields into a plurality of recording tracks, and divides and arranges the field into a plurality of recording tracks. A VT that has a shuffling circuit and a deshuffling circuit that combine the divided and arranged video signals into the original one-field signal again.
In R's external signal manual synthesis device, during playback, the external video signal is digitized by the A/D converter in the recording system and stored in a newly provided frame memory, while mask data is generated based on the presence or absence of the external video signal. is created, and the reproduced video signal from the deshuffling circuit and the external video signal are synthesized via this mask data.

[For production]

When playing back on a high-definition VTR and simultaneously inputting an external video signal, for example from a high-definition camera, to create a composite image with the playback signal, the playback signal from the tape is
A7'D conversion is performed in the SPS (Serial Parallel) circuit of the deshuffling circuit.
A serial input signal is converted into, for example, an 8-bit parallel signal by a 5-bit serial converter, which is input to a frame memory (or field memory) of a deshuffling circuit and written to an address designated by an address control circuit.

On the other hand, the external video signal from the camera is digitized by an A/D converter in the recording system of the VTR, which is not used during playback, and is input to the shift register and mask data creation circuit of the external signal input synthesis device. In the shift register, the serial video signal is converted into, for example, an 8-bit parallel video signal, and the converted signal is written into a newly provided compositing frame memory (or field memory).

In the mask data creation circuit, the presence or absence of a video signal is expressed as 1 or 0 for the input external video signal data, and the result is written in the mask data memory.

After writing one frame (or field) as described above, the frame memory at the address specified by the address control circuit of the deshuffling circuit (
The video signal of the compositing frame memory (or field memory) provided in the external signal input synthesis device, and the data of the mask data memory are read out and input to the compositing circuit.

In the synthesis circuit, the reproduced video signal is ANDed with data obtained by negating the mask data, the external video signal is ANDed with the mask data, and the respective outputs are ORed to generate a composite video signal. create. As a result, when the mask data is around 1, it becomes an external video signal, and when it is around 0, it becomes a reproduced video signal. A synchronization addition signal read out from the synchronization addition ROM of the deshuffling circuit is added to the synthesized video signal, and the SPS converter of the deshuffling circuit converts the parallel signal into a serial signal and outputs the signal.

As mentioned above, the synthesis of the reproduced video signal and the external video signal is performed at the stage when the video is digitized, so the signal synthesis is performed reliably and each circuit can be easily connected to the IC.
It is possible to keep costs low.

〔Example〕

An embodiment of the present invention will be described below based on FIGS. 1 to 4.

In a high-definition VTR, for example, the rotational speed of the magnetic head is tripled compared to the conventional one to increase the relative speed between the tape and the magnetic head, and the video signal is converted to TCI (Tim).
e Compressed Integration
) to expand the time axis of the luminance signal and narrow the band of the recording signal. In such cases, the high-definition signal is digitized, and one frame (one field) of high-definition video is rationalized into multiple tracks to prevent head switching noise from appearing on the screen and to make the screen visible during high-speed searches. It is equipped with a shuffling circuit for dividing and arranging the signals for recording, and a deshuffling circuit for restoring the divided and arranging recording signals back to the original high-definition video during playback.

FIG. 4 shows a schematic configuration of the VTR as described above. In the case of recording, the input video signal is sent to the A/D converter 3.
After being shuffled by a shuffling circuit (also used as a deshuffling circuit, hereinafter referred to as a shuffling/deshuffling circuit) 32, which is composed of two sets of memory boards 33 and 34 having the same configuration, the D/ It is converted into analog again by the A converter 35 and sent to the FM modulator 3.
6, is amplified by a recording amplifier 37, and is recorded on a chip 139 via a magnetic head 38.

During playback, the signal recorded on the tape 39 is amplified by the playback amplifier 4o via the magnetic head 38, and then demodulated by the FM demodulator 42 via the equalizer 41.
(Time Ba5e Corrector) 43
At the same time, the signal is A/D converted and time axis corrected at the shuffling/deshuffling circuit 32, restored to the original high-visicon signal arrangement, and then sent to the D/A converter 44.
The signal is converted into an analog signal, amplified by an output amplifier 45, and outputted.

During playback of such a high-definition VTR, an external signal input synthesis device is required to combine, for example, the output from a high-definition camera with a playback signal from a tape.

The external signal synthesis circuits 2 and 3 forming the external signal input synthesis apparatus (hereinafter referred to as synthesis apparatus) shown in FIG. 1 have the same configuration and perform the same operation in frame alternation.

The external video signal output from the high-definition camera 46 is connected to the input side of the A/D converter 31, which is not used during playback, and the output side of the A/D converter 31 is connected to the playback side contact 47a of the recording/playback switch 47. It is connected to the input side of the synthesis input switch 4, and the output side of the synthesis input switch 4 is connected to the shift registers 2a and 3a of the external signal synthesis circuits 2 and 3.
and are connected to the input sides of the mask data creation circuits 2b and 3b.
).

The output side of the shift register 2a is connected to the input terminal of the synthesis frame memory (or field memory, hereinafter referred to as frame memory) bit 2c, and the output side of the synthesis frame memory bit 2C is connected to the input terminal of the synthesis circuit 2d. It is connected to the. On the other hand, the output side of the mask data creation circuit 2b is connected to the input side of the mask data memory 2e,
The output side of the mask data memory 2e is connected to the input side of the synthesis circuit 2d. Note that the external signal synthesis circuit 2 is provided with an address generator 2f, and its output side is as follows.
It is connected to the input sides of the synthesis frame memory 2c and the mask data memory 2e.

On the other hand, the output side of the TBC 43 of the VTR playback system is connected to the input side of the input switch 48, and the output side of the input switch 48 is connected to the two sets of memory boards 33 and 33 forming the shuffling/deshuffling circuit 32, respectively. (Since the memory boards 33 and 34 forming the shuffling/deshuffling circuit have the same structure, only the memory board 33 will be described below).

One memory board 33 of the shuffling/deshuffling circuit 32 is provided with an address control circuit 33'b and a frame memory 133c, and the output side of the address control circuit 33b is connected to the input side of the frame memory l33c, SP, It is connected to the input side of the converter 33a. The output side of the synthesis circuit 2d of the external signal synthesis circuit 2 is also connected to the input side of this SPS converter 33a. Further, the frame memory 133c includes S
It is connected to the PS converter 33 a and the synthesis circuit 2 d of the external signal synthesis circuit 2 , and the output side of the SPS converter 33 a is connected to the input side of the output switch 49 .

In the VTR having the synthesizer 2 and the shuffling/deshuffling circuit 32 configured as described above, when a playback signal is synthesized with an external signal from a high-definition camera or the like during playback, the signal is played back from the tape 39 via the magnetic head 38. The reproduced video signal is amplified by a reproduction amplifier 40, passed through an equalizer 41, and demodulated by a demodulator 42.
It is A/D converted in the TBC 43, time axis corrected at the same time, inputted to the input switch 48, and each memory board 33 and 34 of the shuffling/deshuffling circuit 32.
The signal is switched and added to the SPS converters 33a and 34a every frame. For example, in the memory board 33, one frame of signals is serially input to the SPS converter 33a, but this is converted into, for example, 8-bit parallel signals, and the atlus control circuit 3
The video signal is written to the address of frame memory +33c specified by 3b.

On the other hand, the external signal from the camera 46 is digitized by the A'/D converter 31 of the recording system, which is not used during playback, and is sent to the synthesizer 1 by the synthesis input switch 4 via the recording/playback switch 47. The signals are alternately switched and input to the external signal synthesis circuits 2 and 3 for each frame. Regarding the external signal synthesis circuit 2, the external video signal is input to a shift register 2a and a mask data creation circuit 2b. In the shift register 2a, the input serial external signal data is converted into, for example, an 8-bit parallel signal, and written into the synthesis frame memory bit 2C at an address designated by the address generator 2f. Also,
The mask data creation circuit 2b, as shown in FIG.
The configuration consists of an R circuit 2b+ and a shift register 2bz, and the presence/absence of a video signal is determined by 1 for external video signal data.
Or it is expressed as 0, converted into an 8-bit parallel signal by the shift register 2bz, and written into the mask data memory 2e at the address designated by the address generator 2f.

As described above, after writing of the reproduced video signal for one frame, three external video signals, and the mask data of the external video signal is completed, reading is performed to create a composite signal.

Address control circuit 3.3b of memory board 33
The reproduced video signal in the frame memory 133c at the address specified by the address generator 2f, the external video signal in the synthesis frame memory 2c in the external signal synthesis circuit 2 at the address specified by the address generator 2f, and the data in the mask data memory 2e. are read out and input to the synthesis circuit 2d of the external signal synthesis circuit 2. The synthesis circuit 2d has a configuration as shown in FIG. That is, on the input side of the NOT circuit 2d+,
The output side of the mask data memory 2e is connected, and the output side is connected to one input side of the AND circuit 2dz.
The output side of the frame memory T 33 c of the memory board 33 is connected to the other input side of the ND circuit 2d2. The output side of the above ANr) circuit 2dz is the OR circuit 2d.
The output side of the AND circuit 2d4 is connected to the other input side of the OR circuit 2ds, and the output side of the OR circuit 2d34 is connected to the input side of the SPS converter 33a of the memory board 33. has been done.

Further, the input side of the AND circuit 2d4 is connected to the output side of the mask data memory 2e and the synthesis frame memory 2C of the external signal synthesis circuit 2.

In the synthesis circuit 2d having the above configuration, the reproduced video signal from the frame memory 133c of the memory board 33 and the mask data from the mask data memory 2e of the external signal synthesis circuit 2 are connected to the NOT circuit 2d.

An AND circuit 2dz performs a logical product with the data negated in , and an AND circuit 2da outputs the external video signal from the synthesis frame memory 2C of the external signal synthesis circuit 2 and the mask data memory 2e. The mask data are ANDed, and the respective outputs of the AND circuits 2dz and 2d are added to the OR circuit 2ds to perform a logical sum. When the mask data is 1, the reproduced video signal is set to 0, the external signal is set to 1, and the external video signal is output. Conversely, when the mask data is 0, a reproduced video signal is output.

5. In the case of such reading, the synchronization (] addition signal is read out from the synchronization addition ROM of the synchronization addition circuit (not shown) and added to the SPS converter 33 of the memory board 33.
a, the parallel signal is converted into a serial signal, and the signal is output.

Furthermore, as described in item 1, when signals are being read from the external signal synthesis circuit 2 and memory board 33, signals are being written to one of the external signal synthesis circuits 3 and memory board 34. Therefore, reading and writing are performed in frame alternation.

As described above, in the present invention, when digitized video signals are combined, they are accurately synthesized on a 1-bit basis, so an extremely accurate composite image can be obtained.

〔Effect of the invention〕

As described above, the VTR external signal input synthesis device according to the present invention digitizes the video signal to be recorded and divides one field into multiple recording tracks in order to synthesize the reproduced video signal and the external video signal. In an external signal input synthesis device for a VTR having a shuffling circuit and a deshuffling circuit for recombining the divided and arranged video signals into the original one field signal, during playback, The A/D converter in the recording system digitizes the external video signal and stores it in a newly created frame memory or field memory, while also creating mask data based on the presence or absence of the external video signal and using this mask data to digitize the external video signal. The configuration is such that the reproduced video signal from the deshuffling circuit and the external video signal are combined.

As a result, the synthesis of external video signals is performed at the digital stage, and moreover, one
Precise synthesis is performed through mask data that creates bit-by-bit accurate data. In addition, not only can existing A/D converters and deshuffling circuits be used, but also newly required circuits can be easily obtained or integrated into ICs, which has the effect of suppressing the overall cost increase of VTRs. .

7

[Brief explanation of drawings]

1 to 4 show one embodiment of the present invention. FIG. 1 is a block diagram showing the configuration of an external signal input synthesis device. FIG. 2 is a block diagram showing the configuration of the mask data creation circuit. FIG. 3 is a block diagram showing the configuration of the synthesis circuit. FIG. 4 is a block diagram of a high-definition VTR. FIG. 5 shows a conventional example, and is a schematic block diagram of a synthesis circuit that synthesizes an external signal and a reproduced signal. 2 is an external signal input synthesis device, 2 and 3 are external signal synthesis circuits, 2a and 3a are shift registers, 2b and 3b are mask data creation circuits, 32 is a shuffling/deshuffling circuit, and 33 and 34 are memory boards. 8

Claims (1)

[Claims] 1. A shaft that digitizes the video signal to be recorded, divides and arranges one field into a plurality of recording tracks, and synthesizes the video signals divided and arranged into the plurality of recording tracks again into the original one field signal. In a VTR external signal input synthesis device having a ring circuit and a deshuffling circuit, during playback, the external video signal is digitized by an A/D converter in the recording system, and is also stored in a newly provided frame memory or field memory. A VTR, characterized in that it is configured to create mask data based on the presence or absence of an external video signal, and to synthesize the reproduced video signal from a deshuffling circuit and the external video signal via this mask data. External signal input synthesis device.