JPH03110859U

JPH03110859U -

Info

Publication number: JPH03110859U
Application number: JP1907890U
Authority: JP
Priority date: 1990-02-27
Filing date: 1990-02-27
Publication date: 1991-11-13

Description

[Brief explanation of the drawing]

第１図は本考案の実施例を示す回路図、第２図
は第１図に示された回路を構成した半導体集積回
路の平面図、第３図は従来例を示す回路図である
。１……回路ブロツク、２……Ｄ−ＦＦ、３……
クロツク発生回路、４……バツフア、５……信号
線、６……接続線。 FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a plan view of a semiconductor integrated circuit constituting the circuit shown in FIG. 1, and FIG. 3 is a circuit diagram showing a conventional example. 1...Circuit block, 2...D-FF, 3...
Clock generation circuit, 4...Buffer, 5...Signal line, 6...Connection line.

Claims

[Claims for Utility Model Registration] A plurality of circuit blocks incorporating a plurality of circuits that process input signals based on a reference clock signal; a clock generation circuit that generates the clock signal; and a clock generation circuit that generates the clock signal from the clock generation circuit. A plurality of clock signal lines that independently supply the clock signal to each of the plurality of circuit blocks, and a low resistance connection line that connects the ends of each of the plurality of clock signal lines, and a connection line between each of the circuit blocks. A semiconductor integrated circuit characterized by preventing deviations in clock signals.