JPH03110847A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPH03110847A JPH03110847A JP24979789A JP24979789A JPH03110847A JP H03110847 A JPH03110847 A JP H03110847A JP 24979789 A JP24979789 A JP 24979789A JP 24979789 A JP24979789 A JP 24979789A JP H03110847 A JPH03110847 A JP H03110847A
- Authority
- JP
- Japan
- Prior art keywords
- power
- wiring
- power supply
- integrated circuit
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 239000004020 conductor Substances 0.000 claims abstract description 11
- 238000010586 diagram Methods 0.000 description 6
- 238000002955 isolation Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、情報処理装置等に用いられる半導体集積回路
に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit used in information processing devices and the like.
半導体集積回路は、半導体基板表面付近に形成した、ト
ランジスタ、抵抗等の素子間を、Ａ４等の配線材料で接
続して、所望の回路を形成する。In a semiconductor integrated circuit, a desired circuit is formed by connecting elements such as transistors and resistors formed near the surface of a semiconductor substrate using a wiring material such as A4.
従来の半導体集積回路では、第４図に示す様に、回路へ
電源を供給する電源配線と、回路の入出力配線すなわち
信号配線とが同一配線層で形成されていた。In a conventional semiconductor integrated circuit, as shown in FIG. 4, a power supply wiring for supplying power to the circuit and an input/output wiring of the circuit, that is, a signal wiring, are formed in the same wiring layer.
第５図に、第３図のＢ−Ｂ’間の断面図を示す。FIG. 5 shows a sectional view taken along line B-B' in FIG. 3.
また第５図のトレンチ５１．５２の様に、トレンチは素
子分離用として用いられていた。Further, trenches, such as trenches 51 and 52 in FIG. 5, were used for element isolation.
上述した従来の半導体集積回路では、電源配線と信号配
線とが同じ配線層に形成されるので、信号配線領域が電
源配線の分だけ減少してしまうという欠点があった。In the conventional semiconductor integrated circuit described above, since the power supply wiring and the signal wiring are formed in the same wiring layer, there is a drawback that the signal wiring area is reduced by the amount of the power supply wiring.
本発明の半導体集積回路は、導電体を埋め込んだトレン
チを電源配線として使用することにより、電源配線によ
る信号配線領域の減少をなくしている。トレンチに埋め
込む導電体としては、たとえばリン、ボロン等をドーピ
ングしたポリシリコン、 ＣＶ Ｄ （ｃｈｅｍｉｃａ
ｌ ｖａｐｏｒ ｄｅｐｏｓ山ｏｎ）アルミ等がある。The semiconductor integrated circuit of the present invention eliminates the reduction in signal wiring area due to the power supply wiring by using a trench filled with a conductor as the power supply wiring. As the conductor to be buried in the trench, for example, polysilicon doped with phosphorus, boron, etc., CVD (chemical
l vapor depos (mountain on) aluminum, etc.
第１図は本発明の一実施例であり、第３図のエミッタホ
ロワ回路を半導体集積回路で実現している。第２図は、
第１図のＡ−Ａ′間の断面を示す図である。第２図に示
す様に、導電体を埋め込んだトレンチ２１をＧＮＤ電源
配線として用いトランジスタのコレクタ電極にＧＮＤ電
源を供給し、導電体を埋め込んだトレンチ２２をＶＥＥ
電源配線として用い抵抗の一方の端子にＶＥＥ電源を供
給している。この様に、導電体を埋め込んだトレンチを
電源配線として用いることにより、信号配線と同じ層に
電源配線を持つ必要がなくなり信号配線領域の減少がな
くなる。なお、トレンチ２３゜２４は、トランジスタの
素子分離用に用いられているトレンチである。FIG. 1 shows an embodiment of the present invention, in which the emitter follower circuit shown in FIG. 3 is realized by a semiconductor integrated circuit. Figure 2 shows
2 is a diagram showing a cross section taken along line A-A' in FIG. 1. FIG. As shown in FIG. 2, a trench 21 filled with a conductor is used as a GND power supply wiring to supply GND power to the collector electrode of the transistor, and a trench 22 filled with a conductor is used as a GND power wiring.
It is used as a power supply wiring to supply VEE power to one terminal of the resistor. In this way, by using a trench filled with a conductor as a power supply wiring, it is not necessary to have a power supply wiring in the same layer as the signal wiring, and there is no reduction in the signal wiring area. Note that the trenches 23 and 24 are trenches used for element isolation of transistors.
以上説明した様に本発明は、導電体を埋め込んだトレン
チを電源配線として用いることにより、電源配線による
信号配線の減少がなくなるという効果がある。As described above, the present invention has the advantage that by using a trench filled with a conductor as a power supply wiring, there is no reduction in signal wiring due to the power supply wiring.
４、4,
第１図は本発明の一実施例を表わす図、第２図は、第１
図の断面を示す図、第３図はエミッタホロワ回路を表わ
す図、第４図は従来技術を表わす図、第５図は第４図の
断面を示す図である。
２１、 ２２． ２３． ２４． ５１．
５２ ・・・・・・ ト レンチ。FIG. 1 is a diagram showing one embodiment of the present invention, and FIG. 2 is a diagram showing one embodiment of the present invention.
3 is a diagram showing an emitter follower circuit, FIG. 4 is a diagram showing a conventional technique, and FIG. 5 is a diagram showing a cross section of FIG. 4. 21, 22. 23. 24. 51.
52... Trench.
Claims (1)
とを特徴とする半導体集積回路。A semiconductor integrated circuit characterized by using a trench filled with a conductor as a power supply wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24979789A JPH03110847A (en) | 1989-09-25 | 1989-09-25 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24979789A JPH03110847A (en) | 1989-09-25 | 1989-09-25 | Semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03110847A true JPH03110847A (en) | 1991-05-10 |
Family
ID=17198358
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24979789A Pending JPH03110847A (en) | 1989-09-25 | 1989-09-25 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03110847A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100342797B1 (en) * | 1996-08-20 | 2002-07-04 | 가나이 쓰도무 | Semiconductor and method for manufacturing the same |
-
1989
- 1989-09-25 JP JP24979789A patent/JPH03110847A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100342797B1 (en) * | 1996-08-20 | 2002-07-04 | 가나이 쓰도무 | Semiconductor and method for manufacturing the same |
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