JPH03108230A - Malfunction preventing circuit for latch relay - Google Patents

Abstract

PURPOSE:To prevent the malfunction of a latch relay caused by an abnormality of the power voltage by providing a means prohibiting the output from a logic circuit to a semiconductor element when a power voltage monitoring means detects the power abnormality of the logic circuit. CONSTITUTION:When the power source V1 of a logic circuit 10 is momentarily interrupted or the voltage drops to the preset voltage or below of a power voltage monitoring circuit 15, the output terminal 15a of the circuit 15 is made 'L', thus the base potential of transistors 14a and 14b is made the earth potential via a diode 16b or 17b and the circuit 15. Even if erroneous outputs appear at output terminals 10a and 10b of a logic circuit 10 due to the voltage drop or momentary interruption of the power source, latch relay 12 is not operated, and a switching contact 13 maintains the state before the power voltage is fluctuated.

Description

[Detailed Description of the Invention] [Summary] Regarding a malfunction prevention circuit for a latch relay driven by the output of a logic circuit, reliability is improved by preventing malfunction of the latch relay due to an abnormality in the power supply voltage of the logic circuit. The power supply voltage monitoring means is provided between the output terminal of the logic circuit and the semiconductor element for driving the latch relay, and the power supply voltage monitoring means detects an abnormality in the power supply voltage of the logic circuit. The device further comprises means for inhibiting output from the logic circuit to the semiconductor element when a power supply abnormality is detected.

[Industrial application field]

The present invention relates to a malfunction prevention circuit for latch relays used in communication equipment and other electrical equipment, and more particularly to a malfunction prevention circuit for latch relays driven by the output of a logic circuit.

[Conventional technology]

2. Description of the Related Art Conventionally, a circuit system having a circuit configuration shown in FIG. 3 is known as a circuit system that switches communication lines by driving a latch relay using the output of a logic circuit.

In FIG. 3, 10 is a logic circuit composed of TTL or CMO3, etc., and by determining the states of a plurality of input signals 11 applied to this logic circuit IO, a set output terminal 10a and a reset output terminal 1
"H" and "L" level output signals are sent from 0b. The logic circuit 10 also includes a power supply V for its operation,
is supplied.

12 is a latch relay, which includes a set coil 12a, a reset coil 12b, and these coils 12a.

It has a switching contact 13 that is switched by excitation of 12b,
One end of the set coil 12a and the reset coil 12b is connected to a drive power source v2, and the other end of the set coil 12a and the reset coil 12b is grounded via respective drive transistors 14a and 14b. Further, the base of the set coil driving transistor 14a is connected to the setting output terminal 10a of the logic circuit 10, and the base of the reset coil driving transistor 14b is connected to the reset output terminal 10b of the logic circuit 10.

The common terminal 13c of the switching contact 13 of the latch relay 12 is connected to the communication line C, and the A line and 8 lines are connected to the contacts 13a and 13b, respectively.

In the circuit system configured as described above, when the input signal 11 is applied to the logic circuit 10, the logic circuit 10 judges the state of the input signal 11 and outputs the output terminal 10.
The output states of a and 10b are set to "H11" or "L".

Here, when the output terminal 10a is set to "H" and the output terminal 10b is set to "'L", the transistor 14a is turned on.
The set coil 12a of the latch relay 12 connected thereto is energized. For this reason, the switching contact 13 is
Switch to a, connect communication circuit C to line A, and
Maintain this state.

Further, when the output terminal 10a of the logic circuit 10 is set to "L" and the output terminal 10b is set to "H" depending on the state of the input signal 11, the transistor 14b is turned on, and the reset coil 12b of the latch relay 12 is turned on. Excite. Therefore, the switching contact 13 is switched to the contact 13b side, and the communication line C is connected to eight lines.

[Problem to be solved by the invention]

By the way, in the conventional logic circuit as described above, there is no problem if the operating power supply v1 is normal and stable, but in many cases, the power supply v1 fluctuates and may be interrupted momentarily. . In this way, if the power supply V is interrupted momentarily or becomes lower than the voltage that allows the logic circuit to operate normally, the output of the logic circuit 1O becomes unstable, and the latch relay 12 is erroneously set or reset, causing a malfunction. There was a problem.

The present invention has been made in view of the above points, and an object of the present invention is to provide a highly reliable latch relay malfunction prevention circuit that prevents malfunctions of latch relays due to drops in power supply voltage and instantaneous power interruptions. shall be.

[Means to solve the problem]

A malfunction prevention circuit for a latch relay according to the present invention is a circuit that controls a semiconductor element using the output of a logic circuit to drive the latch relay, and includes a power supply voltage monitoring means for detecting an abnormality in the power supply voltage of the logic circuit. comprising means provided between an output terminal of the logic circuit and the semiconductor element for driving the latch relay and inhibiting output from the logic circuit to the semiconductor element when the power supply voltage monitoring means detects a power supply abnormality of the logic circuit. It is what it is.

[For production]

When the power supply voltage monitoring means detects that the power supply voltage of the logic circuit has become abnormal, it operates the inhibiting means to inhibit the output from the logic circuit to the semiconductor element for driving the latch relay. Even if an output is produced, this is prevented from being applied to the latch relay driving semiconductor element.

Therefore, in the present invention, malfunction of the latch relay is prevented, and a highly reliable switching circuit using the latch relay is realized.

〔Example〕

Embodiments of the present invention will be described below based on the drawings.

FIG. 1 is a block diagram showing an embodiment of a latch relay malfunction prevention circuit according to the present invention.

In FIG. 1, a logic circuit 10 outputs an output signal for controlling a latch relay 12 to its output terminals 10a and 10b by determining the state of an input signal 11 input thereto, as in the conventional case. In addition, latch relay 12
An AND gate 16 is connected in series to the base of the transistor 14a that drives the set coil 12a of the logic circuit 10. ,
Furthermore, a logic circuit 1 is connected to the base of the transistor 14b that drives the reset coil 12b of the latch relay 12.
0 output terminal 10b and the output from the power supply voltage monitoring circuit 15 are connected in series.

The AND gates 16 and 17 prohibit the output from the logic circuit 10 to the latch relay 12 when the power supply V1 of the logic circuit 10 is abnormal, and connect the cathode side to the output terminal 1.
0a or 10b and a pair of diodes 16a, 16b, and 17a connected to the output side of the power supply voltage monitoring circuit 15.
, 17b, and pull-up resistors 16c and 17c that pull up the anode sides of these diodes to the power supply voltage (1).

The power supply voltage monitoring circuit 15 of the logic circuit 10 has a second
As shown in the figure, when the voltage of the power supply VI is below the set voltage, its output terminal 15a becomes 1"L' (earth potential), and when it is above the set voltage, its output terminal 15a becomes °l Hl"
(Power supply voltage ■I).

In addition, the latch relay 12 has a switching contact 13 as in the conventional case.
The common terminal 13c is connected to the communication line C, and the A line and 8 lines are connected to each contact 13a and 13b, respectively.

Next, the operation will be explained.

If the power supply (2) of the logic circuit 10 is normal and its voltage is higher than the set voltage of the power supply voltage monitoring circuit 15, the output terminal 15a of the power supply voltage monitoring circuit 15 outputs "l Hl". Therefore, as a result of the logic circuit 10 determining the state of the input signal 11, when a "'H°' output appears at its output terminal 10a and an "L" output appears at its output terminal 10b, the AN
Since both the two-man power of D gate 16 become “°H°”, A
The output of the ND game) 16 becomes 'H' (corresponding to the power supply voltage ■3).

As a result, the transistor 14a turns ONL, and by exciting the set coil 12a, the switching contact 13 is switched to the contact 13.
a, and connect line A to communication line C. At this time, since the input terminal of the AND gate 17 on the logic circuit 10 side is at the "'L" level, the AND gate 17
The output of is held at "IIL".

Further, when the output of the logic circuit 10 changes to "°°L" at the output terminal 10a and "H" at the output terminal 10b depending on the input conditions, the output of the AND gate 17 becomes "H" and the transistor 14b turns on. . Therefore, the reset coil 12b is excited, and the switching contact 13 is switched to the contact 13b.

On the other hand, if the power supply v1 of the logic circuit 10 is interrupted momentarily or its voltage drops below the set voltage of the power supply voltage monitoring circuit 15, the output terminal 1 of the power supply voltage monitoring circuit 15
5a becomes "L", the base potential of the transistors 14a and 14b goes through the diode 16b or 17b and the power supply voltage monitoring circuit 15 regardless of whether the input on the logic circuit 10 side of the AND gate 16.17 is "H" or II Ln. Therefore, even if an erroneous output appears at the output terminals 10a, 10'b of the logic circuit 10 due to a drop in power supply voltage or a momentary power interruption, the latch relay 12 does not operate, and the switching contact 13 maintains its state before the power supply voltage fluctuates.

That is, malfunction of the latch relay 12 can be prevented.

Note that in the present invention, when the power supply of the logic circuit 10 becomes abnormal, the latch relay 12 is disconnected from the logic circuit 10.
The circuit that prohibits output to the circuit is not limited to the AND gate shown in the embodiment, but can also be configured by other logic circuits, switch circuits, or the like.

〔Effect of the invention〕

As explained above, according to the present invention, when the power supply voltage monitoring means detects that the power supply of the logic circuit is abnormal, the output from the logic circuit to the latch relay is prohibited. The power supply may be momentarily cut off, or
Alternatively, malfunction of the latch relay can be prevented even if the power supply voltage fluctuates, and a switching circuit using a stable and highly reliable latch relay can be realized.

FIG. 3 is a block diagram of a conventional latch relay.

Explanation of main symbols 10 is a logic circuit; 11 is an input signal; 12 is a latch relay 14a and 14b are transistors, 15 is a power supply voltage monitoring circuit; 16.17 is an AND gate (inhibition means).

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a latch relay malfunction prevention circuit according to the present invention. FIG. 2 is a characteristic diagram of the power supply voltage monitoring circuit in this embodiment. Figure 3 Figure 2

Claims (1)

[Claims] (1) In a circuit that controls a semiconductor element by an output of a logic circuit to drive a latch relay, a power supply voltage monitoring means for detecting an abnormality in the power supply voltage of the logic circuit, and an output terminal of the logic circuit and the latch relay drive. A malfunction prevention circuit for a latch relay, comprising means for prohibiting output from the logic circuit to the semiconductor element when the power supply voltage monitoring means is provided between the semiconductor elements for the logic circuit and detects a power supply abnormality in the logic circuit. .