JPH03107377A - Inverter - Google Patents

Abstract

PURPOSE:To minimize the amount of dead time by producing a control signal for turning either one of a first or second driver stage ON/OFF and holding the other thereby varying the magnitude of response current in the direction for decreasing the magnitude of difference. CONSTITUTION:An ON/OFF interval forming means 280 is connected to receive a selection signal. When the driver stage to be specified by a selection signal is switched from one to the other stage, both stages are held in OFF state for a predetermined interval from the time point of switching. For that purpose, a dead time setting means 2804 for generating a dead time signal indicating a predetermined interval is included and the ON/OFF interval forming means 280 is arranged such that the ON/OFF interval signal, represented by the dead time signal, shows an OFF interval. By such arrangement, the amount of dead time can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a single-phase or polyphase inverter suitable for use as an alternating current power source for a single-phase or polyphase inverter, and also for a single-phase or polyphase AC servo. This relates to phase inverters.

BACKGROUND ART Conventionally, a PWM type inverter has been used in an AC servo device that servo-controls an AC motor used in, for example, an FA. Such an inverter generally includes a PWM (pulse width modulation) control section that receives a target current waveform signal representing a target waveform of the current to be supplied to each coil of the AC motor, and a A driver that supplies the coil with a response current that follows the target current waveform.

There are roughly two types of control methods for the PWMI controller. The first type is an average current control method that compares the deviation between the target current and the response current with a reference triangular wave. The second type is disclosed in JP-A-59-14366 (Control method of pulse width modulation inverter) and JP-A-59-14366 (Pulse width modulation inverter control method).
This is a current control method that performs control as needed to keep the deviation within its allowable range, as disclosed in Japanese Patent No. 209076 (method for controlling a power converter). In either type, the pair of upper and lower switching elements that form the driver of each phase are controlled so that they are alternately turned on between the upper and lower sides, forming a configuration, and each of these on periods, that is, the reference period. The last part is allocated as a dead time to turn off both the upper and lower switching elements in order to prevent short circuits between the upper and lower switching elements.

Problems to be Solved In the conventional PWM control method as described above, since a dead time must be provided during each reference cycle time, the following problems occur.

The first problem is that the frequency of minute vibrations in the response current waveform due to alternate turn-on of the upper and lower switching elements, that is, the carrier frequency, is limited to a value considerably lower than the maximum switching frequency of the upper and lower switching elements themselves. For example, when a transistor is used as a switching element, the maximum switching frequency of the element is 4 to 5 KHz, but in order to provide dead time, the carrier frequency of the response current is usually 1/2 or less.
It is said to be around KHz. The upper limit of this carrier frequency is the main factor that determines the upper limit of the follow-up speed of the response current to the target current.

Furthermore, this 2 KHz frequency falls within the range of audible sound frequencies that is easy to hear, and therefore poses a problem in terms of noise reduction.

As a second problem, since there is such an upper limit limit on the carrier frequency, in the above-mentioned second type of control method that determines the allowable range of deviation of the response current from the target current,
There will also be restrictions on narrowing the allowable range.

As a result, in the servo system, there is a limit to reducing the magnitude of the deviation between the actual rotor position of the servo motor and its designated position.

As a third problem, due to the narrow limit of the allowable deviation range, there is also a limit to reducing the amplitude of minute vibrations in the carrier frequency of the response current. This is an obstacle to smooth control of the motor.

The fourth problem is that switching between the upper and lower switching elements is always performed at a carrier frequency that is considerably higher than the frequency of the target current waveform, so when the carrier frequency is increased, a situation close to a short circuit may occur between the switching elements. This means that the quality of the product increases. Therefore, there is a drawback that stress on the switching element increases and safety decreases.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide an inverter that minimizes the amount of dead time during a unit period of a target current waveform.

Means and Action for Solving the Problems In order to achieve the above object, the inverter of the present invention generates a response current that follows the waveform of a target current from a DC power supply, and includes: (a) for supplying the response current to a load; driver means having an output terminal, the driver means each being controllable on/off, a first driver stage connected between a first DC power supply terminal and said output terminal; a second driver stage connected between an output terminal and a second DC power supply terminal; It is connected to receive a signal indicating a waveform,
c) deviation detection means for detecting the magnitude of the deviation between the target current and the response current and generating a deviation signal representing the deviation; A driver that changes the magnitude of the response current in a direction that reduces the magnitude of the deviation by generating a control signal that turns on/off one of the driver stages and meanwhile holds the other driver stage off. A drive control means.

In an inverter with such a configuration, the number of states in which the first, l, and second driver stages are alternately turned on is reduced, thereby reducing the number of states in which dead time must be provided.

According to the present invention, the driver drive control means controls the first and second waveform signals during a first period in which the amplitude of the target current waveform signal is greater than a reference value indicating one point within the amplitude change range.
one of the driver stages is turned on/off while the other driver stage is held off, and the other driver stage is turned on/off during a second period in which the amplitude of the target current waveform signal is not greater than the reference value. on/off while holding said one driver stage off. In this case, the reference value may be zero.

This makes it unnecessary to provide a dead time except when the amplitude of the reference value is crossed.

Further, according to the present invention, the driver drive control means includes:
When the magnitude of the deviation is outside a predetermined tolerance range, the magnitude of the response current may be changed in a direction such that the magnitude of the deviation is within the predetermined tolerance range. .

In this case, the driver drive control means includes (a) deviation tolerance range setting means for generating a tolerance range signal indicating the tolerance range of the magnitude of the deviation, and (b) receiving the deviation signal and the tolerance range signal. c) an out-of-range detection means connected to receive the out-of-range signal and generating an out-of-range signal indicative when the magnitude of the deviation is outside the allowable range; response current increase/decrease period forming means for generating an increase/decrease period signal determining a period of increase or decrease of the response current required to bring the magnitude of the deviation within the tolerance range in response to the out-of-range signal; )
driver stage on/off control means connected to receive the increase/decrease period signal and controlling on and off of the first driver stage and the second driver stage based on the increase/decrease period signal; , a) an on/off period signal connected to receive the increase/decrease period signal and responsive to the increase/decrease period signal to generate an on/off period signal indicative of the on/off period of the first and second driver stages; off period forming means; b) specifying said one driver stage to be energized during said first period and specifying said other driver stage to be energized during said second period; C) energized driver stage selection means for generating a selection signal; and C) said first and second driver stages connected to receive said on/off period signal and said selection signal and designated by said selection signal. driver stage on/off control means, comprising: control signal generating means for generating a control signal for turning on/off one of the driver stages corresponding to the on/off period and keeping the other driver stage off; I can help you prepare for it.

Furthermore, the on/off period forming means is connected to a) receive the selection signal, and the driver stage specified by the selection signal is switched from one of the first and second driver stages to the other. dead time setting means for generating a dead time signal indicative of the predetermined period in order to hold both the first and second driver stages off for a predetermined period from the time of the change, The on/off period forming means may cause the on/off period signal to indicate off during the predetermined period represented by the dead time signal.

This reduces the amount of dead time in the current control scheme that defines the allowable range of deviation.

Furthermore, the deviation tolerance range setting means is connected to (a) receive the deviation signal and an upper limit value that determines the upper limit of the tolerance range, and when the amplitude of the deviation signal becomes higher than the upper limit value; a first comparison means for generating an upper limit exceedance signal when the amplitude exceeds the upper limit; a) second comparison means that generates a lower limit excess signal when the current exceeds the upper limit signal; a first increase/decrease period signal that assumes one of two states in response to the upper limit exceeded signal and assumes the other state in response to the lower limit exceeds signal; a second increase/decrease period signal;

At this time, the on/off period forming means comprises a) a tarlock generating means for generating a clock signal of a predetermined frequency for limiting the frequency of switching between the on period and the off period; 1 increment/decrease period signal and the clock signal, the first increment/decrement period signal transitioning between two states in response to the first increment/decrement period signal only when the clock signal is present. c) a first flip-flop for generating a first on/off period signal for the driver stage; c) connected to receive the second increase/decrease period signal and the clock signal; a second flip-flop transitioning between two states in response to the second increase/decrease period signal to generate a second on/off period signal for the second driver stage only when present; can be made to include.

With this configuration, the on/off switching frequency is kept below a predetermined frequency and is limited so as not to become excessively fast.

Furthermore, the control signal generating means is configured to: (a)
is connected to receive an off period signal and the selection signal, and when the selection signal specifies the first driver stage, the first on/off period signal is passed to the first driver stage. first gating means for generating said control signal; and second gating means for passing the second on/off period signal to generate a second of the control signal when the control signal is on.

Further, according to the present invention, in order to generate a multiphase response current that follows the waveform of a multiphase target current, a multiphase inverter using the above-mentioned inverter can be configured for each phase.

Embodiment Next, a preferred embodiment of the inverter according to the present invention will be described below.

FIG. 1 shows a PWM control circuit A used in a single-phase inverter or each phase of a multi-phase inverter. still,
The lower part of FIG. 1 shows a driver 7 with a pair of an upper driver stage 3 for feeding current into the load 1 of each phase thereof and a lower driver stage 5 for drawing current therefrom. The overall function of this circuit A is to connect a pair of output terminals 6 to a signal F1 indicating the waveform of the target current received at the input terminal 2 and a signal Fl indicating the waveform of the response current received at the input terminal 4.
and 8 an on/off control signal CU for the upper driver stage 3.
and generating an on/off control signal CL for the lower driver stage 5.

Functionally, this PWM control circuit A can be roughly divided into two types.
It consists of two parts, namely, a deviation detection section 10 and a driver drive control section 20 following it. The detection unit 10 includes a differential amplifier 12, which has input terminals 2.
4 target current and response current waveform signals ■ and Fl (second
(A)) is connected to the non-inverting input terminal and the inverting input terminal via a resistor. Differential amplifier 12
outputs a deviation signal a (FIG. 2 (b)) representing the deviation of the signals ① and Fl to its output terminal.

This signal a is FI! It is negative when greater than FI! It is positive when it is smaller.

Functionally, the driver drive control section 20 receiving this deviation signal a further includes a deviation tolerance range setting section 22, an out-of-range detection section 24, a response current increase/decrease period forming section 26, and a one-sided continuous on/off switch. Driver stage on /
It is divided into an off control section 28 and an off control section 28. Tolerance range setting section 2
2 is an upper limit voltage VH indicating the upper limit of the allowable range of the deviation signal a level (this is the lower limit of the allowable range of the response current), and a lower limit voltage VL indicating the lower limit of the allowable deviation range (the upper limit of the allowable response current range). It is determined by a potentiometer (not shown) or the like. The next out-of-range detection section 24 consists of a pair of upper limit comparator 240 and lower limit comparator 242. The upper limit comparator 240 receives the deviation signal a and the upper limit voltage VH at its inverting and non-inverting input terminals, and has its output terminal receiving a signal when the voltage level of the signal a is higher than VH. On the other hand, the lower limit comparator 242 receives VH and the signal a at its inverting and non-inverting input terminals, and outputs the signal a at its output terminal. Lower limit excess signal LL that becomes low when the voltage level of signal a becomes lower than VL (Fig. 2 (c)
) occurs.

Response current increase/decrease period forming unit 26 receiving these comparator outputs
consists of one R-S flip 70 tube (F/F) 260. This F/F 260 has an upper limit excess signal U
The inverted signal LL (signal indicating that the lower limit of the allowable response current range has been exceeded) is received at the P terminal, and the inverted version of the lower limit excess signal LL (signal that indicates the upper limit of the allowable response current range) is received at the CL terminal. It is connected to the. As output, F/F2
60 has an increase/decrease period signal TI (second
Figure (d)), T2 is generated. Signal TI is set high by a low signal UL to define an increase period IP during which the response current should increase, and reset low by a low signal LL to define a decrease period DP during which the response current is to decrease. .

Signal T2 is the inverted version of signal T1.

The driver stage on/off control section 28 receiving these increase/decrease period signals Tl and T2 is functionally composed of an on/off period forming section 280, an energizing driver stage selection section 282, and a control signal generation section 284. It has become. First, the on/off period forming section 280 includes a pair of D-type flip-flops 2
800.2802, and a dead time setting section 2804 consisting of a series of circuits. F/F 2800 is
The D terminal receives the signal T1, the CK terminal receives the reference frequency clock CLK (Fig. 2 (E)), and the reset terminal receives the dead time output pulse DT (described later) from the dead time setting section 2804. The signal is received through gate 2806. The frequency of the clock CLK determines the upper limit of the on/off switching frequency of the driver stage 35, thereby preventing its switching frequency from becoming too high and causing destruction of the switching elements of the driver stage. do it like this. The F/F 2800 generates at its Q output terminal a first on/off period signal 01 that defines the on/off timing for the upper driver stage 3, and this signal is applied during periods when the input at the reset terminal is low. As shown in FIG. 2(f), the increase/decrease period signal T1 goes low at the first clock after going low to define an off period, and goes high at the first clock after the signal TI goes high. to determine the on period. The second on/off period signal 02 for the lower driver stage 5 at the Q output terminal of F/F 2802 is the inverse of signal 01, which depends on the direction of increase and decrease of the response current and the turn-on of the driver stage. This is because the relationship between OFF and OFF is opposite between the upper driver stage 3 and the lower driver stage 5. These on/off period signals define the carrier frequency of the response current.

First, the energizing driver stage selection unit 282 included in the control unit 28 will be explained. The upper range is divided into two by the upper driver stage 3, which acts to increase the response current when it is on, and the lower range is divided into two parts by the lower driver stage 5, which acts to decrease the response current when it is on. It is assigned to Therefore, in this example, the selection unit outputs the MSB (Fig. 4) of the digital waveform data that is the basis for forming the analog target current waveform signal, that is, a signal indicating the sign of the waveform. This designates upper driver stage 3 when the MSB is high, and designates lower driver stage 5 when it is low.

To explain the formation section 280 again, the selection section 282
Dead time setting to receive that MSB from ff128
04 is a dead time td of a predetermined length from that point when the MSB transitions from high to low or from low to high, that is, when the energizing driver stage is switched from the upper side to the lower side or from the lower side to the upper side. Between, F/F 28
00 and 2802 are reset to force the on/off period signals 01 and 02 to low to prevent short circuits between the upper and lower driver stages. Specifically, as shown in the figure, the setting unit 2804 includes an inverter 2808 that receives MSB input;
an antilog circuit 2810 that receives the output pulse IVI of this, and another inverter 2812 that receives the output cr of this;
EX-OR which receives the output pulse IV2 of this inverter and the MSB input and generates the dead time output pulse DT.
It consists of a gate 2814. The timing of these outputs is as shown in FIG. This dead time pulse DT is passed to the F/F 28 through a NOR gate 2806 which also receives a system reset RESET input.
00 and 2802 reset inputs.

Next, the control signal generation 5284 receiving the on/off period signals 01 and 02 and the MSB will be described. This generator 284 is for the signal 0, which is for the upper driver stage 3.
1 and the MSB, and an AND gate 2844 and a buffer 2846 that receives the inverted version of the signal 02 and the MSB from the inverter 2848, which is for the lower driver stage 5. . Both AND gates provide an emergency stop signal EMERGENCY to turn off both driver stages in an emergency.
(not related to the present invention). Therefore, as shown in the timing diagram for the example in which the target current waveform I is a sine wave in FIG. Outputs control signal CU. On the other hand, gate and buffer 284
4 and 2846 are the lower on/off control signal CL for the lower driver stage 5 through signal 02 when the MSB is low.
Output. FIG. 4 finally shows these control signals CU
3 shows an example of the waveform of the response current Fl supplied to the load by the pair of driver stages 3.5 controlled by the driver stages 3.5 and CL.

Next, the fifth section will discuss an AC servo equipment for a three-phase AC motor using the above-mentioned PWM control circuit A as an inverter.
This will be explained with reference to the figures. This servo device S is a 3-phase AC
The inverter 100 is equipped with a three-phase inverter 100 that supplies response current to the U-phase, ■-phase, and W-phase coils of the motor M, and this inverter 100 includes a driver section 110 and a PWM control section
, the base drive circuit 130, and a response current waveform signal FI that detects and represents the waveforms of the U-phase and W-phase response currents.
u, and a pair of detectors 140 that generate FIw.

The driver unit 110 includes three sets of drivers for the U phase,
80 volts) and the DC bus 152 (e.g. 20 volts), and their upper driver stages (U), (
V), (W) and lower driver stage (X), (Y), (Z)
Output terminal 112.1 connected to the coil of each phase between
14.116.

The PWM control unit 120 includes PWM control circuits A1, A2, and A3, such as the PWM control circuit A in FIG. 1, in the U phase, ■ phase, and W layers. These control circuits A1, A2, A3 are
A pair of control signals CU, CL in response to target current waveform signals Iu, Iv, Iw and response current waveform signals Flu, Fiw.
Three sets of on/off control signals such as CUu, CL
It outputs x, (Uv, CLy, and (Uw, CLz).

Incidentally, as is conventionally known, FIv is defined as Flv within circuit A2.
IuI! is synthesized from u and Flw, and Iv is also synthesized from IuI! in circuit A2. It is also possible to synthesize from l:Iw.

The other parts of the servo device S are conventionally equipped with a three-phase AC power supply 300, an AC-DC:+ inverter 400, and a protection circuit 500 for providing current protection and voltage protection. Furthermore, the device S receives the rotor position control signal and generates three digital signals representing a three-phase target sinusoidal current waveform.
A sine wave ROM 600 that generates a word and converts this digital word into analog target current waveform signals 1u, Iv, I
It also has a D/A converter 700 for converting into w.

In addition, in this servo device, the most significant bits of the above three digital words M S B u , M S B y ,
M S BW is provided to the corresponding PWM control circuit as the MSB shown in FIG.

The response current waveform shown in the lower part of FIG. 4 is an example of one obtained for a coil load such as a motor coil. In the case of this servo device S, while the lower driver stage (X) is off, when the upper driver stage (U) is on, as shown in FIG. The current flows from the bus 150 through the output terminal 112 to the U-phase coil, and when this stage (U) is off, the inductance of that coil tries to keep the current flowing, so the current flows through the diode of the lower stage (X). DC bus 15
2, the flyback current if will flow to the coil via the output terminal 112. This flyback current is
It gradually decreases during the stage (U) off period. In this way, a response current waveform as shown is obtained.

In one embodiment of the inverter of the present invention described above, the following changes are possible.

First, in the above embodiment, the period allocated to each driver stage is divided into two periods based on a certain amplitude of the target current, taking into account that the amplitude and waveform of the current to be supplied to the motor load vary greatly. It's Nishide. However, other two-division methods can also be adopted depending on the type of load and the characteristics of the response current to be supplied.

Second, in the above embodiment, the one-sided continuous on/off switching method was applied to the aforementioned second type of control method, but this technique was applied to the aforementioned first type of control method, that is, the average current control method. It can also be applied to

Third, as a switching element in the driver stage, it has a higher maximum switching side frequency than a transistor.
It is also possible to use other FETs.

Fourth, in the above embodiment, the allowable range is fixed, but it can be changed during operation if necessary.

FIG. 6 shows an example of an alternative circuit 10a of the deviation detecting section 10 of FIG. 1, which allows the tolerance range to be changed.

That is, this circuit includes a variable gain differential amplifier 12a that can set two different gains, and a positioning control section 14 that specifies one of the gains. Resistors RFI and RGI of amplifier 12a define a relatively low first gain (9 example = 40) for use when the controlled motor M is in operation, and resistors RF2 and RG2 define a relatively low first gain (9 = 40) for use when the motor is stopped. This defines a second, larger gain (eg, 80) to use. For example, the first and second gain ratios are two. The positioning control unit 14 generates a positioning completion signal PC which is the front end of the operating state of the controlled motor M and becomes high when the controlled motor M is in the stopped state. ,
Then, the analog switches SF2 and SG2 are directly controlled, and when the signal is high, the corresponding analog switches are turned on. As a result, when the current supplied to the motor changes from a large amplitude during operation to a small amplitude when stopped, the gain of the amplifier 12a is increased and the tolerance range defined by the subsequent circuit sections 22 and 24 is effectively narrowed. act to do so. by this,
Positioning accuracy when the motor is stopped can be improved.

Effects In the inverter of the present invention described above, the dead time ratio is reduced by the one-sided continuous on/off switching method, so the upper limit of the carrier frequency of the response current can be increased, and the tracking speed of the response current can be increased. can be raised. In addition, since the carrier frequency can be increased, when determining the allowable range of deviation, the range can be further narrowed, which allows a response current to be generated that more precisely follows the #l current, while also reducing motor noise. This allows for smoother control. In addition, the frequency of switching between the upper and lower drivers can be reduced to reduce the possibility of short circuits, thereby reducing stress on the driver elements.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing one embodiment of a PWM control circuit for an inverter according to the present invention. FIG. 2 is a diagram showing the timing of signals in the first half of the circuit of FIG. FIG. 3 is a diagram showing the timing of signals of the dead time setting section of FIG. 1. FIG. 4 is a diagram showing the timing of signals in the latter half of the circuit of FIG. 1. FIG. 5 is a circuit diagram showing an AC motor/servo device including an inverter using the PWM control circuit of FIG. 1. FIG. 6 is a circuit diagram showing an alternative circuit to the deviation detecting section 10 of FIG. 1, which makes it possible to change the tolerance range. C code explanation] A: PWM control circuit, 7: Driver, 10.10a:
Deviation detection section, 12a: Variable gain differential amplifier, 20: Driver drive control section, 22: Deviation tolerance range setting section 24: Out of range detection section, 26: Response current increase/decrease period forming section, 28: Driver stage on/off Control unit, 280: On/off period forming unit, 282: Energizing driver stage selection unit, 284: M valve signal generation unit, I: Target current waveform signal, FI: Response current waveform signal, S: AC motor servo device , M: AC-1-single layer, 100: 3-phase inverter,
llO: Driver section, 120: P WMM'iHN
+, 130: Base drive circuit, 140: Detector, 150, 152: DC/<S(
Outside 42) Fig. 2 Fig. 6 00 沫奢工 1 連 トame 4

Claims (1)

[Scope of Claims] 1. An inverter that generates a response current that follows the waveform of a target current from a DC power source, ii) a driver means having an output terminal for supplying the response current to a load, The driver means are each controllable on/off and include a first driver stage connected between a first DC power terminal and the output terminal, and a first driver stage connected between the output terminal and the second DC power terminal. and (b) a second driver stage connected between said driver means, said driver means being connected to receive a signal indicative of the waveform of said target current and a signal indicative of the waveform of said response current. c) deviation detecting means for detecting the magnitude of the deviation between the target current and the response current and generating a deviation signal representing the deviation; c) the deviation detecting means connected to receive the deviation signal; generating a control signal that turns on/off one of the first and second driver stages while holding the other driver stage off, increasing the magnitude of the response current in a direction that reduces the magnitude of the deviation; An inverter consisting of a driver drive control means for changing the . An inverter comprising: 2. In the inverter according to claim 1, the driver drive control means is configured such that the amplitude of the target current waveform signal is 1 within the amplitude change range.
turning one of the first and second driver stages on/off for a first period greater than a reference value indicating a point, and holding the other driver stage off during that period; An inverter characterized in that the other driver stage is turned on and off during a second period in which the amplitude is not greater than the reference value, and the one driver stage is held off during that period. 3. The inverter according to claim 2, wherein the reference value is zero. 4. In the inverter according to any one of claims 1 to 3, when the magnitude of the deviation is outside a predetermined tolerance range, the driver drive control means controls the magnitude of the deviation to An inverter characterized in that the magnitude of the response current is changed in a direction that falls within the predetermined tolerance range. 5. In the inverter according to claim 4, the driver drive control means includes: (a) deviation tolerance range setting means for generating a tolerance range signal indicating an tolerance range of the magnitude of the deviation; and (b) the deviation signal. c) an out-of-range detection means connected to receive the tolerance range signal, and generates an out-of-range signal when the magnitude of the deviation is outside the tolerance range; and generating, in response to the out-of-range signal, an increase/decrease period signal defining a period of increase or decrease in the response current required to bring the magnitude of the deviation within the tolerance range. response current increase/decrease period forming means; d) connected to receive the increase/decrease period signal;
driver stage on/off control means for controlling on and off of the first driver stage and the second driver stage based on the increase/decrease period signal, the driver stage on/off control means being: a) connected to receive the increase/decrease period signal; and
on/off period forming means for generating an on/off period signal indicative of an on/off period of the first and second driver stages in response to the increase/decrease period signal; b) during the first period; energizing driver stage selection means for generating a selection signal specifying said one driver stage to be energized and specifying said other driver stage to be energized during said second period; c) said connected to receive an on/off period signal and the selection signal, and turn on/off one of the first and second driver stages designated by the selection signal in accordance with the on/off period. and driver stage on/off control means comprising: control signal generating means for generating said control signal to hold the other driver stage off; and driver stage on/off control means comprising: 6. In the inverter according to claim 5, the on/off period forming means is: a) connected to receive the selection signal, and the driver stage designated by the selection signal is In order to keep both the first and second driver stages off for a predetermined period from the time of change when changing from one of the two driver stages to the other, a dead time signal indicating the predetermined period is provided. generating dead time setting means, and the on/off period forming means causes the on/off period signal to indicate OFF during the predetermined period represented by the dead time signal. inverter. 7. In the inverter according to claim 6, the deviation tolerance range setting means is: (a) connected to receive the deviation signal and an upper limit value that defines the upper limit of the tolerance range; (b) first comparison means for generating an upper limit exceedance signal when the amplitude becomes higher than the upper limit value; (b) connected to receive the deviation signal and a lower limit value that defines the lower limit of the tolerance range; a) second comparison means for generating a lower limit exceedance signal when the amplitude of the deviation signal becomes lower than the lower limit value; a first increase/decrease period signal that is connected to receive a signal and assumes one of two states in response to the upper limit exceeded signal and assumes the other state in response to the lower limit exceeded signal; and a first flip-flop that generates a second increase/decrease period signal whose state is inverted. 8. In the inverter according to claim 7, the on/off period forming means: a) generates a clock signal of a predetermined frequency for limiting the frequency of switching between the on period and the off period; a) clock generating means; b) connected to receive said first increase/decrease period signal and said clock signal, and responsive to said first increase/decrease period signal only when said clock signal is present; c) a first flip-flop transitioning between and to generate a first on/off period signal for the first driver stage; c) receiving the second increase/decrease period signal and the clock signal; and transitioning between two states in response to the second increase/decrease period signal to generate a second on/off period signal for the second driver stage only when the clock signal is present. An inverter comprising: a second flip-flop that generates a second flip-flop; 9. In the inverter according to claim 8, the control signal generating means is connected to receive the first on/off period signal and the selection signal, and the selection signal is connected to the first on/off period signal and the selection signal. 1
(b) a first gate means for passing the first on/off period signal to generate the first control signal; b) the second on/off period signal; connected to receive the selection signal, and when the selection signal specifies the second driver stage;
second gating means for passing said second on/off period signal to generate a second said control signal;
An inverter featuring: 10. A polyphase inverter comprising an inverter according to any one of claims 1 to 9 for each phase to generate a polyphase response current that follows the waveform of a polyphase target current. .