JPH03105948A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To separate a power-supply line form a defective memory when a reconstituted logic circuit of a memory on a wafer scale has caused a failure and to reduce a wasteful power consumption by a method wherein a protective measure circuit composed of a fuse element, a resistance element and a logic output circuit is formed between a switching transistor and a control logic circuit. CONSTITUTION:In a semiconductor memory device provided with a switching transistor QA which supplies and controls a power supply to a memory circuit 11 and with a control logic circuit 12 which controls its gate, a protective measure circuit 13 is formed between the switching transistor QA and the control logic circuit 12. The protective measure circuit 13 is composed of the following: a connecting point P of a fuse element F and a resistance element R which have been connected in series between a power-supply line VCC and a ground line GND; an output point of the control logic circuit 12; and a logic output circuit 13a connected to a gate G of the switching transistor QA. When a failure is caused in the control logic circuit 12, the fuse element F is blown and the memory circuit 11 which has caused the failure is separated from the power- supply line VCC.

Description

[Detailed Description of the Invention] [Table of Contents] 4Q Industrial Application Fields Prior Art (Figure 5) Problems to be Solved by the Invention Means for Solving the Problems (Figure 1) Working Examples (Second Embodiment) Fig. 41A) Effects of the invention [Summary] Concerning the avoidance of defective memory when reconfiguring a semiconductor memory device, especially a wafer scale memory, or using it as a single memory device, Even in the event of a failure in a logic circuit, switching is applied to the power supply line in order to separate the power supply line from the defective memory, avoid the defective memory with good reproducibility, and reduce unnecessary power consumption. A memory circuit connected via a transistor, and i1I notation t. Q
In a semiconductor memory device comprising a switching transistor that controls power supply to ri'jIll'R and a control logic circuit that controls the gate of the switching transistor, protective measures are provided between the switching transistor and the control logic circuit. A circuit is provided, and the protection circuit includes a connection point between a fuse element and a resistance element connected in series between the power supply line and the ground line. It consists of a logic output circuit connected to the output point of the control logic circuit and the gate of the switching transistor. [Industrial Field of Application] The present invention relates to a semiconductor memory device, and more specifically, it relates to the reconstruction of a large scale memory and the avoidance of a defective memory in a cavity used as a single memory device. .

In recent years, the performance of computer systems has improved dramatically.
Memory usage per system is increasing rapidly.

For this reason, wafer scale memory was developed and manufactured as a large capacity and compact memory system.

By the way, when reconsidering wafer-scale memory,
There is a need for a device that can back up the reconfigurable logic circuit even if it fails.

[Prior Art] FIG. 5 is a schematic diagram of a conventional semiconductor memory device.

This figure shows an overall diagram of a wafer-scale memory and a configuration diagram of one memory circuit.

In the figure, a wafer-scale memory is constructed by connecting and reconfiguring a plurality of memory circuits 2 formed on a semiconductor wafer IE via communication paths 3 while avoiding defective memory circuits 5.

The memory circuit 2 includes a storage element CDRAM (CDRAM) 2a, a write/output control logic circuit (CONLOG2) 2b, a read/write logic circuit (CONLOG2) 2c, and a switching transistor Q8.

The switching transistor QA is a P-channel Mos transistor that controls power supply to the DRAM 2a, and is configured as a
○NJ, rOFF. is controlled by the gate control signal output from onLogic).

When the DRAM 2a cannot be supplied with power supply current due to an internal failure or the like, the C O N L O G l treats the DRAM 2a as a defective memory and cuts off the power supply to it. This allows DR
AM2a is excluded from the configuration of the wafer scale memory.

[The invention attempts to solve the problem] ) By the way, according to the conventional example, when excluding the defective DRAM 2a from the configuration of wafer scale memory,
A gate control signal of "L" level is input from CONLOGl to transistor QA. This causes the transistor QA to turn rOFF. and the DRAM2a and power line V
It is divided into C and C. However, even if CONLOGI receives logic that excludes the DRAM 2a from the configuration for some reason in the process, it may output rH to the transistor QA.

Similar to the cause of defects in DRAM2a, even with sufficient manufacturing control, transistors are formed on silicon wafers and contain defective crystals that originally occurred during the wafer process. It is thought that the cause was that the output of the transistor was inverted, or that an interlayer short circuit occurred due to some kind of process defect in the aluminum wiring, which caused the logical output to be inverted.

Therefore, even if the defective memory avoidance process is executed, the transistor QA is turned on, low, and ? ilti
lj; t-line VCC and DRAM2 that has caused an internal failure, etc.
a is connected. As a result, from the power line ■CC to the corresponding DR
A short current flows through AM2a. This causes problems such as a decrease in the voltage applied to other memory circuits and an increase in the power consumption of the entire wafer, especially during standby. The present invention was created in view of the problems of the conventional example, and is a wafer-scale memory reconfiguration theory Fl! To provide a semiconductor memory device that can reduce wasteful power consumption by separating a power supply line from a defective memory and avoiding the defective memory with good reproducibility even when a circuit breaks down. With the goal.

[Means to solve the problem]

FIG. 1 shows a principle diagram of a semiconductor memory device of the present invention.

The device includes a memory circuit 1811 connected to a power supply line vCC via a switching transistor QA, a switching transistor QA that controls the power supply to the memory circuit 11, and a control logic circuit that controls the gate of the switching transistor QA. In the semiconductor memory device having I2, a protection circuit 3 is provided between the switching transistor QA and the control 1n logic circuit 12, and the protection circuit 13 connects the power supply line VCC and the ground line GND. It is characterized by comprising a connection point P between a fuse element F and a resistance element R connected in series between them, a logic output circuit 13a connected to an output point of a control logic circuit 12, and a gate G of a switching transistor QA, and achieves the above object. be successful.

[Operation] According to the present invention, a protection circuit I3 consisting of a fuse element F, a resistor element R, and a logic output circuit ii'313 is provided between the switching transistor QA and the control logic circuit.

Therefore, under normal conditions when there is no failure in the control logic circuit 12,
As in the conventional example, the protection circuit 13 outputs the "L" level to the switching transistor QA, and the power supply line ■C
C and the memory circuit 11 in which the defect has occurred can be separated. In addition, in an abnormal situation where a failure occurs in the control logic circuit 12, by cutting the fuse element F, the protection countermeasure circuit 13 outputs the fL level to the transistor QA, and as in normal times, the faulty memory The circuit 11 can be separated from the electric fX-ray vCC.

Therefore, the defect avoidance function of the control logic circuit 2 can be backed up by the protection circuit 23.

As a result, it is not possible to control the system for some reason like in the conventional example. Even if the TI logic circuit 12 fails, it is possible to prevent wasteful power consumption from occurring in the C circuit 11 and the like.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

2 to 4 are diagrams for explaining a semiconductor memory device according to an embodiment of the present invention, and FIG. 2 shows a configuration diagram of the semiconductor memory device according to an embodiment of the present invention.

In the figure, 20 is a memory circuit, which constitutes a wafer scale memory. The memory circuit 20 has an I
Approximately 200 pieces are printed on a wafer.

2l is a DRAM (continuous write memory that requires memory retention operation) which is an example of the memory circuit lI, and has a capacity of several Mb.
It has a memory appearance of it.

22 is a reconfigured logic circuit (hereinafter referred to as CONLOGI) which is an example of the CONLOGI logic circuit 12;
Based on the external control signal S, the DRA. Connect M21 to power line ■C
The data input/output path is selected from among the memory circuits 20 that are separated from the memory circuit 20 or adjacent to each other in four directions in terms of hardware.

Reference numeral 23 denotes a fail-safe circuit which is an embodiment of the protection circuit 13, and serves as a backup for the CONLOG L's resetting function. The fugoil safety circuit 23 is
It consists of a two-input AND circuit 23a, a fuse element F, and a resistance element R. The output of the two-input AND circuit 23a is connected to the gate of the switching transistor QA, and one of its outputs is connected to the connection point P between the fuse element F and the resistance element R. The other input is C O N L
Connected to the output point of OG1. Fuse element F
and resistance element R are connected in series between the power supply line vCC and the ground line GND. As a result, when the fuse element F is not blown, the voltage appearing on the resistance element R, that is, the potential at the point P becomes "H" level. Furthermore, when fuse element F is blown, the potential at point P becomes "L".
It becomes a level. In the embodiment of the present invention, polysilicon-based resistance elements are used as the fuse element F and the resistance element R. Therefore, the function of the fail-safe circuit 23 is
When Gl is rH, level, P point is "H" level,
A gate control signal of rH level is output from the two-input AND circuit 23a. This is the operation when the i source is supplied to the DRAM21.

Also, CONLOCI is at "L" level. When the P point is at the "H" level, the two-man power AND circuit 23a outputs the "L" level. This is an operation to cut off the power supply to the DRAM 21, and is a case where CONLOG1 is operating normally.

Furthermore, CONLOG 1 is at “H” level and point P is at “L” level.
”, the two-input AND circuit 23a outputs “L”.
” level is output. This is a case where the power supply to the DRAM 21 is cut off, and the DR. A
Even though I gave the control information to cut off the power supply to M21, rH and Rehel were output from CONLOG1 for some reason. This is a case of refusal. As a result, the output of the fail-safe circuit 23 (at the time of abnormality) becomes the "L" level as the point P becomes the "L" level.

In addition, 24 is a write/continuation control logic circuit (hereinafter, CO
NLOG2), which controls data writing to and data reading from the DRAM 21. Also, CONLOG2, like DRAM2 1,
It is connected to power supply line VCC via switching transistor QA.

QA is a switching transistor that can be turned on or off by a gate control signal from the fail-safe circuit.
F. It works. In the embodiment of the present invention, the transistor QA is a P-channel type MOS transistor.

These constitute a semiconductor memory device that is a wafer scale memory with a memory capacity of 200 megabits.

By the way, the human output signal line of the memory circuit 20 is connected to the DRAM 21, CONLOG1 and CONL after the wafer process.
Based on the test results of the OG2, as shown in FIG. 5, the communication path 3 is selected and connected from the data input/output terminal 4 while avoiding defects that occur on the wafer process. At this time, it is necessary to stop the operational functions of the defective DRAM 21, etc.

Next, assuming that the DRAM 21 in FIG. 2 is a defective memory, the operation of stopping the function of the memory circuit 20 will be described.

FIG. 3 is an explanatory diagram of the normal operation of the semiconductor memory device according to the embodiment of the present invention.

In the figure, first, DRAM2 1 and C O N +-
○C the external control signal S that stops the operation function of G2.
Input to ON+, ○Gl. At this time, CONLOG
1 operates normally, an "L" level is output to the two-input AND circuit 23a. Also, point P is r }I J
held at the level.

Next, since the gate control signal from the two-input AND circuit 23a becomes "L" level, the transistor QA becomes rO
Performs FFJ operation.

Ko. ? l. ! ．． m-yori, DRAM2 1 and cONLOG
2 is separated from the power supply line vCC, and the memory circuit 20
Defects are avoided from wafer-scale memory components.

FIG. 4 is an explanatory diagram of the operation of the semiconductor memory device according to the embodiment of the present invention in the event of an abnormality.

The figure shows that even though the external control signal S that stops the operating functions of DRAM2 1 and CONLOG 2 is input to CONLOG 1, i9 C O N +-○G
1 indicates that the output is rH or level for some reason.

In such a case, in FIG.
cut. In the embodiment of the present invention, since the fuse element F is constituted by a polysilicon resistor element, it can be blown by, for example, a laser beam. As a result, point P is rH,
The signal changes from level to "L" level, and the output of the two-input AND circuit 23a becomes "L" level. This r l-,
The transistor QA to which the level has been input becomes rOFF and operates, and the DRAM21 and CONLOG2 operate as usual.
is separated from the electric wire ■CC. Therefore, the memory circuit 20 is protected from defects from wafer scale memory elements, and the power supply to the DRAM 21 and CONLOG 2 is cut off.

In this way, according to the embodiment of the present invention, the fuse element F. A fail-safe circuit 23 consisting of a resistive element R and a two-input AND circuit 23a is provided.

Therefore, under normal conditions when there is no failure in CONT or OGI,
As in the conventional example, the fail-safe circuit 23 outputs the "L" level to the transistor QA, thereby separating the power supply line CC from the defective DRAM 21 or CONLOC;2.

Also, CONT. ．． In the event of an abnormality in which a fault occurs in OG1, by cutting the fuse element F, a level rL is output to the fail-safe circuit 23 and the transistor QA, and the defective DRAM2 1 is outputted as in normal times.
and CONLOG2 can be separated from the power supply line VCC.

Therefore, the defect avoidance function of CONLOG 1 can be modified by the defect safety circuit 23. As a result, CON
Even if LOG1 fails, DRAM21 and CONL
It is possible to prevent wasteful power consumption caused by OG2 and the like. Note that the "l4" level related to the abnormality of CONLOGI can be set to rl- by canceling the external control signal S.
”Flip to Lehel. In this case as well, since the point P is fixed at r (-, level) due to the blowing of the fuse element F, there is no change in the level of r I- to the transistor QA. Also, wasted power consumption in CONLOGl is prevented. can do.

〔Effect of the invention〕

As described above, according to the present invention, even if the fail-safe logic circuit fails, the defective memory circuit can be disconnected from the power supply with good reproducibility by blowing out the fuse element of the fail-safe circuit.

Therefore, it is possible to deal with defective memory circuits by using the dual defect avoidance functions of the reconfiguration logic circuit and the fail-safe circuit.

This greatly contributes to the manufacture of semiconductor memory devices with high performance and low power consumption.

[Brief explanation of drawings]

FIG. 1 is a principle diagram of a semiconductor memory device according to the present invention, FIG. 2 is a horizontal view of a semiconductor memory device according to an embodiment of the present invention, and FIG. 3 is a semiconductor memory according to an embodiment of the present invention. FIG. 4 is an explanatory diagram of the operation of the device during normal operation; FIG. 4 is an explanatory diagram of the operation of the semiconductor storage device according to the embodiment of the present invention during abnormal conditions; FIG. 5 is a structural diagram of the semiconductor storage device according to the conventional example. . (Explanation of symbols) 11...Memory circuit, 12...Control logic circuit, 13...Protection countermeasure circuit, 13a...Logic output circuit, F...Heat element, R... Resistance element, QA... switching transistor, VCC... power line, GND... grounding line.

Claims (1)

[Claims] Switching transistor (QA) on power line (VCC)
a storage circuit (11) connected via a switching transistor (QA) that controls power supply to the storage circuit (11);
), a protection circuit (13) is provided between the switching transistor (QA) and the control logic circuit (12); The countermeasure circuit (13) includes a fuse element (F) and a resistance element (R) connected in series between the power supply line (VCC) and the ground line (GND), and the fuse element (F).
) and the connection point (P) of the resistance element (R), the output point of the control logic circuit (12) and the switching transistor (Q
A logic output circuit (13a) connected to the gate (G) of
) A semiconductor memory device comprising: