JPH03105463A - Arithmetic processor - Google Patents

Abstract

PURPOSE:To reduce a circuit scale, to reduce the number of constitution elements and cost and to improve reliability and an arithmetic processing speed by realizing a prescribed arithmetic processing by means of the same circuit scale and the number of constitution elements as one multiplier. CONSTITUTION:Dividends A and B are respectively supplied to input terminals 206 and 208, are timing-controlled in latch circuits 207 and 209 and are supplied to the side of the input terminals (0-side) of selectors 201-203 and the side of the input terminals (1-side). A multiplier K is inputted to an input terminal 210, and is converted into a control signal P in a converter 205. Then, bit data of the signal P is supplied to respective selectors as the switching control signals of respective selectors 201-203 through a latch circuit 211. When data is '0', the signal is connected to the 0-side of the input terminals and to 1-side when it is '1'. The outputs of respective selectors 201-203 are weighted in an adder 204 and added, whereby it comes to be M=(1-L) X A+L XB. The value of L becomes equal to the value of the control signal P, and it comes to be L=K.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to a digital arithmetic processing device that sequentially performs predetermined multiplication operations and addition operations, and in particular, it greatly simplifies its configuration and improves processing speed. The aim is to

(Prior art) Generally, two digital data A and B are stored as l-K:K.
When calculating new data M by mixing at a ratio of (0≦K≦1), an arithmetic expression such as M= (1-K)XA0KXB ・Equation (1) is used, and from this expression As is clear, two multiplication operations and one addition operation are required to obtain M.

In addition, when performing such arithmetic processing in real time using data A, B, and K that change sequentially, it is difficult to time-share two multiplication operations with one multiplier due to the calculation time. If this is not possible, two multipliers and one adder that multiply (1 - K) x A and KXB in parallel will be required, and such a digital arithmetic processing device is shown in Fig. 4. The following were known.

That is, as shown in the figure, this digital arithmetic processing device processes each 3-bit digital data (multiplicand) (A; aO+
a l+ a2) (B; t) o, bl+ bz),
Similarly, 3-bit digital data (multiplier) (K; ko,
k-+, k-2) at a ratio of l-K:K to obtain M
), and includes a first multiplier (101) that performs multiplication processing of (1-K)XA, a second multiplier (102) that performs multiplication processing of KXB, and each multiplier (101,
102), and an adder (103) that performs addition processing on the calculation outputs of 102).

In addition, in FIG. 4, the multiplier 1-K is expressed as J(jo, j
−＋． j−z).

In addition, each of the multipliers (101) and (102) is composed of nine AND circuits (hereinafter referred to as rAND circuits) as shown in the figure.
(104-112, 113-120) and each AN
An adder that adds the output of the D circuit with predetermined weighting
121, 122), and each of the AND circuits performs a logical product operation of JXA and KXB.

Furthermore, the first multiplier (101) has a latch circuit (
One of the digital data A is supplied via the latch circuit (123), and the digital data J is supplied via the latch circuit (124), and the second multiplier (102) is supplied with the digital data J via the latch circuit (125). The other digital data B is supplied via the latch circuit (126), and the digital data I<< is supplied via the latch circuit (126).

Note that the digital data J, that is, the complement data of K, supplied to the latch circuit (124) is converted into (1-
K) is obtained by subtraction processing (bit inversion).

Next, the operation of the digital arithmetic processing device configured as described above will be explained.

First, looking at the operation of the first multiplier (101), each of the AND circuits (104) of this multiplier (101)
~112), the above data A (
a o * a + + a 2 ) and J (jo ,
Performs an AND operation with j−+, j−2).

That is, each AND circuit (IO4-1) of the first group (101a) constituted by the AND circuits (104-106)
06) has the most significant digit (2°) of the multiplier J.
The bit data (j0) of the multiplicand A is supplied, and each bit data (a21 al, ao) of the multiplicand A is supplied, and an AND operation is performed on these bit data (a21 al, ao).

As a result, from each AND circuit (104 to 106) of this first group (101a), JOa21 JOall
Each logical product of JOaO is output.

Hereinafter, each AND circuit of the second group (10lb) composed of AND circuits (107 to 109) is used for the second digit (2
-') bit data (j −+ ) and the multiplicand A, and each AND circuit of the third group (101c) consisting of AND circuits (110-112) calculates the multiplier J
Bit data of the least significant digit (2-”) (j −z)
and the multiplicand A.

As a result, the second group (ioxb) and the third group (1
From each AND circuit (107 to 112) of 01c),
J-1a 2+ J-1a I+ J-1aO+
The ANDs of j-2a 2+ J-2al and j-2ao are output.

Note that the logical product operation by these AND circuits (104 to 112) is the multiplication of three-digit numbers, that is, a2
This corresponds to the operation of the X part in the operation al aQ.

Next, the adder (121) performs an addition operation corresponding to the Y part in the equation (2) above for each logical product obtained as described above, and S2, S1, So, S-1, S
Obtain an addition output (multiplication result) of -2.

The adder (121) is composed of a plurality of half adders (128 to 130), full adders (131 to 132), and an OR circuit (133), as shown in FIG. 5, for example. .

On the other hand, the second multiplier (102) is also
The first group (102) operates in the same way as the multiplier (101).
Each AND circuit (113) of a) to third group (102c)
~12l) to calculate the multiplicand B(bo, b++ b
2) and the multiplier K (k,), k-+, k-, z), and performs an addition operation using an adder (122), thereby producing an addition output (multiplication result).
j21tllto, t-+, t~2 is obtained.

Then, the addition output S2 calculated as described above
~S-+, t2 ~ t-2 are supplied to the adder (103) and subjected to an addition operation, whereby M (m 2 m , m ,), m-+m- is calculated using the above equation (1). z
).

(Problem to be Solved by the Invention) As described above, when performing arithmetic processing such as the above equation (1) at a sufficiently high speed using the conventional technology, two multipliers (101, 102) are required. and one adder (103) are necessarily required.

For this reason, the circuit scale of this type of digital arithmetic processing device becomes large, which causes an increase in cost, and
There is a problem in that reliability decreases because the number of elements that make up the circuit is extremely large.

Furthermore, each multiplier (101, 102) and an adder (10
3) are connected in a dependent manner, and each multiplier (101
, 102), it is necessary to perform an AND operation and an addition operation, so there is a problem that the arithmetic processing time in this digital arithmetic processing device, that is, the delay time from data input to data output becomes long.

(Means for Solving the Problems) The present invention has been made in view of the above-mentioned circumstances, and it is possible to reduce costs by reducing the circuit scale and the number of constituent elements, and to improve reliability. It is an object of the present invention to provide a digital arithmetic processing device that can improve the processing speed and further shorten the processing speed.

In order to achieve this object, the present invention has one or more multipliers and a plurality of multiplicands as input, and outputs a product of a multiplicand of 1 and a multiplicand of -, and a complement of the multiplier of 1 and other multiplicands. an arithmetic processing device that adds and outputs a multiplicand and a multiplication output, and selectively outputs the one multiplicand or another multiplicand according to a plurality of control signals generated based on the one multiplicand. The present invention provides an arithmetic processing device characterized by comprising selectors and an adder that adds the outputs of these selectors.

(Function) According to the present invention, by using a selector that can be switched appropriately according to a control signal based on a multiplier, it is possible to eliminate the need for overlapping parts in conventional processing devices of this type, thereby reducing the circuit scale. At the same time, the number of constituent elements is significantly reduced.

In addition, since the arithmetic processing for the multiplicand A and the arithmetic processing for the multiplicand B are executed simultaneously, the time required for the calculation shown in the above equation (1) is significantly shortened.

(Embodiment) Hereinafter, a preferred embodiment of the arithmetic processing device according to the present invention will be described as a first embodiment.
This will be explained in detail with reference to FIGS.

The arithmetic processing device according to this embodiment uses 3-bit digital data (multiplicand) A (a21 a It ao), B
(b2.b,, 3-bit digital data (multiplier) like b(,) K (k O , k-+, k-z)
It is a digital arithmetic processing device that executes arithmetic processing such as the above equation (1) based on the first to third selectors (201, 202, 203) and an adder (204).
) and the multiplier K to each of the selectors (201, 20
A converter (
205).

That is, one of the multiplicands A is input to the input terminal (206).
is supplied, and each bit data (a2,
aI+aO) is latched by a latch circuit (207) and subjected to timing control, and then connected to one input terminal (“O” side) of each selector (201 to 203) via a bus line.
are supplied to each.

Similarly, the other multiplicand B is supplied to the other input terminal (208), and each bit data (b2, b2,
t) I+bo) is latched by the latch circuit (2.09) and controlled to be synchronized with the latch output timing of the multiplicand A, and then output to each of the selectors (20l to 20).
3) are respectively supplied to the other input terminal (“1” side).

Furthermore, each bit data of these multiplicands A and B (a2
1 a,,a,))(b2,bO,b1) is weighted as (2'', 2', 2°).

Further, the multiplier K is supplied to the input terminal (210),
This multiplier K is supplied to the converter (205) and converted into a control signal P.

This converter (205) has two O
It is composed of an R circuit and a predetermined bus line, and each bit data of the multiplier K (k or k-l* k-
z) and each bit data of the control signal P (pp-+,
p-Ijp-2) means that pp-2 is k. Corresponding to P-
+ is k. corresponds to the logical sum output of and k-+, and p-2 is k
It is configured to correspond to the logical sum output of o and kz.

Here, each bit data (1)I)- of the control signal P
2, p-1. The weighting for I)-2) is (2-2
．． 2-1. 2-2), and the sum of these (2-"+2-'+2-2) corresponds to rlJ of the coefficient (1-k) in equation (1) above, and the value of k is preserved. That is, for example, (k O , k−+,
k-z) is (010), the value of k is OX2°
+]X2'+OX2-2=2-', and the bit data of P in this case (pp2+ p l, p-2)
is converted by the converter (205) as described above into (
010), so the value of P is OX2-"+IX2+O
X2-2=2-', and the value of K and the value of P match and are stored.

Then, each bit data in the control signal P as described above (1)I) -2 1 1) -1 1 1)
-2) is supplied to each selector as a switching control signal for each of the selectors (20l to 203) as shown in the figure, through a latch circuit (21 1), and each selector receives rOJ when the supplied data is rOJ. connects the switching terminal to one input terminal ("O" side), and in the case of "1", connects the switching terminal to the other input terminal ("1" side).

In this way, each of the selectors (201 to 203) selects each bit data ( p p-2 ) of the supplied control signal P.
, p-1. The corresponding bit data of the multiplicand A or B is selectively output depending on the value of 1)-2) (“1” or “0”).

Therefore, the output value of the first selector (201) is (1-p-+)XA+p-lXB
... Expressed by equation (3), similarly, each output value of the second and third selectors (202, 203) is (1-1) -2 ) X A + 1) -2 X
B...(4) Formula (II) p-2) X
A+pp-2XB... Expressed by equation (5).

Then, each data d, . d 6
, d-+, e (,, e-11 8-2, f
o, f-+, and f-z are added with predetermined weighting in an adder (204) at the subsequent stage.

That is, each bit data of the control signal P ( p p −
2, 111-1, I)-2), as explained earlier, (2-2. 2-1. 2)
-2), and each selector (201 to 20
For the output value of 3), the supplied bit data is weighted.

Therefore, the first to third selectors (201 to 203)
Each output value considering the weighting is 2”X ((1-p+) XA+p-+XB]...
(6) Formula 2-”X [(1 p 2 ) XA+p-
2XB+...(7) Formula 2-2X [(1 1)! ]
-2) XA + I) I) -2
, dO, d-1) ("O+ e-1, e-2) (r0
, f −+ , f −2 ) correspond to the weighting coefficients.

The adder (204) that adds the respective weighted output values includes two 1-bit half adders (212, 213) and four full adders (212, 213) as shown in FIG. 214, 215, 216, 21
7), and its input/output relationship is connected as shown in the figure to produce a 5-bit calculation output M (m 2 , m l,
m 6 , m-+, m-2) are calculated.

As is clear from the above explanation, the calculation output M in the digital calculation processing device configured as described above is the sum of the above equations (6), (7), and (8).

That is, M = Equation (6) + Equation (7) 10 Equation (8) = [(2-'+2-2+2-2)-(2-'p-++
2-2p-z+2-2pp-2) 1xA+ (February p-
++2-2p-z+2-2pp-z) XB, and 2""p. -++2-2+2-2pp-+
=L, then M= (1-L) xA+LxB...Equation (9) is obtained.

Here, the value of L is the control signal P (1)I)-21 p-
++ 1)-2) value (2-2pp-2+2-'p, +
+2−”p−2), and this value preserves the value of K (2°k.+2−′k+:l”k−z) as explained earlier, so L=K. .

In other words, when ko=1, the input condition of K (0koK
<1), k-+=O, k-z=o, and from the configuration of the converter (205) shown in FIG. 1, pp-+=l, p-1
:1, p-2:l, so L=2-'p-++
2-2p-2+2-”pp-z=l=K...(10)
The formula becomes

In addition, in the case of ko-O, that is, in the case of O<K<1, the control signal P (1
)1)-2, p-+. pI) in pp-z)
-2j p-11p -2 == k-2, so L = 2-'p-++2-2p-2+0= 2-' k
-+ +p-2k-22K...Equation (l1) is obtained.

Therefore, under the input condition of K, L = K always, so L in the above equation (9) can be replaced with K, and according to the digital arithmetic processing device having the configuration shown in Fig. 1, M = (1-L)xA×LxB= (1-K)xA+K
A calculation output M can be obtained when the calculation process xB is executed.

In this way, according to the digital arithmetic processing device according to the present embodiment, the arithmetic processing as in equation (1) is performed by using the selectors (201 to 203) in common for the arithmetic processing for A and the arithmetic processing for B. By doing so, there is no need to provide two independent multipliers as in the conventional example.

Therefore, according to this embodiment, the circuit scale and number of constituent elements of this type of digital arithmetic processing device can be significantly reduced and simplified.

Furthermore, since the configuration can be simplified in this way, the calculation processing time can naturally be significantly shortened. That is, in the conventional example shown in FIG. 4, it was necessary to add the multiplication output from each multiplier in the adder in the subsequent stage, but according to this embodiment, such a Since there is no need for anything equivalent to an adder, the time required for this adder is no longer necessary, and the time required for arithmetic processing can thereby be significantly shortened.

These effects are particularly effective when applied to digital circuits used in video signal processing, which require size reduction and high-speed processing of digital data.

Note that in the above embodiment, the multiplier J for the multiplicand A is 1-
Although we have explained the case where it is set as the value of K, this multiplier J can also be set as n-K, and in that case, the value of the control signal P (pp 21 P-++ p-2) is set to n. Bye.

? In addition, each of the selectors (201 to 203) may select, for example, each bit data (p p -2) of the control signal P.
1p-1, p-2) respectively gate-controlled
It may be configured with an ND circuit.

(Other examples) Next, a second embodiment of the present invention will be described with reference to FIG.

FIG. 3 is a block diagram showing the digital arithmetic processing device according to this embodiment, and in the same figure, 301 is the first multiplicand A (a21 al+ao), and 302 is the second multiplicand B.
( b 2 + b 1 lb o ), 303 is the third multiplicand X ( X 2 1 X I + X o
), 304 is the fourth multiplicand Y (721 V I+
3'o), 305 is the first multiplier K
(k ■, k-+, k-z), 306 is the second multiplier L (j! 0 + 1!-+ + f -2
), 307, 308, 309, respectively input terminals.
are selectors that select and output one of the four multiplicands, and 310 and 311 are selectors (307 to 311) that select and output one of the four multiplicands.
312 is an adder for adding the outputs of the selectors (307 to 309);
3 is a terminal for outputting the calculation result.

The structure and operation of each of the converters (311, 310) are similar to the converter (205) in the previous embodiment, and the combination of the outputs of these converters (310, 311) (q 1 + I ) l) performs switching control of each of the selectors (307 to 309).

The operation will be explained below.

Each bit data of the four multiplicands A, B, X, and Y input from terminals 301, 302, 303, and 304 is distributed and supplied to each terminal of selectors 307, 308, and 309, respectively. Each selector has two
Switching is controlled by a bit control signal (q + + p + ), and one of the four multiplicands is selected and output. The output of each selector is multiplied by a weighting factor of 21, corresponding to its control signal q+p.

For example, the output of the selector 307 is expressed as equation (l2).

2-'(q-1'p-1'A+q-1"p-1'B+
q-1'p-1'X + q-+・p. -+-Y)
...Selectors 308, 3 as in equation (12)
The output of 09 is as shown in equations (13) and (14.).

2-” (Q-2●fragrance-2-A+q-zφp-2●B −
t- q-2●p-2●X -1- q-2・p-2・
Y) ...(13) Formula 2-2(QQ-2●[
)-2 in A+qq-2-pp-2●B→qq-2'11
11 r)-2・x + q q.・pl)-2・Y)
...(l4) The output of the above selector is the adder 312
M=m 2 m 1 to the terminal 313
It is output as m o- m-+m-2. The function of the adder 312 is exactly the same as the adder 204 in the first embodiment.

On the other hand, the control signals (q1,
p+), but as mentioned earlier, in this embodiment, the method of generating the control signal from the multiplier is exactly the same,
Blocks 310 and 311 are the same as the converter (205) in the first embodiment. However, in this embodiment, two multipliers K and I- are provided manually, and a selector control signal is generated from each multiplier. Therefore, since the number of control signals per selector is 2 bits, the number of selector inputs can be increased to 22-4. This means that when the number of multiplier inputs is 3, the number of selector inputs is 8 (2”).
This means that the number of input multiplicands can be up to eight.

Since the output of each selector has a different numerical weight, the 2-bit bare control signal must always have the same weight, that is, it must be a combination of q+ and p1 with the same subscript (q-1p-2 is not allowed to become a bear).

In this embodiment, such a 2-bit control signal is used, so when the output calculation result is expressed using multipliers K and L, as shown below, when L=0, M = A+K - B in (1-K)...(15) formula i- If = i, M= (1-K)・X+K-Y...(16) formula K
In the case of =O, M=(1-L)・A+L-X...(17) Formula K=
In the case of 1, M= (1-L) -B+L●Y...(l8) Shikicho, in the case of =K, M=(1-K)●A+K●Y...(l9) The formula becomes

In this way, according to this embodiment, four
Various arithmetic operations such as those shown in (15) to (19) above can be performed using the three multiplicands A, B, X, and Y and the two multipliers K and L.

In addition, although this embodiment has been described for the case where there are two multipliers, if the number of multipliers is further increased to n,
It is possible to handle as many multiplicands as possible, and furthermore, by appropriately setting the connection relationship of the selectors, it is possible to perform arithmetic processing in any combination.

Furthermore, the present invention may be applied to analog arithmetic processing devices.

(Effect of the invention) As is clear from the above explanation, the arithmetic process (1-K)xA+KxB is executed using a multiplier of 1 or more (for example, K, 0<K<1) and multiplicands (for example, A, B). The structure of an arithmetic processing unit, which conventionally consisted of two multipliers and l adders, can be changed to a circuit scale and number of components equivalent to one multiplier according to the present invention. This makes it possible to reduce the cost of this type of device and improve its reliability.

Further, according to the present invention, by adopting such a configuration, the time required for the above-mentioned arithmetic processing can be significantly shortened.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention;
The figure is a block diagram showing the internal configuration of the adder used in Fig. 1, Fig. 3 is a block diagram showing the second embodiment of the present invention, and Fig. 4 is a block diagram showing the internal configuration of the adder used in Fig.
The figure is a block diagram showing a conventional example, and FIG. 5 is a block diagram showing the internal configuration of the adder used in FIG. 4. 201, 202, 203, 307, 308, 309 ・・・・・・・・・・・・
・・・・・・・・・・・・・・・ Selector 204
, 313・・・・・・・・・・・・・・・・・・
・・・・・・・・・・・・・・・・・・・・・・・・
... Adder 205, 310, 311 ...
・・・・・・・・・・・・・・・・・・・・・・・・
...Converter procedure amendment (voluntary)

Claims (1)

[Claims] Having one or more multipliers and a plurality of multiplicands as input,
An arithmetic processing device that adds and outputs a multiplication output of a multiplier of 1 and a multiplicand of 1, and an output of a multiplication of the complement of the multiplier of 1 and another multiplicand, the processing device being generated based on the multiplier of 1. An arithmetic processing device comprising a selector that selectively outputs the one multiplicand or another multiplicand according to a plurality of control signals, and an adder that adds the outputs of these selectors.