JPH03102866A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To allow a sufficient functional test in a wafer conduction regardless of the number of input/output pins by setting a potential of a plurality of source lines at a normal operating voltage, and the potential of another source line at a level less than the low output logic level and more than the normal operating voltage of an emitter follower, upon the functional test of a logic circuit. CONSTITUTION:An emitter follower EF1 consists of an npn transistor T4, whose collector is connected to the source line VCC and base to the collector of a transistor T2, and two terminal resistors RP1, RP2 connected to the emitter (OUT) of the transistor T4. One resistor RP1 is terminated to a source line VEE1, and the other resistor RP2 to a source line VEE2 of the second low potential. When the high output logic level of the emitter follower EE1 is VOH and the low one VOL, 0>VOH>VOL>VEE2>VEE1 holds in a functional test, and 0>VOH>VOL> VEE2>VEE1 holds in a practical use.

Description

[Detailed Description of the Invention] [Summary] Semiconductor integrated circuits, especially L with high power consumption such as ECL
Regarding the technology for testing SI, the purpose is to perform sufficient functional tests in wafer state regardless of the number of input/output bins, and the purpose is to test semiconductor integrated circuits that include an emitter follower in the logic circuit, and where the termination of the emitter follower is a plurality of power supply lines each having a plurality of variable potentials, each of which is terminated by a plurality of resistors, the potential of one of the plurality of power supply lines is is set to a normally used voltage, and the potentials of other power supply lines are set to levels below the lower output logic level of the emitter follower and above the normally used voltage.

[Industrial application field]

The present invention relates to semiconductor integrated circuits, and in particular to a technique for testing large-scale integrated circuits (LS1) such as emitter-coupled logic circuits (ECLs) that consume large amounts of power.

In recent ECL-LSIs, in order to maintain high speed,
Efforts are being made to increase integration without reducing the current/power per gate. Therefore, it is necessary to supply large current/power even during testing.

[Prior art and problems to be solved by the invention]

In the conventional wafer condition test (wafer blobbing test), a probe card equipped with a probe needle is used to supply power (current) to each chip in the same way as in the actual usage condition, and each circuit is tested normally. We are conducting functional tests to see if it works properly.

However, as mentioned above, when increasing the current/power,
Since the current is supplied through the probe needle, a limit is imposed on the current that can be passed through the probe needle.

On the other hand, even if an attempt is made to increase the number of probe needles due to this limitation, the total number of probe needles will be limited due to reasons such as physical inability to arrange them, and as a result, the number of input/output signals will be reduced. This has been a problem because it goes against the reality that in random logic circuits, as the degree of integration increases, the number of input/output signals must also increase.

In addition, increasing the number of needles when probing a wafer is expensive, and the needles themselves must be made thinner, which reduces durability and further increases costs.

Therefore, it is not possible to supply current while ensuring the number of input/output signals, and it becomes impossible to perform a sufficient functional test in the wafer state. This leads to a decrease in yield in the next process and is also a factor in increasing costs.

The present invention was created in view of the problems in the prior art, and an object of the present invention is to provide a semiconductor integrated circuit that can perform a sufficient functional test in a wafer state regardless of the number of input/output pins.

[Means to solve the problem]

In order to solve the above problems, the present invention reduces the current of an emitter follower, which requires a large amount of current in an ECL circuit or the like, during a functional test.

Therefore, according to the present invention, there is provided a semiconductor integrated circuit including an emitter follower in a logic circuit, the semiconductor integrated circuit having a plurality of resistors for terminating the emitter follower, and a plurality of resistors each terminating the emitter follower. A power supply line having a variable potential is provided, and during a functional test of the logic circuit, one potential of the plurality of power supply lines is set to a normally used voltage, and the potential of the other power supply line is set to a low level of the emitter follower. There is provided a semiconductor integrated circuit characterized in that the output logic level is set to a level lower than the output logic level of the output voltage and a level higher than the normally used voltage.

[For production]

According to the above-described configuration, during a functional test, the potential of one power supply line (denoted as A) is set to the normally used voltage, and the potential of the other power supply line (denoted as B) is set to a level exceeding the normally used voltage. Set. Therefore, the voltage applied to the resistor terminated in the power supply line B is smaller than the voltage applied to the resistor terminated in the power supply line A, so that the current flowing through the resistor is relatively reduced. Therefore, the overall current/power consumed by the emitter follower is reduced.

As a result, even if the LSI has many output pins and consumes a large amount of current (power) during actual use, it is possible to conduct sufficient functional tests in the wafer state without increasing the number of power supply pins. restrictions can be relaxed.

Note that other structural features and details of the operation of the present invention will be explained using the embodiments described below with reference to the accompanying drawings.

〔Example〕

FIG. 1 shows the configuration of an ECL circuit as an embodiment of the present invention.

The circuit of this embodiment is composed of a current switch CSW and an emic follower IEFI.

The current switch CSttl consists of a pair of emitter-coupled npn transistors T1 and T2 that respond to a human input signal IN and a reference signal Vref, respectively, and a high potential power supply VCC' (=OV, GND) t!
= } Resistors RC1 and RC2 connected between the respective collectors of transistors T1 and T2, and transistors T1.
Common emitter of T2 and first low potential power supply line vEE
1 (=-4.5V) (an npn type transistor T3 and a resistor RE that respond to a constant voltage signal vCS).

In the emitter follower EFI, the collector is the power line V
It consists of an npn type transistor T4 connected to CC and whose base is connected to the collector of the transistor T2, and two terminating resistors RP1 and RP2 connected to the emitter (output OMIT) of the transistor T4. One resistor RPI is terminated to the power supply line VEEI, and the other resistor RP2 is terminated to the second low potential power supply line V
Terminated to EB2.

Set the high output logic level of the emitter follower EFI to V
OI{ , assuming that the low output logic level is V[I1, the currents L and I flowing through the resistors RP1 and RP2, respectively
2 is expressed by the following formula.

(a) When the output logic level is VDH, 1, = (VOH-VEE1)/RPI...
(1) I2=(VOH-VEE2)/RP2 ・-・・
-(2)(b) When the output logic level is VOL, 1, =(VOL-VEB1)/RPI -=-=-(3
)12=(VOt, -VEE2)/RP2 -...
・(4) The potential VEEI of the first low potential power supply line is
This is the power supply voltage during actual use (normally used voltage). Furthermore, the potential VEE2 of the second low potential power supply line is set to a level below the low output logic level VOL and above the normally used voltage (VEE1) during the functional test of this circuit, and during actual use. is set to the normally used voltage.

That is, during the functional test, 0 > VOH > VOL ≧VE [E2) VEEI-=
There is the relationship (5), and in actual use, 0 > VOH > VOL > VEE2 = VBE1
- There is the relationship (6).

Termination resistor RPI. RP2 does not necessarily have to have the same resistance value, but is set to have the resistance value in actual use when connected in parallel to the same potential VEAL.

The resistor RPI connected to the power supply line VEEI of the normally used voltage is set to a resistance value as large as possible to perform a functional test. This makes it possible to reduce the current rI flowing through the resistor RPI during testing.

In actual use, the current II is increased in order to operate at high speed, but there is no problem even if the current I1 is small during a function test at low speed.

On the other hand, since the potential of the power supply line VEE2 is set higher than the potential of the power supply line VIEBI during the test, the voltage applied across the resistor RP2 can be made relatively small. Therefore, the current I2 flowing through the resistor RP2 can be suppressed to a small value.

Therefore, the overall current/power consumed by the emitter follower BFI is reduced. In particular, V6B2=vO
(see equation (4)), the output logic level is VOL
At the time, the current I2 flowing through the resistor RP2 becomes 0, and the current/power consumption is further reduced.

From equations (1) to (6) described above, the current ratio during testing to that during actual use is expressed by the following equation.

Current ratio = 1 - 2 RPI (VEEI - VEE2
)/(RPI +RP2)/(2 VEEI −
VOI{-VOL) Therefore, # end resistor RP1,
By appropriately selecting each resistance value of RP2, the current ratio can be varied in response to changes in the potential of the electric and cooling lines VEE2, as shown in FIG.

Incidentally, FIG. 5 shows an example of a conventional ECL circuit for comparison with the circuit structure of this embodiment.

In the conventional type, there is only one emitter/follower leaf termination resistor Rp and the corresponding power supply line VEB, so the resistance value of resistor Rp is set to a small value to increase the speed in actual use. In this case, a large current flows during the test, which causes various problems as described in the related art. On the other hand, if the resistance value of the resistor Rp is set to a large value, the current flowing during actual operation will decrease, which will impede speeding up. In other words, it is not possible to select an appropriate resistance value that is convenient for both testing and actual use.

On the other hand, in this embodiment, two systems are provided for the resistor for the # end of the emitter follower and the power supply line corresponding thereto, so that the inconvenience seen in the conventional type can be solved.

Note that in the embodiment described above, the emitter follower [EF1
The power supply line terminated with the resistor RPI and the power supply line connected with the emitter resistance Rε of the current switch CSlil are at the same potential VIEEI. Resistance R
A third low potential power supply line VEE3 (<V
BE1) may be provided separately.

FIG. 4 shows another modification, and shows a circuit configuration in which the emitter follower BF2 has an npn type transistor T5 that constitutes a constant current source together with the terminating resistors RP1 and RP2.

In this case, if the potential VεE2 of the second low-potential power supply line is set to be equal to the emitter potential VE of the transistor T5 (VEE2=Vε) during the test, the current I2 flowing through the resistor RP2 becomes 0. You can increase your effectiveness more easily.

〔Effect of the invention〕

As explained above, according to the present invention, even for LSIs with many output pins and large current (power) consumption during actual use, sufficient functional tests can be performed in the normal state without increasing the number of power supply pins. , the restrictions on probe needles can be relaxed. Furthermore, in the case of the same number of pins, it is possible to test an LSI with more human output pins.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the configuration of an ECL circuit as an embodiment of the present invention, FIG. 2 is a graph for explaining the effect of the embodiment in FIG. 1, and FIG. 4 is a circuit diagram showing the configuration of a second modification of the embodiment shown in FIG. 1; FIG. 5 is a circuit diagram showing an example of the configuration of a conventional ECL circuit. , is. (Explanation of symbols) EF1, EF2...emitter follower, RP1,
RP2...# end resistor, VEB1, VEE2
- '14m 5 I:' (Potential), VOL...
Low output logic level, T5...transistor (constituting a constant current source), VB
...Emitter potential (of transistor T5).

Claims (1)

[Claims] 1. Emitter followers (EF1, EF2) in logic circuit
A semiconductor integrated circuit including a plurality of termination resistors (RP) of the emitter follower.
1, RP2), and includes a power supply line having a plurality of variable potentials (VEE1, VEE2) where the plurality of resistors are respectively terminated, and when testing the function of the logic circuit, one of the plurality of power supply lines One potential (VEE1) is set to the normally used voltage, and the potential of the other power supply line (VEE2) is set to a level below the lower output logic level (VOL) of the emitter follower and at the normally used voltage (VEE1). ) A semiconductor integrated circuit characterized by being set at a level exceeding ). 2. The resistor (RP1) that is terminated to the power line set to the normal operating voltage (VEE1) has a resistance value larger than that of the other terminating resistor (RP2) within the range where the functional test can be performed. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is set. 3. When testing the function of the logic circuit, the potential of the other power supply line (VEE2) is set to the emitter follower (EFI).
3. The semiconductor integrated circuit according to claim 2, wherein the semiconductor integrated circuit is set to a low output logic level (VOL) of ). 4. The emitter follower (EF2) is a transistor (T5) that constitutes a constant current source together with the terminating resistor.
3. The semiconductor integrated circuit according to claim 2, wherein the potential (VEE2) of the other power supply line is set to the emitter potential (VE) of the transistor during a functional test of the logic circuit.